summaryrefslogtreecommitdiff
path: root/arch/arm/mach-mvebu/include/mach
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-mvebu/include/mach')
-rw-r--r--arch/arm/mach-mvebu/include/mach/cpu.h1
-rw-r--r--arch/arm/mach-mvebu/include/mach/soc.h22
2 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index 674fdaa0d3..6fa41736e2 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -117,6 +117,7 @@ unsigned int mvebu_sdram_bs(enum memory_bank bank);
void mvebu_sdram_size_adjust(enum memory_bank bank);
int mvebu_mbus_probe(struct mbus_win windows[], int count);
int mvebu_soc_family(void);
+u32 mvebu_get_nand_clock(void);
int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index a29e5dcedc..6115d6e58d 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -11,6 +11,8 @@
#ifndef _MVEBU_SOC_H
#define _MVEBU_SOC_H
+#define BIT(x) (1 << (x))
+
#define SOC_MV78460_ID 0x7846
#define SOC_88F6810_ID 0x6810
#define SOC_88F6820_ID 0x6820
@@ -25,6 +27,9 @@
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
#endif
+/* Armada XP PLL frequency (used for NAND clock generation) */
+#define CONFIG_SYS_MVEBU_PLL_CLOCK 2000000000
+
/* SOC specific definations */
#define INTREG_BASE 0xd0000000
#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
@@ -53,6 +58,7 @@
#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
+#define MVEBU_CLOCK_BASE (MVEBU_REGISTER(0x18700))
#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
@@ -64,6 +70,7 @@
#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
#define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000))
#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
+#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
@@ -72,6 +79,21 @@
#define MBUS_BRIDGE_WIN_CTRL_REG (MVEBU_REGISTER(0x20250))
#define MBUS_BRIDGE_WIN_BASE_REG (MVEBU_REGISTER(0x20254))
+#define MVEBU_SOC_DEV_MUX_REG (MVEBU_SYSTEM_REG_BASE + 0x08)
+#define NAND_EN BIT(0)
+#define NAND_ARBITER_EN BIT(27)
+
+#define ARMADA_XP_PUP_ENABLE (MVEBU_SYSTEM_REG_BASE + 0x44c)
+#define GE0_PUP_EN BIT(0)
+#define GE1_PUP_EN BIT(1)
+#define LCD_PUP_EN BIT(2)
+#define NAND_PUP_EN BIT(4)
+#define SPI_PUP_EN BIT(5)
+
+#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
+#define NAND_ECC_DIVCKL_RATIO_OFFS 8
+#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
+
#define SDRAM_MAX_CS 4
#define SDRAM_ADDR_MASK 0xFF000000