summaryrefslogtreecommitdiff
path: root/arch/arm/mach-rockchip/rk3328/rk3328.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-rockchip/rk3328/rk3328.c')
-rw-r--r--arch/arm/mach-rockchip/rk3328/rk3328.c62
1 files changed, 53 insertions, 9 deletions
diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
index 1cf829dc34..592f287613 100644
--- a/arch/arm/mach-rockchip/rk3328/rk3328.c
+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
@@ -4,12 +4,24 @@
*/
#include <common.h>
+#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_rk3328.h>
+#include <asm/arch-rockchip/uart.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
+#define CRU_BASE 0xFF440000
+#define GRF_BASE 0xFF100000
+#define UART2_BASE 0xFF130000
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "rksdmmc@ff520000",
+ [BROM_BOOTSOURCE_SD] = "rksdmmc@ff500000",
+};
+
static struct mm_region rk3328_mem_map[] = {
{
.virt = 0x0UL,
@@ -32,20 +44,52 @@ static struct mm_region rk3328_mem_map[] = {
struct mm_region *mem_map = rk3328_mem_map;
-int dram_init_banksize(void)
+int arch_cpu_init(void)
{
- size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
-
- /* Reserve 0x200000 for ATF bl31 */
- gd->bd->bi_dram[0].start = 0x200000;
- gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
+ /* We do some SoC one time setting here. */
return 0;
}
-int arch_cpu_init(void)
+void board_debug_uart_init(void)
{
- /* We do some SoC one time setting here. */
+ struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
+ struct rk_uart * const uart = (void *)UART2_BASE;
+ enum{
+ GPIO2A0_SEL_SHIFT = 0,
+ GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
+ GPIO2A0_UART2_TX_M1 = 1,
- return 0;
+ GPIO2A1_SEL_SHIFT = 2,
+ GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
+ GPIO2A1_UART2_RX_M1 = 1,
+ };
+ enum {
+ IOMUX_SEL_UART2_SHIFT = 0,
+ IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
+ IOMUX_SEL_UART2_M0 = 0,
+ IOMUX_SEL_UART2_M1,
+ };
+
+ /* uart_sel_clk default select 24MHz */
+ writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
+
+ /* init uart baud rate 1500000 */
+ writel(0x83, &uart->lcr);
+ writel(0x1, &uart->rbr);
+ writel(0x3, &uart->lcr);
+
+ /* Enable early UART2 */
+ rk_clrsetreg(&grf->com_iomux,
+ IOMUX_SEL_UART2_MASK,
+ IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A0_SEL_MASK,
+ GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A1_SEL_MASK,
+ GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
+
+ /* enable FIFO */
+ writel(0x1, &uart->sfe);
}