diff options
Diffstat (limited to 'arch/arm/mach-uniphier/clk')
| -rw-r--r-- | arch/arm/mach-uniphier/clk/pll-base-ld20.c | 6 | ||||
| -rw-r--r-- | arch/arm/mach-uniphier/clk/pll-ld11.c | 13 | ||||
| -rw-r--r-- | arch/arm/mach-uniphier/clk/pll-ld20.c | 21 | ||||
| -rw-r--r-- | arch/arm/mach-uniphier/clk/pll-pxs3.c | 55 |
4 files changed, 90 insertions, 5 deletions
diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c index 697eb7aabf..3aa42f8bfd 100644 --- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -88,7 +88,7 @@ int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) if (!base) return -ENOMEM; - tmp = readl(base + 8); /* SSCPLLCTRL */ + tmp = readl(base + 8); /* SSCPLLCTRL3 */ tmp &= ~SC_PLLCTRL3_REGI_MASK; tmp |= regi << SC_PLLCTRL3_REGI_SHIFT; writel(tmp, base + 8); @@ -133,9 +133,9 @@ int uniphier_ld20_dspll_init(unsigned long reg_base) if (!base) return -ENOMEM; - tmp = readl(base + 8); /* DSPLLCTRL2 */ + tmp = readl(base + 4); /* DSPLLCTRL2 */ tmp |= SC_DSPLLCTRL2_K_LD; - writel(tmp, base + 8); + writel(tmp, base + 4); iounmap(base); diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c index 02befa298b..1a7ec29525 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld11.c +++ b/arch/arm/mach-uniphier/clk/pll-ld11.c @@ -4,13 +4,24 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> +#include <linux/delay.h> #include <linux/io.h> #include "../init.h" #include "../sc64-regs.h" #include "pll.h" +/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ +#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */ +#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */ +#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1460) /* DDR memory */ + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + void uniphier_ld11_pll_init(void) { uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2); /* 2000MHz -> 1960MHz */ diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c index 121a3690e8..5e072c6dff 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-ld20.c @@ -5,12 +5,31 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> +#include <linux/delay.h> #include "../init.h" #include "../sc64-regs.h" #include "pll.h" +/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ +#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ +#define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */ +#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */ +#define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */ +#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */ +#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */ +#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */ + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + +/* PLL type: DSPLL */ +#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) +#define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) + void uniphier_ld20_pll_init(void) { uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); diff --git a/arch/arm/mach-uniphier/clk/pll-pxs3.c b/arch/arm/mach-uniphier/clk/pll-pxs3.c index 201d3517a8..e84d52b80f 100644 --- a/arch/arm/mach-uniphier/clk/pll-pxs3.c +++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c @@ -1,9 +1,64 @@ /* + * Copyright (C) 2017 Socionext Inc. + * * SPDX-License-Identifier: GPL-2.0+ */ +#include <linux/delay.h> + #include "../init.h" +#include "../sc64-regs.h" +#include "pll.h" + +/* PLL type: SSC */ +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ +#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ +#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */ +#define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440) +#define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450) +#define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460) +#define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470) +#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */ +#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */ +#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */ +#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0) + +/* PLL type: VPLL27 */ +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) + +/* PLL type: DSPLL */ +#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) void uniphier_pxs3_pll_init(void) { + uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + /* do nothing for SPLL */ + uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); + uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + + mdelay(1); + + uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL); + uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL); + uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL); + + uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); + uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); + + uniphier_ld20_dspll_init(SC_VPLL8KCTRL); } |