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Diffstat (limited to 'arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h')
-rw-r--r--arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h37
1 files changed, 30 insertions, 7 deletions
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
index 02b3aaba5a..0c11b65e46 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h
@@ -7,7 +7,12 @@
#ifndef _DDRPHY_LD20_REGS_H
#define _DDRPHY_LD20_REGS_H
+#include <linux/bitops.h>
+
#define PHY_REG_SHIFT 2
+#define PHY_SLV_DLY_WIDTH 6
+#define PHY_BITLVL_DLY_WIDTH 6
+#define PHY_MAS_DLY_WIDTH 8
#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT))
#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT))
@@ -17,8 +22,19 @@
#define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT))
#define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT))
#define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT))
+#define PHY_DLL_RECALIB_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
+#define PHY_DLL_RECALIB_INCR BIT(27)
#define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT))
+#define PHY_DLL_ADRCTRL_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
+#define PHY_DLL_ADRCTRL_INCR BIT(9)
+#define PHY_DLL_ADRCTRL_MDL_SHIFT 24
+#define PHY_DLL_ADRCTRL_MDL_MASK (GENMASK(PHY_MAS_DLY_WIDTH - 1, 0) << \
+ PHY_DLL_ADRCTRL_MDL_SHIFT)
#define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT))
+#define PHY_LANE_SEL_LANE_SHIFT 0
+#define PHY_LANE_SEL_LANE_WIDTH 8
+#define PHY_LANE_SEL_BIT_SHIFT 8
+#define PHY_LANE_SEL_BIT_WIDTH 4
#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT))
#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT))
#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT))
@@ -34,9 +50,23 @@
#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT))
#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT))
#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT))
+#define PHY_IP_DQ_DQS_BITWISE_TRIM_MASK \
+ GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
+#define PHY_IP_DQ_DQS_BITWISE_TRIM_INC \
+ BIT(PHY_BITLVL_DLY_WIDTH)
+#define PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE \
+ BIT(PHY_BITLVL_DLY_WIDTH + 1)
#define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT))
#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT))
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK \
+ GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC \
+ BIT(PHY_BITLVL_DLY_WIDTH)
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE \
+ BIT(PHY_BITLVL_DLY_WIDTH + 1)
#define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT))
+#define PHY_DLL_TRIM_CLK_MASK GENMASK(PHY_SLV_DLY_WIDTH, 0)
+#define PHY_DLL_TRIM_CLK_INCR BIT(PHY_SLV_DLY_WIDTH + 1)
#define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT))
#define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT))
#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT))
@@ -45,11 +75,4 @@
#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT))
#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT))
-/* MASK */
-#define MSK_OP_DQ_DM_DQS_BITWISE_TRIM 0x0000007F
-#define MSK_IP_DQ_DQS_BITWISE_TRIM 0x0000007F
-#define MSK_OVERRIDE 0x00000080
-
-#define PHY_BITLVL_DLY_WIDTH 6
-
#endif /* _DDRPHY_LD20_REGS_H */