15 files changed, 1109 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/include/mach/arm-mpcore.h b/arch/arm/mach-uniphier/include/mach/arm-mpcore.h
new file mode 100644
index 0000000000..cf7cd46c10
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/arm-mpcore.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_ARM_MPCORE_H
+#define ARCH_ARM_MPCORE_H
+
+/* Snoop Control Unit */
+#define SCU_OFFSET		0x00
+
+/* SCU Control Register */
+#define SCU_CTRL		0x00
+/* SCU Configuration Register */
+#define SCU_CONF		0x04
+/* SCU CPU Power Status Register */
+#define SCU_PWR_STATUS		0x08
+/* SCU Invalidate All Registers in Secure State */
+#define SCU_INV_ALL		0x0C
+/* SCU Filtering Start Address Register */
+#define SCU_FILTER_START	0x40
+/* SCU Filtering End Address Register */
+#define SCU_FILTER_END		0x44
+/* SCU Access Control Register */
+#define SCU_SAC			0x50
+/* SCU Non-secure Access Control Register */
+#define SCU_SNSAC		0x54
+
+/* Global Timer */
+#define GLOBAL_TIMER_OFFSET	0x200
+
+/* Global Timer Counter Registers */
+#define GTIMER_CNT_L		0x00
+#define GTIMER_CNT_H		0x04
+/* Global Timer Control Register */
+#define GTIMER_CTRL		0x08
+/* Global Timer Interrupt Status Register */
+#define GTIMER_STAT		0x0C
+/* Comparator Value Registers */
+#define GTIMER_CMP_L		0x10
+#define GTIMER_CMP_H		0x14
+/* Auto-increment Register */
+#define GTIMER_INC		0x18
+
+#endif /* ARCH_ARM_MPCORE_H */
diff --git a/arch/arm/mach-uniphier/include/mach/bcu-regs.h b/arch/arm/mach-uniphier/include/mach/bcu-regs.h
new file mode 100644
index 0000000000..0dfd94e5d7
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/bcu-regs.h
@@ -0,0 +1,30 @@
+/*
+ * UniPhier BCU (Bus Control Unit) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_BCU_REGS_H
+#define ARCH_BCU_REGS_H
+
+#define	BCU_BASE		0x50080000
+
+#define	BCSCR(x)                (BCU_BASE + 0x180 + (x) * 4)
+#define	BCSCR0			(BCSCR(0))
+#define	BCSCR1			(BCSCR(1))
+#define	BCSCR2			(BCSCR(2))
+#define	BCSCR3			(BCSCR(3))
+#define	BCSCR4			(BCSCR(4))
+#define	BCSCR5			(BCSCR(5))
+
+#define	BCIPPCCHR(x)		(BCU_BASE + 0x0280 + (x) * 4)
+#define	BCIPPCCHR0		(BCIPPCCHR(0))
+#define	BCIPPCCHR1		(BCIPPCCHR(1))
+#define	BCIPPCCHR2		(BCIPPCCHR(2))
+#define	BCIPPCCHR3		(BCIPPCCHR(3))
+#define	BCIPPCCHR4		(BCIPPCCHR(4))
+#define	BCIPPCCHR5		(BCIPPCCHR(5))
+
+#endif  /* ARCH_BCU_REGS_H */
diff --git a/arch/arm/mach-uniphier/include/mach/board.h b/arch/arm/mach-uniphier/include/mach/board.h
new file mode 100644
index 0000000000..e3cba5befe
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/board.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_BOARD_H
+#define ARCH_BOARD_H
+
+#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \
+	defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
+void support_card_reset(void);
+void support_card_init(void);
+void support_card_late_init(void);
+int check_support_card(void);
+#else
+#define support_card_reset() do {} while (0)
+#define support_card_init()  do {} while (0)
+#define support_card_late_init()  do {} while (0)
+static inline int check_support_card(void)
+{
+	return 0;
+}
+#endif
+
+static inline void uniphier_board_reset(void)
+{
+	support_card_reset();
+}
+
+static inline void uniphier_board_init(void)
+{
+	support_card_init();
+}
+
+static inline void uniphier_board_late_init(void)
+{
+	support_card_late_init();
+}
+
+#endif /* ARCH_BOARD_H */
diff --git a/arch/arm/mach-uniphier/include/mach/boot-device.h b/arch/arm/mach-uniphier/include/mach/boot-device.h
new file mode 100644
index 0000000000..7a10f1c5b2
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/boot-device.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_BOOT_DEVICE_H_
+#define _ASM_BOOT_DEVICE_H_
+
+int get_boot_mode_sel(void);
+
+struct boot_device_info {
+	u32 type;
+	char *info;
+};
+
+extern struct boot_device_info boot_device_table[];
+
+#endif /* _ASM_BOOT_DEVICE_H_ */
diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
new file mode 100644
index 0000000000..6b7d600a9c
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
@@ -0,0 +1,172 @@
+/*
+ * UniPhier DDR PHY registers
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_DDRPHY_REGS_H
+#define ARCH_DDRPHY_REGS_H
+
+#include <linux/compiler.h>
+
+#ifndef __ASSEMBLY__
+
+struct ddrphy {
+	u32 ridr;		/* Revision Identification Register */
+	u32 pir;		/* PHY Initialixation Register */
+	u32 pgcr[2];		/* PHY General Configuration Register */
+	u32 pgsr[2];		/* PHY General Status Register */
+	u32 pllcr;		/* PLL Control Register */
+	u32 ptr[5];		/* PHY Timing Register */
+	u32 acmdlr;		/* AC Master Delay Line Register */
+	u32 acbdlr;		/* AC Bit Delay Line Register */
+	u32 aciocr;		/* AC I/O Configuration Register */
+	u32 dxccr;		/* DATX8 Common Configuration Register */
+	u32 dsgcr;		/* DDR System General Configuration Register */
+	u32 dcr;		/* DRAM Configuration Register */
+	u32 dtpr[3];		/* DRAM Timing Parameters Register */
+	u32 mr0;		/* Mode Register 0 */
+	u32 mr1;		/* Mode Register 1 */
+	u32 mr2;		/* Mode Register 2 */
+	u32 mr3;		/* Mode Register 3 */
+	u32 odtcr;		/* ODT Configuration Register */
+	u32 dtcr;		/* Data Training Configuration Register */
+	u32 dtar[4];		/* Data Training Address Register */
+	u32 dtdr[2];		/* Data Training Data Register */
+	u32 dtedr[2];		/* Data Training Eye Data Register */
+	u32 rsv0[13];		/* Reserved */
+	u32 dcuar;		/* DCU Address Register */
+	u32 dcudr;		/* DCU Data Register */
+	u32 dcurr;		/* DCU Run Register */
+	u32 dculr;		/* DCU Loop Register */
+	u32 dcugcr;		/* DCU General Configuration Register */
+	u32 dcutpr;		/* DCU Timing Parameters Register */
+	u32 dcusr[2];		/* DCU Status Register */
+	u32 rsv1[8];		/* Reserved */
+	u32 bistrr;		/* BIST Run Register */
+	u32 bistwcr;		/* BIST Word Count Register */
+	u32 bistmskr[3];	/* BIST Mask Register */
+	u32 bistlsr;		/* BIST LFSR Sed Register */
+	u32 bistar[3];		/* BIST Address Register */
+	u32 bistudpr;		/* BIST User Data Pattern Register */
+	u32 bistgsr;		/* BIST General Status Register */
+	u32 bistwer;		/* BIST Word Error Register */
+	u32 bistber[4];		/* BIST Bit Error Register */
+	u32 bistwcsr;		/* BIST Word Count Status Register */
+	u32 bistfwr[3];		/* BIST Fail Word Register */
+	u32 rsv2[10];		/* Reserved */
+	u32 gpr[2];		/* General Purpose Register */
+	struct ddrphy_zq {	/* ZQ */
+		u32 cr[2];	/* Impedance Control Register */
+		u32 sr[2];	/* Impedance Status Register */
+	} zq[4];
+	struct ddrphy_datx8 {	/* DATX8 */
+		u32 gcr;	/* General Configuration Register */
+		u32 gsr[2];	/* General Status Register */
+		u32 bdlr[5];	/* Bit Delay Line Register */
+		u32 lcdlr[3];	/* Local Calibrated Delay Line Register */
+		u32 mdlr;	/* Master Delay Line Register */
+		u32 gtr;	/* General Timing Register */
+		u32 rsv[3];	/* Reserved */
+	} dx[9];
+};
+
+#endif /* __ASSEMBLY__ */
+
+#define PIR_INIT		(1 <<  0)	/* Initialization Trigger */
+#define PIR_ZCAL		(1 <<  1)	/* Impedance Calibration */
+#define PIR_PLLINIT		(1 <<  4)	/* PLL Initialization */
+#define PIR_DCAL		(1 <<  5)	/* DDL Calibration */
+#define PIR_PHYRST		(1 <<  6)	/* PHY Reset */
+#define PIR_DRAMRST		(1 <<  7)	/* DRAM Reset */
+#define PIR_DRAMINIT		(1 <<  8)	/* DRAM Initialization */
+#define PIR_WL			(1 <<  9)	/* Write Leveling */
+#define PIR_QSGATE		(1 << 10)	/* Read DQS Gate Training */
+#define PIR_WLADJ		(1 << 11)	/* Write Leveling Adjust */
+#define PIR_RDDSKW		(1 << 12)	/* Read Data Bit Deskew */
+#define PIR_WRDSKW		(1 << 13)	/* Write Data Bit Deskew */
+#define PIR_RDEYE		(1 << 14)	/* Read Data Eye Training */
+#define PIR_WREYE		(1 << 15)	/* Write Data Eye Training */
+#define PIR_LOCKBYP		(1 << 28)	/* PLL Lock Bypass */
+#define PIR_DCALBYP		(1 << 29)	/* DDL Calibration Bypass */
+#define PIR_ZCALBYP		(1 << 30)	/* Impedance Calib Bypass */
+#define PIR_INITBYP		(1 << 31)	/* Initialization Bypass */
+
+#define PGSR0_IDONE		(1 <<  0)	/* Initialization Done */
+#define PGSR0_PLDONE		(1 <<  1)	/* PLL Lock Done */
+#define PGSR0_DCDONE		(1 <<  2)	/* DDL Calibration Done */
+#define PGSR0_ZCDONE		(1 <<  3)	/* Impedance Calibration Done */
+#define PGSR0_DIDONE		(1 <<  4)	/* DRAM Initialization Done */
+#define PGSR0_WLDONE		(1 <<  5)	/* Write Leveling Done */
+#define PGSR0_QSGDONE		(1 <<  6)	/* DQS Gate Training Done */
+#define PGSR0_WLADONE		(1 <<  7)	/* Write Leveling Adjust Done */
+#define PGSR0_RDDONE		(1 <<  8)	/* Read Bit Deskew Done */
+#define PGSR0_WDDONE		(1 <<  9)	/* Write Bit Deskew Done */
+#define PGSR0_REDONE		(1 << 10)	/* Read Eye Training Done */
+#define PGSR0_WEDONE		(1 << 11)	/* Write Eye Training Done */
+#define PGSR0_IERR		(1 << 16)	/* Initialization Error */
+#define PGSR0_PLERR		(1 << 17)	/* PLL Lock Error */
+#define PGSR0_DCERR		(1 << 18)	/* DDL Calibration Error */
+#define PGSR0_ZCERR		(1 << 19)	/* Impedance Calib Error */
+#define PGSR0_DIERR		(1 << 20)	/* DRAM Initialization Error */
+#define PGSR0_WLERR		(1 << 21)	/* Write Leveling Error */
+#define PGSR0_QSGERR		(1 << 22)	/* DQS Gate Training Error */
+#define PGSR0_WLAERR		(1 << 23)	/* Write Leveling Adj Error */
+#define PGSR0_RDERR		(1 << 24)	/* Read Bit Deskew Error */
+#define PGSR0_WDERR		(1 << 25)	/* Write Bit Deskew Error */
+#define PGSR0_REERR		(1 << 26)	/* Read Eye Training Error */
+#define PGSR0_WEERR		(1 << 27)	/* Write Eye Training Error */
+#define PGSR0_DTERR_SHIFT	28		/* Data Training Error Status*/
+#define PGSR0_DTERR		(7 << (PGSR0_DTERR_SHIFT))
+#define PGSR0_APLOCK		(1 << 31)	/* AC PLL Lock */
+
+#define DXCCR_DQSRES_OPEN	(0 << 5)
+#define DXCCR_DQSRES_688_OHM	(1 << 5)
+#define DXCCR_DQSRES_611_OHM	(2 << 5)
+#define DXCCR_DQSRES_550_OHM	(3 << 5)
+#define DXCCR_DQSRES_500_OHM	(4 << 5)
+#define DXCCR_DQSRES_458_OHM	(5 << 5)
+#define DXCCR_DQSRES_393_OHM	(6 << 5)
+#define DXCCR_DQSRES_344_OHM	(7 << 5)
+
+#define DXCCR_DQSNRES_OPEN	(0 << 9)
+#define DXCCR_DQSNRES_688_OHM	(1 << 9)
+#define DXCCR_DQSNRES_611_OHM	(2 << 9)
+#define DXCCR_DQSNRES_550_OHM	(3 << 9)
+#define DXCCR_DQSNRES_500_OHM	(4 << 9)
+#define DXCCR_DQSNRES_458_OHM	(5 << 9)
+#define DXCCR_DQSNRES_393_OHM	(6 << 9)
+#define DXCCR_DQSNRES_344_OHM	(7 << 9)
+
+#define DTCR_DTRANK_SHIFT	4		/* Data Training Rank */
+#define DTCR_DTRANK_MASK	(0x3 << (DTCR_DTRANK_SHIFT))
+#define DTCR_DTMPR		(1 << 6)	/* Data Training using MPR */
+#define DTCR_RNKEN_SHIFT	24		/* Rank Enable */
+#define DTCR_RNKEN_MASK		(0xf << (DTCR_RNKEN_SHIFT))
+
+#define DXGCR_WLRKEN_SHIFT	26		/* Write Level Rank Enable */
+#define DXGCR_WLRKEN_MASK	(0xf << (DXGCR_WLRKEN_SHIFT))
+
+/* SoC-specific parameters */
+#define NR_DATX8_PER_DDRPHY	2
+
+#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#define NR_DDRPHY_PER_CH		1
+#else
+#define NR_DDRPHY_PER_CH		2
+#endif
+
+#define NR_DDRCH		2
+
+#define DDRPHY_BASE(ch, phy)	(0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
+
+#ifndef __ASSEMBLY__
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
+int ddrphy_training(struct ddrphy __iomem *phy);
+#endif
+
+#endif /* ARCH_DDRPHY_REGS_H */
diff --git a/arch/arm/mach-uniphier/include/mach/debug-uart.S b/arch/arm/mach-uniphier/include/mach/debug-uart.S
new file mode 100644
index 0000000000..af55feed04
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/debug-uart.S
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/serial_reg.h>
+
+#if !defined(CONFIG_DEBUG_SEMIHOSTING)
+#include CONFIG_DEBUG_LL_INCLUDE
+#endif
+
+#define BAUDRATE		115200
+#define DIV_ROUND(x, d)		(((x) + ((d) / 2)) / (d))
+#define DIVISOR			DIV_ROUND(UART_CLK, 16 * BAUDRATE)
+
+	.macro		init_debug_uart, ra, rb, rc
+	addruart	\ra, \rb, \rc
+	mov		\rb, #UART_LCR_WLEN8
+	strb		\rb, [\ra, #0x11]
+	ldr		\rb, =DIVISOR
+	str		\rb, [\ra, #0x24]
+	.endm
diff --git a/arch/arm/mach-uniphier/include/mach/ehci-uniphier.h b/arch/arm/mach-uniphier/include/mach/ehci-uniphier.h
new file mode 100644
index 0000000000..e9c5fb4af8
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/ehci-uniphier.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PLAT_UNIPHIER_EHCI_H
+#define __PLAT_UNIPHIER_EHCI_H
+
+#include <linux/types.h>
+#include <asm/io.h>
+#include "mio-regs.h"
+
+struct uniphier_ehci_platform_data {
+	unsigned long base;
+};
+
+extern struct uniphier_ehci_platform_data uniphier_ehci_platdata[];
+
+static inline void uniphier_ehci_reset(int index, int on)
+{
+	u32 tmp;
+
+	tmp = readl(MIO_USB_RSTCTRL(index));
+	if (on)
+		tmp &= ~MIO_USB_RSTCTRL_XRST;
+	else
+		tmp |= MIO_USB_RSTCTRL_XRST;
+	writel(tmp, MIO_USB_RSTCTRL(index));
+}
+
+#endif /* __PLAT_UNIPHIER_EHCI_H */
diff --git a/arch/arm/mach-uniphier/include/mach/led.h b/arch/arm/mach-uniphier/include/mach/led.h
new file mode 100644
index 0000000000..21277dac76
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/led.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_LED_H
+#define ARCH_LED_H
+
+#include <config.h>
+
+#define LED_CHAR_0	0x7e
+#define LED_CHAR_1	0x0c
+#define LED_CHAR_2	0xb6
+#define LED_CHAR_3	0x9e
+#define LED_CHAR_4	0xcc
+#define LED_CHAR_5	0xda
+#define LED_CHAR_6	0xfa
+#define LED_CHAR_7	0x4e
+#define LED_CHAR_8	0xfe
+#define LED_CHAR_9	0xde
+
+#define LED_CHAR_A	0xee
+#define LED_CHAR_B	0xf8
+#define LED_CHAR_C	0x72
+#define LED_CHAR_D	0xbc
+#define LED_CHAR_E	0xf2
+#define LED_CHAR_F	0xe2
+#define LED_CHAR_G	0x7a
+#define LED_CHAR_H	0xe8
+#define LED_CHAR_I	0x08
+#define LED_CHAR_J	0x3c
+#define LED_CHAR_K	0xea
+#define LED_CHAR_L	0x70
+#define LED_CHAR_M	0x6e
+#define LED_CHAR_N	0xa8
+#define LED_CHAR_O	0xb8
+#define LED_CHAR_P	0xe6
+#define LED_CHAR_Q	0xce
+#define LED_CHAR_R	0xa0
+#define LED_CHAR_S	0xc8
+#define LED_CHAR_T	0x8c
+#define LED_CHAR_U	0x7c
+#define LED_CHAR_V	0x54
+#define LED_CHAR_W	0xfc
+#define LED_CHAR_X	0xec
+#define LED_CHAR_Y	0xdc
+#define LED_CHAR_Z	0xa4
+
+#define LED_CHAR_SPACE	0x00
+#define LED_CHAR_DOT	0x01
+
+#define LED_CHAR_	(LED_CHAR_SPACE)
+
+/** Macro to translate 4 characters into integer to display led */
+#define LED_C2I(C0, C1, C2, C3)			\
+	(~(					\
+		(LED_CHAR_##C0 << 24) |		\
+		(LED_CHAR_##C1 << 16) |		\
+		(LED_CHAR_##C2 <<  8) |		\
+		(LED_CHAR_##C3)			\
+	))
+
+#if defined(CONFIG_SUPPORT_CARD_LED_BASE)
+
+#define LED_ADDR    CONFIG_SUPPORT_CARD_LED_BASE
+
+#ifdef __ASSEMBLY__
+
+#define led_write(C0, C1, C2, C3)  raw_led_write LED_C2I(C0, C1, C2, C3)
+.macro raw_led_write data
+	ldr r0, =\data
+	ldr r1, =LED_ADDR
+	str r0, [r1]
+.endm
+
+#else /* __ASSEMBLY__ */
+
+#include <asm/io.h>
+
+#define led_write(C0, C1, C2, C3)		\
+do {						\
+	raw_led_write(LED_C2I(C0, C1, C2, C3));	\
+} while (0)
+
+static inline void raw_led_write(u32 data)
+{
+	writel(data, LED_ADDR);
+}
+
+#endif /* __ASSEMBLY__ */
+
+#else /* CONFIG_SUPPORT_CARD_LED_BASE */
+
+#define led_write(C0, C1, C2, C3)
+#define raw_led_write(x)
+
+#endif /* CONFIG_SUPPORT_CARD_LED_BASE */
+
+#endif /* ARCH_LED_H */
diff --git a/arch/arm/mach-uniphier/include/mach/mio-regs.h b/arch/arm/mach-uniphier/include/mach/mio-regs.h
new file mode 100644
index 0000000000..3306934ff7
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/mio-regs.h
@@ -0,0 +1,20 @@
+/*
+ * UniPhier MIO (Media I/O) registers
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_MIO_REGS_H
+#define ARCH_MIO_REGS_H
+
+#define MIO_BASE		0x59810000
+
+#define MIO_CLKCTRL(i)		(MIO_BASE + 0x200 * (i) + 0x0020)
+#define MIO_RSTCTRL(i)		(MIO_BASE + 0x200 * (i) + 0x0110)
+#define MIO_USB_RSTCTRL(i)	(MIO_BASE + 0x200 * (i) + 0x0114)
+
+#define MIO_USB_RSTCTRL_XRST	(0x1 << 0)
+
+#endif /* ARCH_MIO_REGS_H */
diff --git a/arch/arm/mach-uniphier/include/mach/platdevice.h b/arch/arm/mach-uniphier/include/mach/platdevice.h
new file mode 100644
index 0000000000..62a512659c
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/platdevice.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_PLATDEVICE_H
+#define ARCH_PLATDEVICE_H
+
+#include <dm/platdata.h>
+#include <dm/platform_data/serial-uniphier.h>
+
+#define SERIAL_DEVICE(n, ba, clk)					\
+static struct uniphier_serial_platform_data serial_device##n = {	\
+	.base = ba,							\
+	.uartclk = clk							\
+};									\
+U_BOOT_DEVICE(serial##n) = {						\
+	.name = DRIVER_NAME,						\
+	.platdata = &serial_device##n					\
+};
+
+#include <asm/arch/ehci-uniphier.h>
+
+#endif /* ARCH_PLATDEVICE_H */
diff --git a/arch/arm/mach-uniphier/include/mach/sbc-regs.h b/arch/arm/mach-uniphier/include/mach/sbc-regs.h
new file mode 100644
index 0000000000..efb68e8564
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/sbc-regs.h
@@ -0,0 +1,109 @@
+/*
+ * UniPhier SBC (System Bus Controller) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_SBC_REGS_H
+#define ARCH_SBC_REGS_H
+
+#define	SBBASE_BASE		0x58c00100
+#define	SBBASE(x)		(SBBASE_BASE + (x) * 0x10)
+
+#define	SBBASE0			(SBBASE(0))
+#define	SBBASE1			(SBBASE(1))
+#define	SBBASE2			(SBBASE(2))
+#define	SBBASE3			(SBBASE(3))
+#define	SBBASE4			(SBBASE(4))
+#define	SBBASE5			(SBBASE(5))
+#define	SBBASE6			(SBBASE(6))
+#define	SBBASE7			(SBBASE(7))
+
+#define	SBBASE_BANK_ENABLE	(0x00000001)
+
+#define	SBCTRL_BASE		0x58c00200
+#define	SBCTRL(x, y)		(SBCTRL_BASE + (x) * 0x10 + (y) * 4)
+
+#define	SBCTRL00		SBCTRL(0, 0)
+#define	SBCTRL01		SBCTRL(0, 1)
+#define	SBCTRL02		SBCTRL(0, 2)
+#define	SBCTRL03		SBCTRL(0, 3)
+#define	SBCTRL04		(SBCTRL_BASE + 0x100)
+
+#define	SBCTRL10		SBCTRL(1, 0)
+#define	SBCTRL11		SBCTRL(1, 1)
+#define	SBCTRL12		SBCTRL(1, 2)
+#define	SBCTRL13		SBCTRL(1, 3)
+#define	SBCTRL14		(SBCTRL_BASE + 0x110)
+
+#define	SBCTRL20		SBCTRL(2, 0)
+#define	SBCTRL21		SBCTRL(2, 1)
+#define	SBCTRL22		SBCTRL(2, 2)
+#define	SBCTRL23		SBCTRL(2, 3)
+#define	SBCTRL24		(SBCTRL_BASE + 0x120)
+
+#define	SBCTRL30		SBCTRL(3, 0)
+#define	SBCTRL31		SBCTRL(3, 1)
+#define	SBCTRL32		SBCTRL(3, 2)
+#define	SBCTRL33		SBCTRL(3, 3)
+#define	SBCTRL34		(SBCTRL_BASE + 0x130)
+
+#define	SBCTRL40		SBCTRL(4, 0)
+#define	SBCTRL41		SBCTRL(4, 1)
+#define	SBCTRL42		SBCTRL(4, 2)
+#define	SBCTRL43		SBCTRL(4, 3)
+#define	SBCTRL44		(SBCTRL_BASE + 0x140)
+
+#define	SBCTRL50		SBCTRL(5, 0)
+#define	SBCTRL51		SBCTRL(5, 1)
+#define	SBCTRL52		SBCTRL(5, 2)
+#define	SBCTRL53		SBCTRL(5, 3)
+#define	SBCTRL54		(SBCTRL_BASE + 0x150)
+
+#define	SBCTRL60		SBCTRL(6, 0)
+#define	SBCTRL61		SBCTRL(6, 1)
+#define	SBCTRL62		SBCTRL(6, 2)
+#define	SBCTRL63		SBCTRL(6, 3)
+#define	SBCTRL64		(SBCTRL_BASE + 0x160)
+
+#define	SBCTRL70		SBCTRL(7, 0)
+#define	SBCTRL71		SBCTRL(7, 1)
+#define	SBCTRL72		SBCTRL(7, 2)
+#define	SBCTRL73		SBCTRL(7, 3)
+#define	SBCTRL74		(SBCTRL_BASE + 0x170)
+
+/* slower but LED works */
+#define SBCTRL0_SAVEPIN_PERI_VALUE	0x55450000
+#define SBCTRL1_SAVEPIN_PERI_VALUE	0x07168d00
+#define SBCTRL2_SAVEPIN_PERI_VALUE	0x34000009
+#define SBCTRL4_SAVEPIN_PERI_VALUE	0x02110110
+
+/* faster but LED does not work */
+#define SBCTRL0_SAVEPIN_MEM_VALUE	0x55450000
+#define SBCTRL1_SAVEPIN_MEM_VALUE	0x06057700
+/* NOR flash needs more wait counts than SRAM */
+#define SBCTRL2_SAVEPIN_MEM_VALUE	0x34000009
+#define SBCTRL4_SAVEPIN_MEM_VALUE	0x02110210
+
+#define SBCTRL0_ADMULTIPLX_PERI_VALUE	0x33120000
+#define SBCTRL1_ADMULTIPLX_PERI_VALUE	0x03005500
+#define SBCTRL2_ADMULTIPLX_PERI_VALUE	0x14000020
+
+#define SBCTRL0_ADMULTIPLX_MEM_VALUE	0x33120000
+#define SBCTRL1_ADMULTIPLX_MEM_VALUE	0x03005500
+#define SBCTRL2_ADMULTIPLX_MEM_VALUE	0x14000010
+
+#define PC0CTRL				0x598000c0
+#define ROM_BOOT_ROMRSV2		0x59801208
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+static inline int boot_is_swapped(void)
+{
+	return !(readl(SBBASE0) & SBBASE_BANK_ENABLE);
+}
+#endif
+
+#endif	/* ARCH_SBC_REGS_H */
diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h
new file mode 100644
index 0000000000..1197bb52d4
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h
@@ -0,0 +1,62 @@
+/*
+ * UniPhier SC (System Control) block registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_SC_REGS_H
+#define ARCH_SC_REGS_H
+
+#define SC_BASE_ADDR			0x61840000
+
+#define SC_MPLLOSCCTL                   (SC_BASE_ADDR | 0x1184)
+#define SC_MPLLOSCCTL_MPLLEN		(0x1 << 0)
+#define SC_MPLLOSCCTL_MPLLST		(0x1 << 1)
+
+#define SC_DPLLCTRL			(SC_BASE_ADDR | 0x1200)
+#define SC_DPLLCTRL_SSC_EN		(0x1 << 31)
+#define SC_DPLLCTRL_FOUTMODE_MASK        (0xf << 16)
+#define SC_DPLLCTRL_SSC_RATE		(0x1 << 15)
+
+#define SC_DPLLCTRL2			(SC_BASE_ADDR | 0x1204)
+#define SC_DPLLCTRL2_NRSTDS		(0x1 << 28)
+
+#define SC_DPLLCTRL3			(SC_BASE_ADDR | 0x1208)
+#define SC_DPLLCTRL3_LPFSEL_COEF2	(0x0 << 31)
+#define SC_DPLLCTRL3_LPFSEL_COEF3	(0x1 << 31)
+
+#define SC_UPLLCTRL			(SC_BASE_ADDR | 0x1210)
+
+#define SC_VPLL27ACTRL			(SC_BASE_ADDR | 0x1270)
+#define SC_VPLL27ACTRL2			(SC_BASE_ADDR | 0x1274)
+#define SC_VPLL27ACTRL3			(SC_BASE_ADDR | 0x1278)
+
+#define SC_VPLL27BCTRL			(SC_BASE_ADDR | 0x1290)
+#define SC_VPLL27BCTRL2			(SC_BASE_ADDR | 0x1294)
+#define SC_VPLL27BCTRL3			(SC_BASE_ADDR | 0x1298)
+
+#define SC_RSTCTRL			(SC_BASE_ADDR | 0x2000)
+#define SC_RSTCTRL_NRST_ETHER		(0x1 << 12)
+#define SC_RSTCTRL_NRST_UMC1		(0x1 <<  5)
+#define SC_RSTCTRL_NRST_UMC0		(0x1 <<  4)
+#define SC_RSTCTRL_NRST_NAND		(0x1 <<  2)
+
+#define SC_RSTCTRL2			(SC_BASE_ADDR | 0x2004)
+#define SC_RSTCTRL3			(SC_BASE_ADDR | 0x2008)
+
+#define SC_CLKCTRL			(SC_BASE_ADDR | 0x2104)
+#define SC_CLKCTRL_CLK_ETHER		(0x1 << 12)
+#define SC_CLKCTRL_CLK_MIO		(0x1 << 11)
+#define SC_CLKCTRL_CLK_UMC		(0x1 <<  4)
+#define SC_CLKCTRL_CLK_NAND		(0x1 <<  2)
+#define SC_CLKCTRL_CLK_SBC		(0x1 <<  1)
+#define SC_CLKCTRL_CLK_PERI		(0x1 <<  0)
+
+/* System reset control register */
+#define SC_IRQTIMSET			(SC_BASE_ADDR | 0x3000)
+#define SC_SLFRSTSEL			(SC_BASE_ADDR | 0x3010)
+#define SC_SLFRSTCTL			(SC_BASE_ADDR | 0x3014)
+
+#endif /* ARCH_SC_REGS_H */
diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/include/mach/sg-regs.h
new file mode 100644
index 0000000000..4ae67c8adb
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h
@@ -0,0 +1,238 @@
+/*
+ * UniPhier SG (SoC Glue) block registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_SG_REGS_H
+#define ARCH_SG_REGS_H
+
+/* Base Address */
+#define SG_CTRL_BASE			0x5f800000
+#define SG_DBG_BASE			0x5f900000
+
+/* Revision */
+#define SG_REVISION			(SG_CTRL_BASE | 0x0000)
+#define SG_REVISION_TYPE_SHIFT		16
+#define SG_REVISION_TYPE_MASK		(0xff << SG_REVISION_TYPE_SHIFT)
+#define SG_REVISION_MODEL_SHIFT		8
+#define SG_REVISION_MODEL_MASK		(0x3 << SG_REVISION_MODEL_SHIFT)
+#define SG_REVISION_REV_SHIFT		0
+#define SG_REVISION_REV_MASK		(0x1f << SG_REVISION_REV_SHIFT)
+
+/* Memory Configuration */
+#define SG_MEMCONF			(SG_CTRL_BASE | 0x0400)
+
+#define SG_MEMCONF_CH0_SZ_64M		((0x0 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_SZ_128M		((0x0 << 10) | (0x02 << 0))
+#define SG_MEMCONF_CH0_SZ_256M		((0x0 << 10) | (0x03 << 0))
+#define SG_MEMCONF_CH0_SZ_512M		((0x1 << 10) | (0x00 << 0))
+#define SG_MEMCONF_CH0_SZ_1G		((0x1 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_NUM_1		(0x1 << 8)
+#define SG_MEMCONF_CH0_NUM_2		(0x0 << 8)
+
+#define SG_MEMCONF_CH1_SZ_64M		((0x0 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_SZ_128M		((0x0 << 11) | (0x02 << 2))
+#define SG_MEMCONF_CH1_SZ_256M		((0x0 << 11) | (0x03 << 2))
+#define SG_MEMCONF_CH1_SZ_512M		((0x1 << 11) | (0x00 << 2))
+#define SG_MEMCONF_CH1_SZ_1G		((0x1 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_NUM_1		(0x1 << 9)
+#define SG_MEMCONF_CH1_NUM_2		(0x0 << 9)
+
+#define SG_MEMCONF_CH2_SZ_64M		((0x0 << 26) | (0x01 << 16))
+#define SG_MEMCONF_CH2_SZ_128M		((0x0 << 26) | (0x02 << 16))
+#define SG_MEMCONF_CH2_SZ_256M		((0x0 << 26) | (0x03 << 16))
+#define SG_MEMCONF_CH2_SZ_512M		((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_NUM_1		(0x1 << 24)
+#define SG_MEMCONF_CH2_NUM_2		(0x0 << 24)
+
+#define SG_MEMCONF_SPARSEMEM		(0x1 << 4)
+
+/* Pin Control */
+#define SG_PINCTRL_BASE			(SG_CTRL_BASE | 0x1000)
+
+#if defined(CONFIG_MACH_PH1_PRO4)
+# define SG_PINCTRL(n)			(SG_PINCTRL_BASE + (n) * 8)
+#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+# define SG_PINCTRL(n)			(SG_PINCTRL_BASE + (n) * 4)
+#endif
+
+#if defined(CONFIG_MACH_PH1_PRO4)
+#define SG_PINSELBITS			4
+#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#define SG_PINSELBITS			8
+#endif
+
+#define SG_PINSEL_ADDR(n)		(SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
+#define SG_PINSEL_MASK(n)		(~(((1 << (SG_PINSELBITS)) - 1) << \
+						((n) * (SG_PINSELBITS) % 32)))
+#define SG_PINSEL_MODE(n, mode)		((mode) << ((n) * (SG_PINSELBITS) % 32))
+
+/* Only for PH1-Pro4 */
+#define SG_LOADPINCTRL			(SG_CTRL_BASE | 0x1700)
+
+/* Input Enable */
+#define SG_IECTRL			(SG_CTRL_BASE | 0x1d00)
+
+/* Pin Monitor */
+#define SG_PINMON0			(SG_DBG_BASE | 0x0100)
+
+#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK	(0x3 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT	(0x0 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A	(0x2 << 19)
+#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B	(0x3 << 19)
+
+#define SG_PINMON0_CLK_MODE_AXOSEL_MASK		(0x3 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ	(0x0 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ	(0x1 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ	(0x2 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ	(0x3 << 16)
+
+#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT	(0x0 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U	(0x1 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ	(0x2 << 16)
+#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A	(0x3 << 16)
+
+#ifdef __ASSEMBLY__
+
+	.macro	set_pinsel, n, value, ra, rd
+	ldr	\ra, =SG_PINSEL_ADDR(\n)
+	ldr	\rd, [\ra]
+	and	\rd, \rd, #SG_PINSEL_MASK(\n)
+	orr	\rd, \rd, #SG_PINSEL_MODE(\n, \value)
+	str	\rd, [\ra]
+	.endm
+
+#else
+
+#include <linux/types.h>
+#include <linux/sizes.h>
+#include <asm/io.h>
+
+static inline void sg_set_pinsel(int n, int value)
+{
+	writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
+	       | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
+}
+
+static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
+{
+	int size_mb = size / num;
+	u32 ret;
+
+	switch (size_mb) {
+	case SZ_64M:
+		ret = SG_MEMCONF_CH0_SZ_64M;
+		break;
+	case SZ_128M:
+		ret = SG_MEMCONF_CH0_SZ_128M;
+		break;
+	case SZ_256M:
+		ret = SG_MEMCONF_CH0_SZ_256M;
+		break;
+	case SZ_512M:
+		ret = SG_MEMCONF_CH0_SZ_512M;
+		break;
+	case SZ_1G:
+		ret = SG_MEMCONF_CH0_SZ_1G;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	switch (num) {
+	case 1:
+		ret |= SG_MEMCONF_CH0_NUM_1;
+		break;
+	case 2:
+		ret |= SG_MEMCONF_CH0_NUM_2;
+		break;
+	default:
+		BUG();
+		break;
+	}
+	return ret;
+}
+
+static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
+{
+	int size_mb = size / num;
+	u32 ret;
+
+	switch (size_mb) {
+	case SZ_64M:
+		ret = SG_MEMCONF_CH1_SZ_64M;
+		break;
+	case SZ_128M:
+		ret = SG_MEMCONF_CH1_SZ_128M;
+		break;
+	case SZ_256M:
+		ret = SG_MEMCONF_CH1_SZ_256M;
+		break;
+	case SZ_512M:
+		ret = SG_MEMCONF_CH1_SZ_512M;
+		break;
+	case SZ_1G:
+		ret = SG_MEMCONF_CH1_SZ_1G;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	switch (num) {
+	case 1:
+		ret |= SG_MEMCONF_CH1_NUM_1;
+		break;
+	case 2:
+		ret |= SG_MEMCONF_CH1_NUM_2;
+		break;
+	default:
+		BUG();
+		break;
+	}
+	return ret;
+}
+
+static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
+{
+	int size_mb = size / num;
+	u32 ret;
+
+	switch (size_mb) {
+	case SZ_64M:
+		ret = SG_MEMCONF_CH2_SZ_64M;
+		break;
+	case SZ_128M:
+		ret = SG_MEMCONF_CH2_SZ_128M;
+		break;
+	case SZ_256M:
+		ret = SG_MEMCONF_CH2_SZ_256M;
+		break;
+	case SZ_512M:
+		ret = SG_MEMCONF_CH2_SZ_512M;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	switch (num) {
+	case 1:
+		ret |= SG_MEMCONF_CH2_NUM_1;
+		break;
+	case 2:
+		ret |= SG_MEMCONF_CH2_NUM_2;
+		break;
+	default:
+		BUG();
+		break;
+	}
+	return ret;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* ARCH_SG_REGS_H */
diff --git a/arch/arm/mach-uniphier/include/mach/ssc-regs.h b/arch/arm/mach-uniphier/include/mach/ssc-regs.h
new file mode 100644
index 0000000000..77b3470c6d
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/ssc-regs.h
@@ -0,0 +1,67 @@
+/*
+ * UniPhier System Cache (L2 Cache) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_SSC_REGS_H
+#define ARCH_SSC_REGS_H
+
+#define SSCC			0x500c0000
+#define SSCC_BST		(0x1 << 20)
+#define SSCC_ACT		(0x1 << 19)
+#define SSCC_WTG		(0x1 << 18)
+#define SSCC_PRD		(0x1 << 17)
+#define SSCC_WBWA		(0x1 << 16)
+#define SSCC_EX			(0x1 << 13)
+#define SSCC_ON			(0x1 <<  0)
+
+#define SSCLPDAWCR		0x500c0030
+
+#define SSCOPE			0x506c0244
+#define SSCOPE_CM_SYNC		0x00000008
+
+#define SSCOQM			0x506c0248
+#define SSCOQM_TID_MASK		(0x3 << 21)
+#define SSCOQM_TID_BY_WAY	(0x2 << 21)
+#define SSCOQM_TID_BY_INST_WAY	(0x1 << 21)
+#define SSCOQM_TID_BY_DATA_WAY	(0x0 << 21)
+#define SSCOQM_S_MASK		(0x3 << 17)
+#define SSCOQM_S_WAY		(0x2 << 17)
+#define SSCOQM_S_ALL		(0x1 << 17)
+#define SSCOQM_S_ADDRESS	(0x0 << 17)
+#define SSCOQM_CE		(0x1 << 15)
+#define SSCOQM_CW		(0x1 << 14)
+#define SSCOQM_CM_MASK		(0x7)
+#define SSCOQM_CM_DIRT_TOUCH	(0x7)
+#define SSCOQM_CM_ZERO_TOUCH	(0x6)
+#define SSCOQM_CM_NORM_TOUCH	(0x5)
+#define SSCOQM_CM_PREF_FETCH	(0x4)
+#define SSCOQM_CM_SSC_FETCH	(0x3)
+#define SSCOQM_CM_WB_INV	(0x2)
+#define SSCOQM_CM_WB		(0x1)
+#define SSCOQM_CM_INV		(0x0)
+
+#define SSCOQAD			0x506c024c
+#define SSCOQSZ			0x506c0250
+#define SSCOQWN			0x506c0258
+
+#define SSCOPPQSEF		0x506c025c
+#define SSCOPPQSEF_FE		(0x1 << 1)
+#define SSCOPPQSEF_OE		(0x1 << 0)
+
+#define SSCOLPQS		0x506c0260
+#define SSCOLPQS_EF		(0x1 << 2)
+#define SSCOLPQS_EST		(0x1 << 1)
+#define SSCOLPQS_QST		(0x1 << 0)
+
+#define SSCOQCE0		0x506c0270
+
+#define SSC_LINE_SIZE		128
+#define SSC_NUM_ENTRIES		256
+#define SSC_WAY_SIZE		((SSC_LINE_SIZE) * (SSC_NUM_ENTRIES))
+#define SSC_RANGE_OP_MAX_SIZE	(0x00400000 - (SSC_LINE_SIZE))
+
+#endif  /* ARCH_SSC_REGS_H */
diff --git a/arch/arm/mach-uniphier/include/mach/umc-regs.h b/arch/arm/mach-uniphier/include/mach/umc-regs.h
new file mode 100644
index 0000000000..6159281fd3
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/umc-regs.h
@@ -0,0 +1,119 @@
+/*
+ * UniPhier UMC (Universal Memory Controller) registers
+ *
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARCH_UMC_REGS_H
+#define ARCH_UMC_REGS_H
+
+#define UMC_BASE		0x5b800000
+
+/* SSIF registers */
+#define UMC_SSIF_BASE		UMC_BASE
+
+#define UMC_CPURST		0x00000700
+#define UMC_IDSRST		0x0000070C
+#define UMC_IXMRST		0x00000714
+#define UMC_HDMRST		0x00000718
+#define UMC_MDMRST		0x0000071C
+#define UMC_HDDRST		0x00000720
+#define UMC_MDDRST		0x00000724
+#define UMC_SIORST		0x00000728
+#define UMC_GIORST		0x0000072C
+#define UMC_HD2RST		0x00000734
+#define UMC_VIORST		0x0000073C
+#define UMC_FRCRST		0x00000748 /* LD4/sLD8 */
+#define UMC_DVCRST		0x00000748 /* Pro4 */
+#define UMC_RGLRST		0x00000750
+#define UMC_VPERST		0x00000758
+#define UMC_AIORST		0x00000764
+#define UMC_DMDRST		0x00000770
+
+#define UMC_HDMCHSEL		0x00000898
+#define UMC_MDMCHSEL		0x0000089C
+#define UMC_DVCCHSEL		0x000008C8
+#define UMC_DMDCHSEL		0x000008F0
+
+#define UMC_CLKEN_SSIF_FETCH	0x0000C060
+#define UMC_CLKEN_SSIF_COMQUE0	0x0000C064
+#define UMC_CLKEN_SSIF_COMWC0	0x0000C068
+#define UMC_CLKEN_SSIF_COMRC0	0x0000C06C
+#define UMC_CLKEN_SSIF_COMQUE1	0x0000C070
+#define UMC_CLKEN_SSIF_COMWC1	0x0000C074
+#define UMC_CLKEN_SSIF_COMRC1	0x0000C078
+#define UMC_CLKEN_SSIF_WC	0x0000C07C
+#define UMC_CLKEN_SSIF_RC	0x0000C080
+#define UMC_CLKEN_SSIF_DST	0x0000C084
+
+/* CA registers */
+#define UMC_CA_BASE(ch)		(UMC_BASE + 0x00001000 + 0x00001000 * (ch))
+
+/* DRAM controller registers */
+#define UMC_DRAMCONT_BASE(ch)	(UMC_BASE + 0x00400000 + 0x00200000 * (ch))
+
+#define UMC_CMDCTLA		0x00000000
+#define UMC_CMDCTLB		0x00000004
+#define UMC_INITCTLA		0x00000008
+#define UMC_INITCTLB		0x0000000C
+#define UMC_INITCTLC		0x00000010
+#define UMC_INITSET		0x00000014
+#define UMC_INITSTAT		0x00000018
+#define UMC_DRMMR0		0x0000001C
+#define UMC_DRMMR1		0x00000020
+#define UMC_DRMMR2		0x00000024
+#define UMC_DRMMR3		0x00000028
+#define UMC_SPCCTLA		0x00000030
+#define UMC_SPCCTLB		0x00000034
+#define UMC_SPCSETA		0x00000038
+#define UMC_SPCSETB		0x0000003C
+#define UMC_SPCSETC		0x00000040
+#define UMC_SPCSETD		0x00000044
+#define UMC_SPCSTATA		0x00000050
+#define UMC_SPCSTATB		0x00000054
+#define UMC_SPCSTATC		0x00000058
+#define UMC_ACSSETA		0x00000060
+#define UMC_FLOWCTLA		0x00000400
+#define UMC_FLOWCTLB		0x00000404
+#define UMC_FLOWCTLC		0x00000408
+#define UMC_FLOWCTLG		0x00000508
+#define UMC_RDATACTL_D0		0x00000600
+#define UMC_WDATACTL_D0		0x00000604
+#define UMC_RDATACTL_D1		0x00000608
+#define UMC_WDATACTL_D1		0x0000060C
+#define UMC_DATASET		0x00000610
+#define UMC_DCCGCTL		0x00000720
+#define UMC_DICGCTLA		0x00000724
+#define UMC_DICGCTLB		0x00000728
+#define UMC_DIOCTLA		0x00000C00
+#define UMC_DFICUPDCTLA		0x00000C20
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+static inline void umc_polling(u32 address, u32 expval, u32 mask)
+{
+	u32 nmask = ~mask;
+	u32 data;
+	do {
+		data = readl(address) & nmask;
+	} while (data != expval);
+}
+
+static inline void umc_dram_init_start(void __iomem *dramcont)
+{
+	writel(0x00000002, dramcont + UMC_INITSET);
+}
+
+static inline void umc_dram_init_poll(void __iomem *dramcont)
+{
+	while ((readl(dramcont + UMC_INITSTAT) & 0x00000002))
+		;
+}
+
+#endif
+
+#endif