11 files changed, 0 insertions, 625 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 089bef22e8..0bed390f0d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -223,10 +223,6 @@ config ORION5X
 	bool "Marvell Orion"
 	select CPU_ARM926EJS
 
-config TARGET_DKB
-	bool "Support dkb"
-	select CPU_ARM926EJS
-
 config TARGET_SPEAR300
 	bool "Support spear300"
 	select CPU_ARM926EJS
@@ -757,7 +753,6 @@ source "board/BuR/tseries/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
 source "board/Marvell/db-mv784mp-gp/Kconfig"
-source "board/Marvell/dkb/Kconfig"
 source "board/Marvell/gplugd/Kconfig"
 source "board/altera/socfpga/Kconfig"
 source "board/armadeus/apf27/Kconfig"
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index ac23116955..63fa159db6 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -19,5 +19,4 @@ obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
 obj-$(CONFIG_MX25) += mx25/
 obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
-obj-$(CONFIG_PANTHEON) += pantheon/
 obj-$(if $(filter spear,$(SOC)),y) += spear/
diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile
deleted file mode 100644
index 988341f8fb..0000000000
--- a/arch/arm/cpu/arm926ejs/pantheon/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2011
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Lei Wen <leiwen@marvell.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= cpu.o timer.o dram.o
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
deleted file mode 100644
index 4e2a177c0d..0000000000
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
-#define SET_MRVL_ID	(1<<8)
-#define L2C_RAM_SEL	(1<<4)
-
-int arch_cpu_init(void)
-{
-	u32 val;
-	struct panthcpu_registers *cpuregs =
-		(struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
-	struct panthapb_registers *apbclkres =
-		(struct panthapb_registers*) PANTHEON_APBC_BASE;
-
-	struct panthmpmu_registers *mpmu =
-		(struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
-
-	struct panthapmu_registers *apmu =
-		(struct panthapmu_registers *) PANTHEON_APMU_BASE;
-
-	/* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
-	val = readl(&cpuregs->cpu_conf);
-	val = val | SET_MRVL_ID;
-	writel(val, &cpuregs->cpu_conf);
-
-	/* Turn on clock gating (PMUM_CCGR) */
-	writel(0xFFFFFFFF, &mpmu->ccgr);
-
-	/* Turn on clock gating (PMUM_ACGR) */
-	writel(0xFFFFFFFF, &mpmu->acgr);
-
-	/* Turn on uart2 clock */
-	writel(UARTCLK14745KHZ, &apbclkres->uart0);
-
-	/* Enable GPIO clock */
-	writel(APBC_APBCLK, &apbclkres->gpio);
-
-#ifdef CONFIG_I2C_MV
-	/* Enable I2C clock */
-	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
-	writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
-#endif
-
-#ifdef CONFIG_MV_SDHCI
-	/* Enable mmc clock */
-	writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
-			&apmu->sd1);
-	writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
-			&apmu->sd3);
-#endif
-
-	icache_enable();
-
-	return 0;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	u32 id;
-	struct panthcpu_registers *cpuregs =
-		(struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
-	id = readl(&cpuregs->chip_id);
-	printf("SoC:   PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_I2C_MV
-void i2c_clk_enable(void)
-{
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c
deleted file mode 100644
index f77e3d0ab5..0000000000
--- a/arch/arm/cpu/arm926ejs/pantheon/dram.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>,
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pantheon.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Pantheon DRAM controller supports upto 8 banks
- * for chip select 0 and 1
- */
-
-/*
- * DDR Memory Control Registers
- * Refer Datasheet 4.4
- */
-struct panthddr_map_registers {
-	u32	cs;	/* Memory Address Map Register -CS */
-	u32	pad[3];
-};
-
-struct panthddr_registers {
-	u8	pad[0x100 - 0x000];
-	struct panthddr_map_registers mmap[2];
-};
-
-/*
- * panth_sdram_base - reads SDRAM Base Address Register
- */
-u32 panth_sdram_base(int chip_sel)
-{
-	struct panthddr_registers *ddr_regs =
-		(struct panthddr_registers *)PANTHEON_DRAM_BASE;
-	u32 result = 0;
-	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
-	if (!CS_valid)
-		return 0;
-
-	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
-	return result;
-}
-
-/*
- * panth_sdram_size - reads SDRAM size
- */
-u32 panth_sdram_size(int chip_sel)
-{
-	struct panthddr_registers *ddr_regs =
-		(struct panthddr_registers *)PANTHEON_DRAM_BASE;
-	u32 result = 0;
-	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
-	if (!CS_valid)
-		return 0;
-
-	result = readl(&ddr_regs->mmap[chip_sel].cs);
-	result = (result >> 16) & 0xF;
-	if (result < 0x7) {
-		printf("Unknown DRAM Size\n");
-		return -1;
-	} else {
-		return ((0x8 << (result - 0x7)) * 1024 * 1024);
-	}
-}
-
-#ifndef CONFIG_SYS_BOARD_DRAM_INIT
-int dram_init(void)
-{
-	int i;
-
-	gd->ram_size = 0;
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = panth_sdram_base(i);
-		gd->bd->bi_dram[i].size = panth_sdram_size(i);
-		/*
-		 * It is assumed that all memory banks are consecutive
-		 * and without gaps.
-		 * If the gap is found, ram_size will be reported for
-		 * consecutive memory only
-		 */
-		if (gd->bd->bi_dram[i].start != gd->ram_size)
-			break;
-
-		gd->ram_size += gd->bd->bi_dram[i].size;
-
-	}
-
-	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
-		/*
-		 * If above loop terminated prematurely, we need to set
-		 * remaining banks' start address & size as 0. Otherwise other
-		 * u-boot functions and Linux kernel gets wrong values which
-		 * could result in crash
-		 */
-		gd->bd->bi_dram[i].start = 0;
-		gd->bd->bi_dram[i].size = 0;
-	}
-	return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-void dram_init_banksize(void)
-{
-	dram_init();
-}
-#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c
deleted file mode 100644
index 6382d3b0cf..0000000000
--- a/arch/arm/cpu/arm926ejs/pantheon/timer.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-/*
- * Timer registers
- * Refer 6.2.9 in Datasheet
- */
-struct panthtmr_registers {
-	u32 clk_ctrl;	/* Timer clk control reg */
-	u32 match[9];	/* Timer match registers */
-	u32 count[3];	/* Timer count registers */
-	u32 status[3];
-	u32 ie[3];
-	u32 preload[3];	/* Timer preload value */
-	u32 preload_ctrl[3];
-	u32 wdt_match_en;
-	u32 wdt_match_r;
-	u32 wdt_val;
-	u32 wdt_sts;
-	u32 icr[3];
-	u32 wdt_icr;
-	u32 cer;	/* Timer count enable reg */
-	u32 cmr;
-	u32 ilr[3];
-	u32 wcr;
-	u32 wfar;
-	u32 wsar;
-	u32 cvwr[3];
-};
-
-#define TIMER			0	/* Use TIMER 0 */
-/* Each timer has 3 match registers */
-#define MATCH_CMP(x)		((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 		0xffffffff
-#define	COUNT_RD_REQ		0x1
-
-DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
-
-/*
- * For preventing risk of instability in reading counter value,
- * first set read request to register cvwr and then read same
- * register after it captures counter value.
- */
-ulong read_timer(void)
-{
-	struct panthtmr_registers *panthtimers =
-		(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
-	volatile int loop=100;
-	ulong val;
-
-	writel(COUNT_RD_REQ, &panthtimers->cvwr);
-	while (loop--)
-		val = readl(&panthtimers->cvwr);
-
-	/*
-	 * This stop gcc complain and prevent loop mistake init to 0
-	 */
-	val = readl(&panthtimers->cvwr);
-
-	return val;
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now = read_timer();
-
-	if (now >= gd->arch.tbl) {
-		/* normal mode */
-		gd->arch.tbu += now - gd->arch.tbl;
-	} else {
-		/* we have an overflow ... */
-		gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
-	}
-	gd->arch.tbl = now;
-
-	return gd->arch.tbu;
-}
-
-ulong get_timer(ulong base)
-{
-	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
-		base);
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong delayticks;
-	ulong endtime;
-
-	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
-	endtime = get_timer_masked() + delayticks;
-
-	while (get_timer_masked() < endtime)
-		;
-}
-
-/*
- * init the Timer
- */
-int timer_init(void)
-{
-	struct panthapb_registers *apb1clkres =
-		(struct panthapb_registers *) PANTHEON_APBC_BASE;
-	struct panthtmr_registers *panthtimers =
-		(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
-
-	/* Enable Timer clock at 3.25 MHZ */
-	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
-
-	/* load value into timer */
-	writel(0x0, &panthtimers->clk_ctrl);
-	/* Use Timer 0 Match Resiger 0 */
-	writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
-	/* Preload value is 0 */
-	writel(0x0, &panthtimers->preload[TIMER]);
-	/* Enable match comparator 0 for Timer 0 */
-	writel(0x1, &panthtimers->preload_ctrl[TIMER]);
-
-	/* Enable timer 0 */
-	writel(0x1, &panthtimers->cer);
-	/* init the gd->arch.tbu and gd->arch.tbl value */
-	gd->arch.tbl = read_timer();
-	gd->arch.tbu = 0;
-
-	return 0;
-}
-
-#define MPMU_APRR_WDTR	(1<<4)
-#define TMR_WFAR	0xbaba	/* WDT Register First key */
-#define TMP_WSAR	0xeb10	/* WDT Register Second key */
-
-/*
- * This function uses internal Watchdog Timer
- * based reset mechanism.
- * Steps to write watchdog registers (protected access)
- * 1. Write key value to TMR_WFAR reg.
- * 2. Write key value to TMP_WSAR reg.
- * 3. Perform write operation.
- */
-void reset_cpu (unsigned long ignored)
-{
-	struct panthmpmu_registers *mpmu =
-		(struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
-	struct panthtmr_registers *panthtimers =
-		(struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
-	u32 val;
-
-	/* negate hardware reset to the WDT after system reset */
-	val = readl(&mpmu->aprr);
-	val = val | MPMU_APRR_WDTR;
-	writel(val, &mpmu->aprr);
-
-	/* reset/enable WDT clock */
-	writel(APBC_APBCLK, &mpmu->wdtpcr);
-
-	/* clear previous WDT status */
-	writel(TMR_WFAR, &panthtimers->wfar);
-	writel(TMP_WSAR, &panthtimers->wsar);
-	writel(0, &panthtimers->wdt_sts);
-
-	/* set match counter */
-	writel(TMR_WFAR, &panthtimers->wfar);
-	writel(TMP_WSAR, &panthtimers->wsar);
-	writel(0xf, &panthtimers->wdt_match_r);
-
-	/* enable WDT reset */
-	writel(TMR_WFAR, &panthtimers->wfar);
-	writel(TMP_WSAR, &panthtimers->wsar);
-	writel(0x3, &panthtimers->wdt_match_en);
-
-	/*enable functional WDT clock */
-	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	return (ulong)CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h
deleted file mode 100644
index 1eed7b1d56..0000000000
--- a/arch/arm/include/asm/arch-pantheon/config.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PANTHEON_CONFIG_H
-#define _PANTHEON_CONFIG_H
-
-#include <asm/arch/pantheon.h>
-
-/* default Dcache Line length for pantheon */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-#define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
-#define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */
-#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
-#define MV_MFPR_BASE		PANTHEON_MFPR_BASE
-#define MV_UART_CONSOLE_BASE	PANTHEON_UART1_BASE
-#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
-						represents UART Unit Enable */
-/*
- * I2C definition
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MV			1
-#define CONFIG_MV_I2C_REG		0xd4011000
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		0
-#define CONFIG_SYS_I2C_SLAVE		0xfe
-#endif
-
-/*
- * MMC definition
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT			1
-#define CONFIG_MMC			1
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_SDHCI			1
-#define CONFIG_MMC_SDHCI_IO_ACCESSORS	1
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT	0x1000
-#define CONFIG_MMC_SDMA			1
-#define CONFIG_MV_SDHCI			1
-#define CONFIG_DOS_PARTITION		1
-#define CONFIG_EFI_PARTITION		1
-#define CONFIG_SYS_MMC_NUM		2
-#define CONFIG_SYS_MMC_BASE		{0xD4280000, 0xd4281000}
-#endif
-
-#endif /* _PANTHEON_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h
deleted file mode 100644
index 3ccdf8a359..0000000000
--- a/arch/arm/include/asm/arch-pantheon/cpu.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PANTHEON_CPU_H
-#define _PANTHEON_CPU_H
-
-#include <asm/io.h>
-#include <asm/system.h>
-
-/*
- * Main Power Management (MPMU) Registers
- * Refer Register Datasheet 9.1
- */
-struct panthmpmu_registers {
-	u8 pad0[0x0024];
-	u32 ccgr;	/*0x0024*/
-	u8 pad1[0x0200 - 0x024 - 4];
-	u32 wdtpcr;	/*0x0200*/
-	u8 pad2[0x1020 - 0x200 - 4];
-	u32 aprr;	/*0x1020*/
-	u32 acgr;	/*0x1024*/
-};
-
-/*
- * Application Power Management (APMU) Registers
- * Refer Register Datasheet 9.2
- */
-struct panthapmu_registers {
-	u8 pad0[0x0054];
-	u32 sd1;	/*0x0054*/
-	u8 pad1[0x00e0 - 0x054 - 4];
-	u32 sd3;	/*0x00e0*/
-};
-
-/*
- * APB Clock Reset/Control Registers
- * Refer Register Datasheet 6.14
- */
-struct panthapb_registers {
-	u32 uart0;	/*0x000*/
-	u32 uart1;	/*0x004*/
-	u32 gpio;	/*0x008*/
-	u8 pad0[0x02c - 0x08 - 4];
-	u32 twsi;	/*0x02c*/
-	u8 pad1[0x034 - 0x2c - 4];
-	u32 timers;	/*0x034*/
-};
-
-/*
- * CPU Interface Registers
- * Refer Register Datasheet 4.3
- */
-struct panthcpu_registers {
-	u32 chip_id;		/* Chip Id Reg */
-	u32 pad;
-	u32 cpu_conf;		/* CPU Conf Reg */
-	u32 pad1;
-	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
-	u32 pad2;
-	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
-	u32 mcb_conf;		/* MCB Conf Reg */
-	u32 sys_boot_ctl;	/* Sytem Boot Control */
-};
-
-/*
- * Functions
- */
-u32 panth_sdram_base(int);
-u32 panth_sdram_size(int);
-int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
-
-#endif /* _PANTHEON_CPU_H */
diff --git a/arch/arm/include/asm/arch-pantheon/gpio.h b/arch/arm/include/asm/arch-pantheon/gpio.h
deleted file mode 100644
index e69de29bb2..0000000000
--- a/arch/arm/include/asm/arch-pantheon/gpio.h
+++ /dev/null
diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h
deleted file mode 100644
index 7909d53d46..0000000000
--- a/arch/arm/include/asm/arch-pantheon/mfp.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Based on arch/arm/include/asm/arch-armada100/mfp.h
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __PANTHEON_MFP_H
-#define __PANTHEON_MFP_H
-
-/*
- * Frequently used MFP Configuration macros for all PANTHEON family of SoCs
- *
- * offset, pull,pF, drv,dF, edge,eF ,afn,aF
- */
-/* UART2 */
-#define MFP47_UART2_RXD		(MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP48_UART2_TXD		(MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
-#define MFP53_CI2C_SCL		(MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFP54_CI2C_SDA		(MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-
-/* More macros can be defined here... */
-#define MFP_MMC1_DAT7		(MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT6		(MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT5		(MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT4		(MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_DAT3		(MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT2		(MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT1		(MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_DAT0		(MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CMD		(MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CLK		(MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST)
-#define MFP_MMC1_CD		(MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-#define MFP_MMC1_WP		(MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM)
-
-#define MFP_PIN_MAX	117
-#endif
diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h
deleted file mode 100644
index c3a71bfce4..0000000000
--- a/arch/arm/include/asm/arch-pantheon/pantheon.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _PANTHEON_H
-#define _PANTHEON_H
-
-/* Common APB clock register bit definitions */
-#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
-#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
-#define APBC_RST        (1<<2)  /* Reset Generation */
-/* Functional Clock Selection Mask */
-#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
-
-/* Common APMU register bit definitions */
-#define APMU_PERI_CLK	(1<<4)	/* Peripheral Clock Enable */
-#define APMU_AXI_CLK	(1<<3)	/* AXI Clock Enable*/
-#define APMU_PERI_RST	(1<<1)	/* Peripheral Reset */
-#define APMU_AXI_RST	(1<<0)	/* AXI Reset */
-
-/* Register Base Addresses */
-#define PANTHEON_DRAM_BASE	0xB0000000
-#define PANTHEON_TIMER_BASE	0xD4014000
-#define PANTHEON_WD_TIMER_BASE	0xD4080000
-#define PANTHEON_APBC_BASE	0xD4015000
-#define PANTHEON_UART1_BASE	0xD4017000
-#define PANTHEON_UART2_BASE	0xD4018000
-#define PANTHEON_GPIO_BASE	0xD4019000
-#define PANTHEON_MFPR_BASE	0xD401E000
-#define PANTHEON_MPMU_BASE	0xD4050000
-#define PANTHEON_APMU_BASE	0xD4282800
-#define PANTHEON_CPU_BASE	0xD4282C00
-
-#endif /* _PANTHEON_H */