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-rw-r--r--arch/arm/dts/imx6qdl-icore-rqs.dtsi7
-rw-r--r--arch/arm/dts/imx6qdl-icore.dtsi2
-rw-r--r--arch/arm/dts/imx6qdl.dtsi5
-rw-r--r--arch/arm/dts/imx6ul-geam-kit.dts4
-rw-r--r--arch/arm/dts/imx6ul-isiot-emmc.dts2
-rw-r--r--arch/arm/dts/imx6ul-isiot.dtsi2
-rw-r--r--arch/arm/dts/imx6ul.dtsi6
-rw-r--r--arch/arm/include/asm/arch-mx5/crm_regs.h8
-rw-r--r--arch/arm/include/asm/arch-mx5/imx-regs.h50
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h2
-rw-r--r--arch/arm/include/asm/mach-imx/sys_proto.h2
-rw-r--r--arch/arm/mach-imx/init.c12
-rw-r--r--arch/arm/mach-imx/mx5/Kconfig7
-rw-r--r--arch/arm/mach-imx/mx6/Kconfig60
-rw-r--r--arch/arm/mach-imx/mx6/soc.c2
-rw-r--r--arch/arm/mach-imx/mx7/soc.c2
16 files changed, 128 insertions, 45 deletions
diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
index 8b9d5b4b08..816cdce2f3 100644
--- a/arch/arm/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
@@ -43,6 +43,11 @@
#include <dt-bindings/clock/imx6qdl-clock.h>
/ {
+ aliases {
+ mmc1 = &usdhc3;
+ mmc2 = &usdhc4;
+ };
+
memory {
reg = <0x10000000 0x80000000>;
};
@@ -100,6 +105,7 @@
};
&usdhc3 {
+ u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -165,6 +171,7 @@
};
pinctrl_usdhc3: usdhc3grp {
+ u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070
diff --git a/arch/arm/dts/imx6qdl-icore.dtsi b/arch/arm/dts/imx6qdl-icore.dtsi
index a485c3eb95..06d9bc3a42 100644
--- a/arch/arm/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/dts/imx6qdl-icore.dtsi
@@ -118,6 +118,7 @@
};
&usdhc1 {
+ u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -208,6 +209,7 @@
};
pinctrl_usdhc1: usdhc1grp {
+ u-boot,dm-spl;
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index b13b0b2db8..e04b57089a 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -77,6 +77,7 @@
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
+ u-boot,dm-spl;
dma_apbh: dma-apbh@00110000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
@@ -225,6 +226,7 @@
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
+ u-boot,dm-spl;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
@@ -516,6 +518,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ u-boot,dm-spl;
};
gpio2: gpio@020a0000 {
@@ -805,6 +808,7 @@
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
+ u-boot,dm-spl;
};
ldb: ldb@020e0008 {
@@ -889,6 +893,7 @@
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
+ u-boot,dm-spl;
crypto: caam@2100000 {
compatible = "fsl,sec-v4.0";
diff --git a/arch/arm/dts/imx6ul-geam-kit.dts b/arch/arm/dts/imx6ul-geam-kit.dts
index 07c21cb0a2..15e3f94153 100644
--- a/arch/arm/dts/imx6ul-geam-kit.dts
+++ b/arch/arm/dts/imx6ul-geam-kit.dts
@@ -87,6 +87,7 @@
};
&usdhc1 {
+ u-boot,dm-spl;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@@ -134,6 +135,7 @@
};
pinctrl_usdhc1: usdhc1grp {
+ u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
@@ -145,6 +147,7 @@
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
@@ -156,6 +159,7 @@
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
diff --git a/arch/arm/dts/imx6ul-isiot-emmc.dts b/arch/arm/dts/imx6ul-isiot-emmc.dts
index 677de96473..a611e3bba5 100644
--- a/arch/arm/dts/imx6ul-isiot-emmc.dts
+++ b/arch/arm/dts/imx6ul-isiot-emmc.dts
@@ -50,6 +50,7 @@
};
&usdhc2 {
+ u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
@@ -60,6 +61,7 @@
&iomuxc {
pinctrl_usdhc2: usdhc2grp {
+ u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
diff --git a/arch/arm/dts/imx6ul-isiot.dtsi b/arch/arm/dts/imx6ul-isiot.dtsi
index 9a3c35c56a..5007a88f45 100644
--- a/arch/arm/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/dts/imx6ul-isiot.dtsi
@@ -82,6 +82,7 @@
};
&usdhc1 {
+ u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
@@ -128,6 +129,7 @@
};
pinctrl_usdhc1: usdhc1grp {
+ u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi
index def5f8cac9..7affab866f 100644
--- a/arch/arm/dts/imx6ul.dtsi
+++ b/arch/arm/dts/imx6ul.dtsi
@@ -134,6 +134,7 @@
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
+ u-boot,dm-spl;
pmu {
compatible = "arm,cortex-a7-pmu";
@@ -185,6 +186,7 @@
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
+ u-boot,dm-spl;
spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
@@ -415,6 +417,7 @@
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
<&iomuxc 16 33 16>;
+ u-boot,dm-spl;
};
gpio2: gpio@020a0000 {
@@ -451,6 +454,7 @@
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
+ u-boot,dm-spl;
};
gpio5: gpio@020ac000 {
@@ -649,6 +653,7 @@
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6ul-iomuxc";
reg = <0x020e0000 0x4000>;
+ u-boot,dm-spl;
};
gpr: iomuxc-gpr@020e4000 {
@@ -729,6 +734,7 @@
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
+ u-boot,dm-spl;
usbotg1: usb@02184000 {
compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index b61c7b970a..7fea569176 100644
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -210,6 +210,14 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET 26
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK (0x7 << 26)
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v) (((v) & 0x7) << 26)
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r) (((r) >> 26) & 0x7)
+
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5
+
/* Define the bits in register CSCDR2 */
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 3e79fa3224..61c8d440f8 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -416,6 +416,39 @@ struct iomuxc {
};
#endif
+#define IOMUXC_GPR2_BITMAP_SPWG 0
+#define IOMUXC_GPR2_BITMAP_JEIDA 1
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA << \
+ IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG << \
+ IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_18 0
+#define IOMUXC_GPR2_DATA_WIDTH_24 1
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18 << \
+ IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24 << \
+ IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+
+#define IOMUXC_GPR2_MODE_DISABLED 0
+#define IOMUXC_GPR2_MODE_ENABLED_DI0 1
+#define IOMUXC_GPR2_MODE_ENABLED_DI1 3
+
+#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
+#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED << \
+ IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0 << \
+ IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1 << \
+ IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+
/* System Reset Controller (SRC) */
struct src {
u32 scr;
@@ -508,6 +541,23 @@ struct fuse_bank4_regs {
};
#endif
+#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN (1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
+struct pwm_regs {
+ u32 cr;
+ u32 sr;
+ u32 ir;
+ u32 sar;
+ u32 pr;
+ u32 cnr;
+};
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 624ccecfd6..7736b6a8ac 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -367,7 +367,7 @@
#include <asm/types.h>
/* only for i.MX6SX/UL */
-#define WDOG3_BASE_ADDR ((is_mx6ul() ? \
+#define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ? \
MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \
MX6SLL_LCDIF_BASE_ADDR : \
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 703634334f..a80a392a73 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -105,7 +105,7 @@ void set_chipselect_size(int const);
void init_aips(void);
void init_src(void);
-void imx_set_wdog_powerdown(bool enable);
+void imx_wdog_disable_powerdown(void);
int board_mmc_get_env_dev(int devno);
diff --git a/arch/arm/mach-imx/init.c b/arch/arm/mach-imx/init.c
index 720ad672a6..0aa8295751 100644
--- a/arch/arm/mach-imx/init.c
+++ b/arch/arm/mach-imx/init.c
@@ -65,7 +65,7 @@ void init_aips(void)
}
}
-void imx_set_wdog_powerdown(bool enable)
+void imx_wdog_disable_powerdown(void)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
@@ -75,13 +75,13 @@ void imx_set_wdog_powerdown(bool enable)
#endif
/* Write to the PDE (Power Down Enable) bit */
- writew(enable, &wdog1->wmcr);
- writew(enable, &wdog2->wmcr);
+ writew(0, &wdog1->wmcr);
+ writew(0, &wdog2->wmcr);
- if (is_mx6sx() || is_mx6ul() || is_mx7())
- writew(enable, &wdog3->wmcr);
+ if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx7())
+ writew(0, &wdog3->wmcr);
#ifdef CONFIG_MX7D
- writew(enable, &wdog4->wmcr);
+ writew(0, &wdog4->wmcr);
#endif
}
diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
index d96020d847..250194b623 100644
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@@ -46,6 +46,12 @@ config TARGET_MX53LOCO
select BOARD_LATE_INIT
select MX53
+config TARGET_MX53PPD
+ bool "Support mx53ppd"
+ select MX53
+ help
+ Enable support for the GE Healthcare PPD.
+
config TARGET_MX53SMD
bool "Support mx53smd"
select MX53
@@ -70,6 +76,7 @@ source "board/freescale/mx53ard/Kconfig"
source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/freescale/mx53smd/Kconfig"
+source "board/ge/mx53ppd/Kconfig"
source "board/inversepath/usbarmory/Kconfig"
source "board/technologic/ts4800/Kconfig"
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index fd73c67fde..bee7eabe02 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -109,6 +109,7 @@ config TARGET_ARISTAINETOS2B
config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
select DM
@@ -117,6 +118,7 @@ config TARGET_CGTQMX6EVAL
config TARGET_CM_FX6
bool "CM-FX6"
select SUPPORT_SPL
+ select MX6QDL
select DM
select DM_SERIAL
select DM_GPIO
@@ -131,6 +133,7 @@ config TARGET_COLIBRI_IMX6
config TARGET_DHCOMIMX6
bool "dh_imx6"
+ select MX6QDL
select BOARD_LATE_INIT
select BOARD_EARLY_INIT_F
select SUPPORT_SPL
@@ -165,6 +168,7 @@ config TARGET_GE_B850V3
config TARGET_GW_VENTANA
bool "gw_ventana"
+ select MX6QDL
select SUPPORT_SPL
imply CMD_SATA
imply CMD_SPL
@@ -176,10 +180,12 @@ config TARGET_KOSAGI_NOVENA
config TARGET_MCCMON6
bool "mccmon6"
+ select MX6QDL
select SUPPORT_SPL
config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
@@ -199,23 +205,8 @@ config TARGET_MX6LOGICPD
config TARGET_MX6QARM2
bool "mx6qarm2"
-config TARGET_MX6Q_ICORE
- bool "Support Engicam i.Core"
- select BOARD_LATE_INIT
- select MX6QDL
- select OF_CONTROL
- select SPL_OF_LIBFDT
- select DM
- select DM_ETH
- select DM_GPIO
- select DM_I2C
- select DM_MMC
- select DM_THERMAL
- select SUPPORT_SPL
- select SPL_LOAD_FIT
-
-config TARGET_MX6Q_ICORE_RQS
- bool "Support Engicam i.Core RQS"
+config TARGET_MX6Q_ENGICAM
+ bool "Support Engicam i.Core(RQS)"
select BOARD_LATE_INIT
select MX6QDL
select OF_CONTROL
@@ -228,9 +219,14 @@ config TARGET_MX6Q_ICORE_RQS
select DM_THERMAL
select SUPPORT_SPL
select SPL_LOAD_FIT
+ select SPL_DM if SPL
+ select SPL_OF_CONTROL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SPL_PINCTRL if SPL
config TARGET_MX6SABREAUTO
bool "mx6sabreauto"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
select DM
@@ -239,6 +235,7 @@ config TARGET_MX6SABREAUTO
config TARGET_MX6SABRESD
bool "mx6sabresd"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
select DM
@@ -288,20 +285,8 @@ config TARGET_MX6UL_14X14_EVK
select DM_THERMAL
select SUPPORT_SPL
-config TARGET_MX6UL_GEAM
- bool "Support Engicam GEAM6UL"
- select BOARD_LATE_INIT
- select MX6UL
- select OF_CONTROL
- select DM
- select DM_ETH
- select DM_GPIO
- select DM_I2C
- select DM_MMC
- select DM_THERMAL
- select SUPPORT_SPL
-config TARGET_MX6UL_ISIOT
- bool "Support Engicam Is.IoT MX6UL"
+config TARGET_MX6UL_ENGICAM
+ bool "Support Engicam GEAM6UL/Is.IoT"
select BOARD_LATE_INIT
select MX6UL
select OF_CONTROL
@@ -312,6 +297,10 @@ config TARGET_MX6UL_ISIOT
select DM_MMC
select DM_THERMAL
select SUPPORT_SPL
+ select SPL_DM if SPL
+ select SPL_OF_CONTROL if SPL
+ select SPL_SEPARATE_BSS if SPL
+ select SPL_PINCTRL if SPL
config TARGET_MX6ULL_14X14_EVK
bool "Support mx6ull_14x14_evk"
@@ -360,6 +349,7 @@ config TARGET_PCM058
config TARGET_PFLA02
bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
@@ -378,6 +368,7 @@ config TARGET_TQMA6
config TARGET_UDOO
bool "udoo"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
@@ -398,6 +389,7 @@ config TARGET_SAMTEC_VINING_2000
config TARGET_WANDBOARD
bool "wandboard"
+ select MX6QDL
select BOARD_LATE_INIT
select SUPPORT_SPL
@@ -446,10 +438,8 @@ source "board/congatec/cgtqmx6eval/Kconfig"
source "board/dhelectronics/dh_imx6/Kconfig"
source "board/el/el6x/Kconfig"
source "board/embest/mx6boards/Kconfig"
-source "board/engicam/geam6ul/Kconfig"
-source "board/engicam/icorem6/Kconfig"
-source "board/engicam/icorem6_rqs/Kconfig"
-source "board/engicam/isiotmx6ul/Kconfig"
+source "board/engicam/imx6q/Kconfig"
+source "board/engicam/imx6ul/Kconfig"
source "board/freescale/mx6qarm2/Kconfig"
source "board/freescale/mx6sabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index ad72c12511..43cb58106b 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -436,7 +436,7 @@ int arch_cpu_init(void)
if (is_mx6sl())
setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
- imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+ imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
if (is_mx6sx())
setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 87bf105f38..d160e80146 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -236,7 +236,7 @@ int arch_cpu_init(void)
init_csu();
/* Disable PDE bit of WMCR register */
- imx_set_wdog_powerdown(false);
+ imx_wdog_disable_powerdown();
imx_enet_mdio_fixup();
generated by cgit (git 2.34.1) at 2025-01-14 06:23:50 +0000