3 files changed, 62 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_defs.h b/arch/arm/include/asm/arch-stm32f4/stm32_defs.h
new file mode 100644
index 0000000000..29b98aecf4
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/stm32_defs.h
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __STM32_DEFS_H__
+#define __STM32_DEFS_H__
+#include <asm/arch/stm32_periph.h>
+
+int clock_setup(enum periph_clock);
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_periph.h b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h
new file mode 100644
index 0000000000..a1af25cb58
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/stm32_periph.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PERIPH_H
+#define __ASM_ARM_ARCH_PERIPH_H
+
+/*
+ * Peripherals required for pinmux configuration. List will
+ * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
+ *
+ */
+enum periph_id {
+	UART1_GPIOA_9_10 = 0,
+	UART2_GPIOD_5_6,
+};
+
+enum periph_clock {
+	USART1_CLOCK_CFG = 0,
+	USART2_CLOCK_CFG,
+};
+
+#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c
index 3deb17aa83..576d3e68ae 100644
--- a/arch/arm/mach-stm32/stm32f4/clock.c
+++ b/arch/arm/mach-stm32/stm32f4/clock.c
@@ -11,6 +11,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/stm32.h>
+#include <asm/arch/stm32_periph.h>
 
 #define RCC_CR_HSION		(1 << 0)
 #define RCC_CR_HSEON		(1 << 16)
@@ -50,6 +51,14 @@
 
 #define RCC_APB1ENR_PWREN	(1 << 28)
 
+/*
+ * RCC USART specific definitions
+ */
+#define RCC_ENR_USART1EN		(1 << 4)
+#define RCC_ENR_USART2EN		(1 << 17)
+#define RCC_ENR_USART3EN		(1 << 18)
+#define RCC_ENR_USART6EN		(1 <<  5)
+
 #define PWR_CR_VOS0		(1 << 14)
 #define PWR_CR_VOS1		(1 << 15)
 #define PWR_CR_VOS_MASK		0xC000
@@ -221,3 +230,14 @@ unsigned long clock_get(enum clock clck)
 		break;
 	}
 }
+
+void clock_setup(int peripheral)
+{
+	switch (peripheral) {
+	case USART1_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);
+		break;
+	default:
+		break;
+	}
+}