diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/dts/armada-388-clearfog.dts | 10 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/cpu.c | 41 |
2 files changed, 45 insertions, 6 deletions
diff --git a/arch/arm/dts/armada-388-clearfog.dts b/arch/arm/dts/armada-388-clearfog.dts index b2dfd56435..bc52bc0167 100644 --- a/arch/arm/dts/armada-388-clearfog.dts +++ b/arch/arm/dts/armada-388-clearfog.dts @@ -61,6 +61,7 @@ ethernet1 = ð0; ethernet2 = ð1; ethernet3 = ð2; + spi1 = &spi1; }; chosen { @@ -330,11 +331,9 @@ status = "okay"; }; - spi@10680 { + spi1: spi@10680 { /* - * We don't seem to have the W25Q32 on the - * A1 Rev 2.0 boards, so disable SPI. - * CS0: W25Q32 (doesn't appear to be present) + * CS0: W25Q32 * CS1: * CS2: mikrobus */ @@ -345,10 +344,9 @@ spi-flash@0 { #address-cells = <1>; #size-cells = <0>; - compatible = "w25q32", "jedec,spi-nor"; + compatible = "w25q32", "jedec,spi-nor", "spi-flash"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <3000000>; - status = "disabled"; }; }; diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 74a63dd656..7c64a68388 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -554,6 +554,47 @@ void scsi_init(void) } #endif +#ifdef CONFIG_USB_XHCI_MVEBU +#define USB3_MAX_WINDOWS 4 +#define USB3_WIN_CTRL(w) (0x0 + ((w) * 8)) +#define USB3_WIN_BASE(w) (0x4 + ((w) * 8)) + +static void xhci_mvebu_mbus_config(void __iomem *base, + const struct mbus_dram_target_info *dram) +{ + int i; + + for (i = 0; i < USB3_MAX_WINDOWS; i++) { + writel(0, base + USB3_WIN_CTRL(i)); + writel(0, base + USB3_WIN_BASE(i)); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + + /* Write size, attributes and target id to control register */ + writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + base + USB3_WIN_CTRL(i)); + + /* Write base address to base register */ + writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i)); + } +} + +int board_xhci_enable(fdt_addr_t base) +{ + const struct mbus_dram_target_info *dram; + + printf("MVEBU XHCI INIT controller @ 0x%lx\n", base); + + dram = mvebu_mbus_dram_info(); + xhci_mvebu_mbus_config((void __iomem *)base, dram); + + return 0; +} +#endif + void enable_caches(void) { /* Avoid problem with e.g. neta ethernet driver */ |