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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/dts/Makefile3
-rw-r--r--arch/arm/dts/zynq-cse-nand.dts80
-rw-r--r--arch/arm/dts/zynq-cse-nor.dts88
-rw-r--r--arch/arm/dts/zynqmp-mini-qspi.dts79
-rw-r--r--arch/arm/dts/zynqmp-zcu100-revC.dts2
-rw-r--r--arch/arm/mach-mvebu/arm64-common.c2
-rw-r--r--arch/arm/mach-socfpga/misc.c2
-rw-r--r--arch/arm/mach-zynq/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-zynq/spl.c3
10 files changed, 260 insertions, 2 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5b3746c80b..64d58a6241 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1474,6 +1474,8 @@ source "board/toradex/colibri_pxa270/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
+source "board/xilinx/Kconfig"
+source "board/xilinx/zynq/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
source "board/zipitz2/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9607239b03..094c41b3de 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -129,6 +129,8 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
+ zynq-cse-nand.dtb \
+ zynq-cse-nor.dtb \
zynq-cse-qspi-single.dtb \
zynq-microzed.dtb \
zynq-minized.dtb \
@@ -150,6 +152,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
+ zynqmp-mini-qspi.dtb \
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
new file mode 100644
index 0000000000..9b1dd19a85
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NAND board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zynq CSE NAND Board";
+ compatible = "xlnx,zynq-cse-nand", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 = &dcc;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x400000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ slcr: slcr@f8000000 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ reg = <0xF8000000 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ u-boot,dm-pre-reloc;
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ clock-output-names = "armpll", "ddrpll",
+ "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0",
+ "gem1", "fclk0", "fclk1",
+ "fclk2", "fclk3", "can0",
+ "can1", "sdio0", "sdio1",
+ "uart0", "uart1", "spi0",
+ "spi1", "dma", "usb0_aper",
+ "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper",
+ "sdio1_aper", "spi0_aper",
+ "spi1_aper", "can0_aper",
+ "can1_aper", "i2c0_aper",
+ "i2c1_aper", "uart0_aper",
+ "uart1_aper", "gpio_aper",
+ "lqspi_aper", "smc_aper",
+ "swdt", "dbg_trc", "dbg_apb";
+ reg = <0x100 0x100>;
+ };
+ };
+ };
+
+};
+
+&dcc {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
new file mode 100644
index 0000000000..ba6f9a1a79
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE NOR board DTS
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Zynq CSE NOR Board";
+ compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 = &dcc;
+ };
+
+ memory@fffc0000 {
+ device_type = "memory";
+ reg = <0xFFFC0000 0x40000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+
+ intc: interrupt-controller@f8f01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xF8F01000 0x1000>,
+ <0xF8F00100 0x100>;
+ };
+
+ slcr: slcr@f8000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+ reg = <0xF8000000 0x1000>;
+ ranges;
+ clkc: clkc@100 {
+ #clock-cells = <1>;
+ compatible = "xlnx,ps7-clkc";
+ fclk-enable = <0xf>;
+ clock-output-names = "armpll", "ddrpll",
+ "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x", "cpu_1x",
+ "ddr2x", "ddr3x", "dci",
+ "lqspi", "smc", "pcap", "gem0",
+ "gem1", "fclk0", "fclk1",
+ "fclk2", "fclk3", "can0",
+ "can1", "sdio0", "sdio1",
+ "uart0", "uart1", "spi0",
+ "spi1", "dma", "usb0_aper",
+ "usb1_aper", "gem0_aper",
+ "gem1_aper", "sdio0_aper",
+ "sdio1_aper", "spi0_aper",
+ "spi1_aper", "can0_aper",
+ "can1_aper", "i2c0_aper",
+ "i2c1_aper", "uart0_aper",
+ "uart1_aper", "gpio_aper",
+ "lqspi_aper", "smc_aper",
+ "swdt", "dbg_trc", "dbg_apb";
+ reg = <0x100 0x100>;
+ };
+ };
+ };
+
+};
+
+&dcc {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts
new file mode 100644
index 0000000000..c235a5f731
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP Mini Configuration
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+/ {
+ model = "ZynqMP MINI QSPI";
+ compatible = "xlnx,zynqmp";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &dcc;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@fffc0000 {
+ device_type = "memory";
+ reg = <0x0 0xfffc0000 0x40000>;
+ };
+
+ dcc: dcc {
+ compatible = "arm,dcc";
+ status = "disabled";
+ u-boot,dm-pre-reloc;
+ };
+
+ amba: amba {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ qspi: spi@ff0f0000 {
+ compatible = "xlnx,zynqmp-qspi-1.0";
+ status = "disabled";
+ clock-names = "ref_clk", "pclk";
+ clocks = <&misc_clk &misc_clk>;
+ num-cs = <1>;
+ reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ misc_clk: misc_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+ };
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "n25q512a11";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 6e575a063b..2fffe177b5 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -280,11 +280,13 @@
&spi0 { /* Low Speed connector */
status = "okay";
label = "LS-SPI0";
+ num-cs = <1>;
};
&spi1 { /* High Speed connector */
status = "okay";
label = "HS-SPI1";
+ num-cs = <1>;
};
&uart0 {
diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index d3ea9e67e0..f47273fde9 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -54,7 +54,7 @@ int dram_init_banksize(void)
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
return 0;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 77628e1181..a4f6d5c1ac 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -40,7 +40,7 @@ struct bsel bsel_str[] = {
int dram_init(void)
{
- if (fdtdec_setup_memory_size() != 0)
+ if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
return 0;
diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h
index f69cf004ec..3ff3c1073e 100644
--- a/arch/arm/mach-zynq/include/mach/hardware.h
+++ b/arch/arm/mach-zynq/include/mach/hardware.h
@@ -20,6 +20,7 @@
#define ZYNQ_EFUSE_BASEADDR 0xF800D000
#define ZYNQ_USB_BASEADDR0 0xE0002000
#define ZYNQ_USB_BASEADDR1 0xE0003000
+#define ZYNQ_OCM_BASEADDR 0xFFFC0000
/* Bootmode setting values */
#define ZYNQ_BM_MASK 0x7
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index 83297d6c69..9b7c0be951 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -29,6 +29,9 @@ void board_init_f(ulong dummy)
void spl_board_init(void)
{
preloader_console_init();
+#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA_SUPPORT)
+ arch_early_init_r();
+#endif
board_init();
}
#endif
generated by cgit (git 2.34.1) at 2025-01-09 08:14:35 +0000