diff options
Diffstat (limited to 'arch/blackfin/include/asm/mach-common')
| -rw-r--r-- | arch/blackfin/include/asm/mach-common/bits/cgu.h | 80 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/mach-common/bits/dde.h | 88 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/mach-common/bits/mpu.h | 6 | ||||
| -rw-r--r-- | arch/blackfin/include/asm/mach-common/bits/pll.h | 5 |
4 files changed, 178 insertions, 1 deletions
diff --git a/arch/blackfin/include/asm/mach-common/bits/cgu.h b/arch/blackfin/include/asm/mach-common/bits/cgu.h new file mode 100644 index 0000000000..cdf7349925 --- /dev/null +++ b/arch/blackfin/include/asm/mach-common/bits/cgu.h @@ -0,0 +1,80 @@ +/* + * CGU Masks + */ + +#ifndef __BFIN_PERIPHERAL_CGU__ +#define __BFIN_PERIPHERAL_CGU__ + +/* CGU_CTL Masks */ +#define DF (1 << 0) +#define MSEL (0x7f << MSEL_P) +#define WIDLE (1 << WIDLE_P) +#define LOCK (1 << LOCK_P) + +#define DF_P 0 +#define MSEL_P 8 +#define WIDLE_P 30 +#define LOCK_P 31 +#define MSEL_MASK 0x7F00 +#define DF_MASK 0x1 + +/* CGU_STAT Masks */ +#define PLLEN (1 << 0) +#define PLLBP (1 << 1) +#define PLLLK (1 << 2) +#define CLKSALGN (1 << 3) +#define CCBF0EN (1 << 4) +#define CCBF1EN (1 << 5) +#define SCBF0EN (1 << 6) +#define SCBF1EN (1 << 7) +#define DCBFEN (1 << 8) +#define OCBFEN (1 << 9) +#define ADRERR (1 << 16) +#define LWERR (1 << 17) +#define DIVERR (1 << 18) +#define WDFMSERR (1 << 19) +#define WDIVERR (1 << 20) +#define PLLLKERR (1 << 21) + +/* CGU_DIV Masks */ +#define CSEL (0x1f << CSEL_P) +#define S0SEL (3 << S0SEL_P) +#define SYSSEL (0x1f << SYSSEL_P) +#define S1SEL (3 << S1SEL_P) +#define DSEL (0x1f << DSEL_P) +#define OSEL (0x7f << OSEL_P) +#define ALGN (1 << ALGN_P) +#define UPDT (1 << UPDT_P) +#define LOCK (1 << LOCK_P) + +#define CSEL_P 0 +#define S0SEL_P 5 +#define SYSSEL_P 8 +#define S1SEL_P 13 +#define DSEL_P 16 +#define OSEL_P 22 +#define ALGN_P 29 +#define UPDT_P 30 +#define LOCK_P 31 + +/* CGU_CLKOUTSEL Masks */ +#define CLKOUTSEL (0xf << 0) +#define USBCLKSEL (0x3f << 16) +#define LOCK (1 << LOCK_P) + +#define LOCK_P 31 + +#define CLKOUTSEL_CLKIN 0x0 +#define CLKOUTSEL_CCLK 0x1 +#define CLKOUTSEL_SYSCLK 0x2 +#define CLKOUTSEL_SCLK0 0x3 +#define CLKOUTSEL_SCLK1 0x4 +#define CLKOUTSEL_DCLK 0x5 +#define CLKOUTSEL_USB_PLL 0x6 +#define CLKOUTSEL_OUTCLK 0x7 +#define CLKOUTSEL_USB_CLKIN 0x8 +#define CLKOUTSEL_WDOG 0x9 +#define CLKOUTSEL_PMON 0xA +#define CLKOUTSEL_GND 0xB + +#endif diff --git a/arch/blackfin/include/asm/mach-common/bits/dde.h b/arch/blackfin/include/asm/mach-common/bits/dde.h new file mode 100644 index 0000000000..f7b0bb90f3 --- /dev/null +++ b/arch/blackfin/include/asm/mach-common/bits/dde.h @@ -0,0 +1,88 @@ +/* + * Distributed DMA Engine (DDE) Masks + */ + +#ifndef __BFIN_PERIPHERAL_DDE__ +#define __BFIN_PERIPHERAL_DDE__ + +/* DMA_CONFIG Masks */ +#define DMAEN (1 << DMAEN_P) /* DMA Channel Enable */ +#define WNR (1 << WNR_P) /* Channel Direction (W/R*) */ +#define SYNC (1 << SYNC_P) /* Sync Work Unit Transitions */ +#define CADDR (1 << CADDR_P) /* Use Current Address */ +#define PSIZE (7 << PSIZE_P) /* Peripheral Word Size */ +#define PSIZE_1 (0 << PSIZE_P) +#define PSIZE_2 (1 << PSIZE_P) +#define PSIZE_4 (2 << PSIZE_P) +#define PSIZE_8 (3 << PSIZE_P) +#define MSIZE (7 << MSIZE_P) /* Memory Transfer Size */ +#define MSIZE_1 (0 << MSIZE_P) +#define MSIZE_2 (1 << MSIZE_P) +#define MSIZE_4 (2 << MSIZE_P) +#define MSIZE_8 (3 << MSIZE_P) +#define MSIZE_16 (4 << MSIZE_P) +#define MSIZE_32 (5 << MSIZE_P) +#define FLOW (7 << FLOW_P) /* Next Operation */ +#define FLOW_STOP (0 << FLOW_P) /* Stop Mode */ +#define FLOW_AUTO (1 << FLOW_P) /* Autobuffer Mode */ +#define FLOW_DSCL (4 << FLOW_P) /* Descriptor List */ +#define FLOW_DSCA (5 << FLOW_P) /* Descriptor Array */ +#define FLOW_DSDL (6 << FLOW_P) /* Descriptor On Demand List */ +#define FLOW_DSDA (7 << FLOW_P) /* Descriptor On Demand Array */ +#define NDSIZE (7 << NDSIZE_P) /* Next Descriptor Set Size */ +#define NDSIZE_1 (0 << NDSIZE_P) +#define NDSIZE_2 (1 << NDSIZE_P) +#define NDSIZE_3 (2 << NDSIZE_P) +#define NDSIZE_4 (3 << NDSIZE_P) +#define NDSIZE_5 (4 << NDSIZE_P) +#define NDSIZE_6 (5 << NDSIZE_P) +#define NDSIZE_7 (6 << NDSIZE_P) +#define DI_EN_X (1 << INT_P) +#define DI_EN_Y (2 << INT_P) +#define DI_EN_P (3 << INT_P) +#define DI_EN (DI_EN_X) +#define DI_XCOUNT_EN (1 << INT_P) /* xcount expires interrupt */ +#define TRIG (3 << TRIG_P) /* Generate Trigger */ +#define TOVEN (1 << TOVEN_P) +#define DESCIDCPY (1 << DESCIDCPY_P) +#define TWOD (1 << TWOD_P) +#define PDRF (1 << PDRF_P) + +#define DMAEN_P 0 +#define WNR_P 1 +#define SYNC_P 2 +#define CADDR_P 3 +#define PSIZE_P 4 +#define MSIZE_P 8 +#define FLOW_P 12 +#define TWAIT_P 15 +#define NDSIZE_P 16 +#define INT_P 20 +#define TRIG_P 22 +#define TOVEN_P 24 +#define DESCIDCPY_P 25 +#define TWOD_P 26 +#define PDRF_P 28 + +/* DMA_STATUS Masks */ +#define DMA_DONE (1 << DMA_DONE_P) /* Work Unit/Row Done */ +#define DMA_ERR (1 << DMA_ERR_P) /* Error Interrupt */ +#define DMA_PIRQ (1 << DMA_PIRQ_P) /* Peri Intr Request */ +#define DMA_ERRC (7 << DMA_ERRC_P) /* Error Cause */ +#define DMA_RUN (7 << DMA_RUN_P) /* Run Status */ +#define DMA_PBWIDTH (3 << DMA_PBWIDTH_P) /* Peri Bus Width */ +#define DMA_MBWIDTH (3 << DMA_MBWIDTH_P) /* Memory Bus Width */ +#define DMA_FIFOFILL (7 << DMA_FIFOFILL_P) /* FIFO Fill Status */ +#define DMA_TWAIT (1 << DMA_TWAIT_P) /* Trigger Wait Stat */ + +#define DMA_DONE_P 0 +#define DMA_ERR_P 1 +#define DMA_PIRQ_P 2 +#define DMA_ERRC_P 4 +#define DMA_RUN_P 8 +#define DMA_PBWIDTH_P 12 +#define DMA_MBWIDTH_P 14 +#define DMA_FIFOFILL_P 16 +#define DMA_TWAIT_P 20 + +#endif diff --git a/arch/blackfin/include/asm/mach-common/bits/mpu.h b/arch/blackfin/include/asm/mach-common/bits/mpu.h index 39998f82aa..cfde2364d7 100644 --- a/arch/blackfin/include/asm/mach-common/bits/mpu.h +++ b/arch/blackfin/include/asm/mach-common/bits/mpu.h @@ -70,7 +70,11 @@ #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ -#define PAGE_SIZE_MASK 0x00030000 /* the bits for the page_size field */ +#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */ +#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */ +#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */ +#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */ +#define PAGE_SIZE_MASK 0x00070000 /* page_size field mask */ #define PAGE_SIZE_SHIFT 16 #define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */ #define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ diff --git a/arch/blackfin/include/asm/mach-common/bits/pll.h b/arch/blackfin/include/asm/mach-common/bits/pll.h index 9009f26401..fe0ba0f543 100644 --- a/arch/blackfin/include/asm/mach-common/bits/pll.h +++ b/arch/blackfin/include/asm/mach-common/bits/pll.h @@ -16,6 +16,8 @@ #define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ #define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */ +#define MSEL_P 9 + /* PLL_DIV Masks */ #define SSEL 0x000F /* System Select */ #define CSEL 0x0030 /* Core Select */ @@ -29,6 +31,9 @@ #define CCLK_DIV4 CSEL_DIV4 #define CCLK_DIV8 CSEL_DIV8 +#define SSEL_P 0 +#define CSEL_P 4 + /* PLL_STAT Masks */ #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ #define FULL_ON 0x0002 /* Processor In Full On Mode */ |