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-rw-r--r--arch/mips/dts/mscc,serval.dtsi149
-rw-r--r--arch/mips/dts/serval_pcb105.dts56
2 files changed, 205 insertions, 0 deletions
diff --git a/arch/mips/dts/mscc,serval.dtsi b/arch/mips/dts/mscc,serval.dtsi
new file mode 100644
index 0000000000..bd60051719
--- /dev/null
+++ b/arch/mips/dts/mscc,serval.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,serval";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <&cpu_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpuintc: interrupt-controller@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <416666666>;
+ };
+
+ sys_clk: sys-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <208333333>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <208333333>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x70000000 0x2000000>;
+
+ interrupt-parent = <&intc>;
+
+ cpu_ctrl: syscon@0 {
+ compatible = "mscc,serval-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ intc: interrupt-controller@70 {
+ compatible = "mscc,serval-icpu-intr";
+ reg = <0x70 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@100000 {
+ pinctrl-0 = <&uart_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100000 0x20>;
+ interrupts = <6>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@100800 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100800 0x20>;
+ interrupts = <7>;
+ clocks = <&ahb_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ reset@1070008 {
+ compatible = "mscc,serval-chip-reset";
+ reg = <0x1070008 0x4>;
+ };
+
+ gpio: pinctrl@1070034 {
+ compatible = "mscc,serval-pinctrl";
+ reg = <0x1070034 0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 22>;
+
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1";
+ function = "sio";
+ };
+
+ uart_pins: uart-pins {
+ pins = "GPIO_26", "GPIO_27";
+ function = "uart";
+ };
+
+ uart2_pins: uart2-pins {
+ pins = "GPIO_13", "GPIO_14";
+ function = "uart2";
+ };
+ };
+
+ spi0: spi-bitbang {
+ compatible = "mscc,luton-bb-spi";
+ status = "okay";
+ reg = <0x50 0x4>;
+ num-chipselects = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sgpio: gpio@10700b4 {
+ compatible = "mscc,luton-sgpio";
+ status = "disabled";
+ clocks = <&sys_clk>;
+ pinctrl-0 = <&sgpio_pins>;
+ pinctrl-names = "default";
+ reg = <0x10700b4 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&sgpio 0 0 64>;
+ };
+ };
+};
diff --git a/arch/mips/dts/serval_pcb105.dts b/arch/mips/dts/serval_pcb105.dts
new file mode 100644
index 0000000000..d0d6facba2
--- /dev/null
+++ b/arch/mips/dts/serval_pcb105.dts
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,serval.dtsi"
+
+/ {
+ model = "Serval PCB105 Reference Board";
+ compatible = "mscc,serval-pcb105", "mscc,serval";
+
+ aliases {
+ spi0 = &spi0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ status_green {
+ label = "pcb105:green:status";
+ gpios = <&sgpio 43 1>; /* p11.1 */
+ default-state = "on";
+ };
+
+ status_red {
+ label = "pcb105:red:status";
+ gpios = <&sgpio 11 1>; /* p11.0 */
+ default-state = "off";
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <18000000>; /* input clock */
+ reg = <0>; /* CS0 */
+ spi-cs-high;
+ };
+};
+
+&sgpio {
+ status = "okay";
+ sgpio-ports = <0x00FFFFFF>;
+};