diff options
Diffstat (limited to 'arch/nds32/cpu/n1213/ag101/lowlevel_init.S')
| -rw-r--r-- | arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 59 |
1 files changed, 22 insertions, 37 deletions
diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S index abdd340479..452d814042 100644 --- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S +++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S @@ -86,25 +86,7 @@ bnez $r1, 1b .endm -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -.globl lowlevel_init -lowlevel_init: - move $r10, $lp - - led 0x0 - jal mem_init - - led 0x10 - jal remap - -#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) - led 0x1f - jal enable_fpu -#endif - - led 0x20 - ret $r10 - +.globl mem_init mem_init: move $r11, $lp @@ -124,9 +106,7 @@ mem_init: lwi $r1, [$r0+#0x00] ori $r1, $r1, 0x8f0 xori $r1, $r1, 0x8f0 - /* - * check board - */ + /* check board */ li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG lwi $r3, [$r3] li $r4, BOARD_ID_FAMILY_MASK @@ -134,29 +114,21 @@ mem_init: li $r4, BOARD_ID_FAMILY_K7 xor $r4, $r3, $r4 beqz $r4, use_flash_16bit_boot - /* - * 32-bit mode - */ + /* 32-bit mode */ use_flash_32bit_boot: ori $r1, $r1, 0x50 li $r2, 0x00151151 j sdram_b0_cr - /* - * 16-bit mode - */ + /* 16-bit mode */ use_flash_16bit_boot: ori $r1, $r1, 0x60 li $r2, 0x00153153 - /* - * SRAM bank0 config - */ + /* SRAM bank0 config */ sdram_b0_cr: swi $r1, [$r0+#0x00] swi $r2, [$r0+#0x04] - /* - * config AHB Controller - */ + /* config AHB Controller */ led 0x02 /* @@ -192,6 +164,21 @@ sdram_b0_cr: move $lp, $r11 ret + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + +.globl lowlevel_init +lowlevel_init: + move $r10, $lp + led 0x10 + jal remap +#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) + led 0x1f + jal enable_fpu +#endif + led 0x20 + ret $r10 + remap: move $r11, $lp #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */ @@ -203,9 +190,7 @@ relo_base: mfusr $r0, $pc #endif /* __NDS32_N1213_43U1H__ */ - /* - * Remapping - */ + /* Remapping */ led 0x1a write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001800 write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001880 |