diff options
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Makefile | 2 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 51 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu.c | 106 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 58 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 6 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/fdt.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/mp.c | 23 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/p1022_serdes.c | 98 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 5 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/tlb.c | 70 |
10 files changed, 257 insertions, 166 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index f064fee26b..4ee0e9af8c 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -32,6 +32,7 @@ START = start.o resetvec.o SOBJS-$(CONFIG_MP) += release.o SOBJS = $(SOBJS-y) +COBJS-$(CONFIG_CMD_ERRATA) += cmd_errata.o COBJS-$(CONFIG_CPM2) += commproc.o # supports ddr1 @@ -63,6 +64,7 @@ COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o +COBJS-$(CONFIG_P1022) += p1022_serdes.o COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c new file mode 100644 index 0000000000..d7835c8d69 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -0,0 +1,51 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <linux/compiler.h> +#include <asm/processor.h> + +static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + __maybe_unused u32 svr = get_svr(); + +#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) + if (IS_SVR_REV(svr, 1, 0)) { + switch (SVR_SOC_VER(svr)) { + case SVR_P1013: + case SVR_P1013_E: + case SVR_P1022: + case SVR_P1022_E: + puts("Work-around for Erratum SATA A001 enabled\n"); + } + } +#endif + + return 0; +} + +U_BOOT_CMD( + errata, 1, 0, do_errata, + "Report errata workarounds", + "" +); diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 6f81fdf61b..fe2b52d860 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -32,6 +32,8 @@ #include <fsl_esdhc.h> #include <asm/cache.h> #include <asm/io.h> +#include <asm/mmu.h> +#include <asm/fsl_law.h> DECLARE_GLOBAL_DATA_PTR; @@ -93,18 +95,26 @@ int checkcpu (void) minor = PVR_MIN(pvr); printf("Core: "); - switch (fam) { - case PVR_FAM(PVR_85xx): - puts("E500"); - break; - default: - puts("Unknown"); - break; + if (PVR_FAM(PVR_85xx)) { + switch(PVR_MEM(pvr)) { + case 0x1: + case 0x2: + puts("E500"); + break; + case 0x3: + puts("E500MC"); + break; + case 0x4: + puts("E5500"); + break; + default: + puts("Unknown"); + break; + } + } else { + puts("Unknown"); } - if (PVR_MEM(pvr) == 0x03) - puts("MC"); - printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); @@ -250,71 +260,6 @@ reset_85xx_watchdog(void) #endif /* CONFIG_WATCHDOG */ /* - * Configures a UPM. The function requires the respective MxMR to be set - * before calling this function. "size" is the number or entries, not a sizeof. - */ -void upmconfig (uint upm, uint * table, uint size) -{ - int i, mdr, mad, old_mad = 0; - volatile u32 *mxmr; - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); - volatile u32 *brp,*orp; - volatile u8* dummy = NULL; - int upmmask; - - switch (upm) { - case UPMA: - mxmr = &lbc->mamr; - upmmask = BR_MS_UPMA; - break; - case UPMB: - mxmr = &lbc->mbmr; - upmmask = BR_MS_UPMB; - break; - case UPMC: - mxmr = &lbc->mcmr; - upmmask = BR_MS_UPMC; - break; - default: - printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); - hang(); - } - - /* Find the address for the dummy write transaction */ - for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; - i++, brp += 2, orp += 2) { - - /* Look for a valid BR with selected UPM */ - if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) { - dummy = (volatile u8*)(in_be32(brp) & BR_BA); - break; - } - } - - if (i == 8) { - printf("Error: %s() could not find matching BR\n", __FUNCTION__); - hang(); - } - - for (i = 0; i < size; i++) { - /* 1 */ - out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i); - /* 2 */ - out_be32(&lbc->mdr, table[i]); - /* 3 */ - mdr = in_be32(&lbc->mdr); - /* 4 */ - *(volatile u8 *)dummy = 0; - /* 5 */ - do { - mad = in_be32(mxmr) & MxMR_MAD_MSK; - } while (mad <= old_mad && !(!mad && i == (size-1))); - old_mad = mad; - } - out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM); -} - -/* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() */ @@ -326,3 +271,14 @@ int cpu_mmc_init(bd_t *bis) return 0; #endif } + +/* + * Print out the state of various machine registers. + * Currently prints out LAWs, BR0/OR0, and TLBs + */ +void mpc85xx_reginfo(void) +{ + print_tlbcam(); + print_laws(); + print_lbc_regs(); +} diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 99431dc1a7..d491e2ad5a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -154,7 +154,6 @@ static void corenet_tb_init(void) void cpu_init_f (void) { - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); extern void m8560_cpm_reset (void); #ifdef CONFIG_MPC8548 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); @@ -177,60 +176,7 @@ void cpu_init_f (void) config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); #endif - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary - * addresses - these have to be modified later when FLASH size - * has been determined - */ -#if defined(CONFIG_SYS_OR0_REMAP) - out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP); -#endif -#if defined(CONFIG_SYS_OR1_REMAP) - out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP); -#endif - - /* now restrict to preliminary range */ - /* if cs1 is already set via debugger, leave cs0/cs1 alone */ - if (! memctl->br1 & 1) { -#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) - out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM); - out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) - out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM); - out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM); -#endif - } - -#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) - out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM); - out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) - out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM); - out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) - out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM); - out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) - out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM); - out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) - out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM); - out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM); -#endif - -#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) - out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM); - out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM); -#endif + init_early_memctl_regs(); #if defined(CONFIG_CPM2) m8560_cpm_reset(); @@ -263,7 +209,7 @@ void cpu_init_f (void) int cpu_init_r(void) { #ifdef CONFIG_SYS_LBC_LCRR - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; #endif puts ("L2: "); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c index 184cca4c54..8fb27abc55 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c @@ -25,7 +25,7 @@ void cpu_init_f(void) { - ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + fsl_lbc_t *lbc = LBC_BASE_ADDR; /* * LCRR - Clock Ratio Register - set up local bus timing @@ -34,8 +34,8 @@ void cpu_init_f(void) out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); #if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM) - out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM); - out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM); + set_lbc_br(0, CONFIG_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_NAND_OR_PRELIM); #else #error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 1d11ab470f..2628cc5f95 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -404,8 +404,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_MP ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); -#endif ft_fixup_num_cores(blob); +#endif ft_fixup_cache(blob); diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index ddbc2211c3..e05257cf04 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -77,6 +77,13 @@ int cpu_disable(int nr) return 0; } + +int is_core_disabled(int nr) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 coredisrl = in_be32(&gur->coredisrl); + + return (coredisrl & (1 << nr)); +} #else int cpu_disable(int nr) { @@ -96,6 +103,22 @@ int cpu_disable(int nr) return 0; } + +int is_core_disabled(int nr) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr = in_be32(&gur->devdisr); + + switch (nr) { + case 0: + return (devdisr & MPC85xx_DEVDISR_CPU0); + case 1: + return (devdisr & MPC85xx_DEVDISR_CPU1); + default: + printf("Invalid cpu number for disable %d\n", nr); + } + + return 0; +} #endif static u8 boot_entry_map[4] = { diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c new file mode 100644 index 0000000000..6b0fbf200c --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c @@ -0,0 +1,98 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Author: Timur Tabi <timur@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 2 + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {NONE, NONE, NONE, NONE}, + [0x01] = {NONE, NONE, NONE, NONE}, + [0x02] = {NONE, NONE, NONE, NONE}, + [0x03] = {NONE, NONE, NONE, NONE}, + [0x04] = {NONE, NONE, NONE, NONE}, + [0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, + [0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, + [0x09] = {PCIE1, NONE, NONE, NONE}, + [0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, + [0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, + [0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x15] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x16] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x17] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x18] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x19] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2}, +}; + +static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x00] = {PCIE3, PCIE3}, + [0x01] = {PCIE2, PCIE3}, + [0x02] = {SATA1, SATA2}, + [0x03] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x04] = {NONE, NONE}, + [0x06] = {SATA1, SATA2}, + [0x07] = {NONE, NONE}, + [0x09] = {PCIE3, PCIE2}, + [0x0a] = {SATA1, SATA2}, + [0x0b] = {NONE, NONE}, + [0x0d] = {PCIE3, PCIE2}, + [0x0e] = {SATA1, SATA2}, + [0x0f] = {NONE, NONE}, + [0x15] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x16] = {SATA1, SATA2}, + [0x17] = {NONE, NONE}, + [0x18] = {PCIE3, PCIE3}, + [0x19] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x1a] = {SATA1, SATA2}, + [0x1b] = {NONE, NONE}, + [0x1c] = {PCIE3, PCIE3}, + [0x1d] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x1e] = {SATA1, SATA2}, + [0x1f] = {NONE, NONE}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + unsigned int i; + + debug("%s: dev = %d\n", __FUNCTION__, device); + debug("PORDEVSR[IO_SEL] = 0x%x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds_cfg); + return 0; + } + + for (i = 0; i < SRDS1_MAX_LANES; i++) { + if (serdes1_cfg_tbl[srds_cfg][i] == device) + return 1; + if (serdes2_cfg_tbl[srds_cfg][i] == device) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 8132115fca..dd4c6b3e98 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -172,10 +172,7 @@ void get_sys_info (sys_info_t * sysInfo) /* We will program LCRR to this value later */ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; #else - { - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); - lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV; - } + lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; #endif if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { #if defined(CONFIG_FSL_CORENET) diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index b3037aceaf..f2833a5df7 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -55,7 +55,45 @@ void init_tlbs(void) return ; } +void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn, + phys_addr_t *rpn) +{ + u32 _mas1; + + mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0)); + asm volatile("tlbre;isync"); + _mas1 = mfspr(MAS1); + + *valid = (_mas1 & MAS1_VALID); + *tsize = (_mas1 >> 8) & 0xf; + *epn = mfspr(MAS2) & MAS2_EPN; + *rpn = mfspr(MAS3) & MAS3_RPN; +#ifdef CONFIG_ENABLE_36BIT_PHYS + *rpn |= ((u64)mfspr(MAS7)) << 32; +#endif +} + #ifndef CONFIG_NAND_SPL +void print_tlbcam(void) +{ + int i; + unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; + + /* walk all the entries */ + printf("TLBCAM entries\n"); + for (i = 0; i < num_cam; i++) { + unsigned long epn; + u32 tsize, valid; + phys_addr_t rpn; + + read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn); + printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:", + i, (valid == 0) ? 0 : 1, (unsigned int)epn, + (unsigned long long)rpn); + print_size(TSIZE_TO_BYTES(tsize), "\n"); + } +} + static inline void use_tlb_cam(u8 idx) { int i = idx / 32; @@ -82,15 +120,9 @@ void init_used_tlb_cams(void) /* walk all the entries */ for (i = 0; i < num_cam; i++) { - u32 _mas1; - mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); - asm volatile("tlbre;isync"); - _mas1 = mfspr(MAS1); - - /* if the entry isn't valid skip it */ - if ((_mas1 & MAS1_VALID)) + if (mfspr(MAS1) & MAS1_VALID) use_tlb_cam(i); } } @@ -134,7 +166,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, #ifdef CONFIG_ADDR_MAP if ((tlb == 1) && (gd->flags & GD_FLG_RELOC)) - addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel); + addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel); #endif } @@ -201,26 +233,12 @@ void init_addr_map(void) /* walk all the entries */ for (i = 0; i < num_cam; i++) { unsigned long epn; - u32 tsize, _mas1; + u32 tsize, valid; phys_addr_t rpn; - mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); - - asm volatile("tlbre;isync"); - _mas1 = mfspr(MAS1); - - /* if the entry isn't valid skip it */ - if (!(_mas1 & MAS1_VALID)) - continue; - - tsize = (_mas1 >> 8) & 0xf; - epn = mfspr(MAS2) & MAS2_EPN; - rpn = mfspr(MAS3) & MAS3_RPN; -#ifdef CONFIG_ENABLE_36BIT_PHYS - rpn |= ((phys_addr_t)mfspr(MAS7)) << 32; -#endif - - addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i); + read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn); + if (valid & MAS1_VALID) + addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i); } return ; |