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-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu.c19
-rw-r--r--arch/powerpc/cpu/mpc83xx/ecc.c36
-rw-r--r--arch/powerpc/cpu/mpc83xx/spd_sdram.c36
-rw-r--r--arch/powerpc/cpu/mpc8xxx/fsl_pamu.c12
4 files changed, 60 insertions, 43 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 9c67099a17..3048ecf34a 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -133,18 +133,18 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
#ifdef MPC83xx_RESET
/* Interrupts and MMU off */
- __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
-
- msr &= ~( MSR_EE | MSR_IR | MSR_DR);
- __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+ msr = mfmsr();
+ msr &= ~(MSR_EE | MSR_IR | MSR_DR);
+ mtmsr(msr);
/* enable Reset Control Reg */
immap->reset.rpr = 0x52535445;
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
+ sync();
+ isync();
/* confirm Reset Control Reg is enabled */
- while(!((immap->reset.rcer) & RCER_CRE));
+ while(!((immap->reset.rcer) & RCER_CRE))
+ ;
udelay(200);
@@ -156,10 +156,9 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
/* Interrupts and MMU off */
- __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
-
+ msr = mfmsr();
msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
- __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+ mtmsr(msr);
/*
* Trying to execute the next instruction at a non-existing address
diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c
index 73f0be2a30..10e9b96add 100644
--- a/arch/powerpc/cpu/mpc83xx/ecc.c
+++ b/arch/powerpc/cpu/mpc83xx/ecc.c
@@ -191,8 +191,8 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
}
ddr->err_disable = val;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
return 0;
} else if (strcmp(argv[1], "errdetectclr") == 0) {
val = ddr->err_detect;
@@ -249,8 +249,8 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
printf("Incorrect command\n");
ddr->ecc_err_inject = val;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
return 0;
} else if (strcmp(argv[1], "mirror") == 0) {
val = ddr->ecc_err_inject;
@@ -282,26 +282,26 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
/* enable injects */
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
/* write memory location injecting errors */
ppcDWstore((u32 *) i, pattern);
- __asm__ __volatile__("sync");
+ sync();
/* disable injects */
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
/* read data, this generates ECC error */
ppcDWload((u32 *) i, ret);
- __asm__ __volatile__("sync");
+ sync();
/* re-initialize memory, double word write the location again,
* generates new ECC code this time */
ppcDWstore((u32 *) i, writeback);
- __asm__ __volatile__("sync");
+ sync();
}
enable_interrupts();
return 0;
@@ -321,29 +321,29 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
/* enable injects */
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
/* write memory location injecting errors */
*(u32 *) i = 0xfedcba98UL;
- __asm__ __volatile__("sync");
+ sync();
/* sub double word write,
* bus will read-modify-write,
* generates ECC error */
*((u32 *) i + 1) = 0x76543210UL;
- __asm__ __volatile__("sync");
+ sync();
/* disable injects */
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
- __asm__ __volatile__("sync");
- __asm__ __volatile__("isync");
+ sync();
+ isync();
/* re-initialize memory,
* double word write the location again,
* generates new ECC code this time */
ppcDWstore((u32 *) i, writeback);
- __asm__ __volatile__("sync");
+ sync();
}
enable_interrupts();
return 0;
diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index 5ca307ca58..8b5ecdb9ad 100644
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -436,7 +436,7 @@ long int spd_sdram()
else if (caslat == 4)
ddr->debug_reg = 0x202c0000; /* CL=3.0 */
- __asm__ __volatile__ ("sync");
+ sync();
debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
}
@@ -765,7 +765,8 @@ long int spd_sdram()
#endif
debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
- asm("sync;isync");
+ sync();
+ isync();
udelay(600);
@@ -834,7 +835,8 @@ long int spd_sdram()
#endif
/* Enable controller, and GO! */
ddr->sdram_cfg = sdram_cfg;
- asm("sync;isync");
+ sync();
+ isync();
udelay(500);
debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
@@ -843,6 +845,22 @@ long int spd_sdram()
#endif /* CONFIG_SPD_EEPROM */
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+static inline u32 mftbu(void)
+{
+ u32 rval;
+
+ asm volatile("mftbu %0" : "=r" (rval));
+ return rval;
+}
+
+static inline u32 mftb(void)
+{
+ u32 rval;
+
+ asm volatile("mftb %0" : "=r" (rval));
+ return rval;
+}
+
/*
* Use timebase counter, get_timer() is not available
* at this point of initialization yet.
@@ -858,9 +876,9 @@ static __inline__ unsigned long get_tbms (void)
/* get the timebase ticks */
do {
- asm volatile ("mftbu %0":"=r" (tbu1):);
- asm volatile ("mftb %0":"=r" (tbl):);
- asm volatile ("mftbu %0":"=r" (tbu2):);
+ tbu1 = mftbu();
+ tbl = mftb();
+ tbu2 = mftbu();
} while (tbu1 != tbu2);
/* convert ticks to ms */
@@ -897,7 +915,7 @@ void ddr_enable_ecc(unsigned int dram_size)
for (p = 0; p < (u64*)(size); p++) {
ppcDWstore((u32*)p, pattern);
}
- __asm__ __volatile__ ("sync");
+ sync();
#endif
t_end = get_tbms();
@@ -922,8 +940,8 @@ void ddr_enable_ecc(unsigned int dram_size)
/* Enable errors for ECC */
ddr->err_disable &= ECC_ERROR_ENABLE;
- __asm__ __volatile__ ("sync");
- __asm__ __volatile__ ("isync");
+ sync();
+ isync();
}
#endif /* CONFIG_DDR_ECC */
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
index 23cc5a32ac..d81af70f44 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
@@ -131,10 +131,10 @@ static int pamu_config_ppaace(uint32_t liodn, uint64_t win_addr,
set_bf(ppaace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL);
}
- asm volatile("sync" : : : "memory");
+ sync();
/* Mark the ppace entry valid */
ppaace->addr_bitfields |= PAACE_V_VALID;
- asm volatile("sync" : : : "memory");
+ sync();
return 0;
}
@@ -279,7 +279,7 @@ int pamu_init(void)
out_be32(&regs->splah, spaact_lim >> 32);
out_be32(&regs->splal, (uint32_t)spaact_lim);
}
- asm volatile("sync" : : : "memory");
+ sync();
base_addr += PAMU_OFFSET;
}
@@ -294,7 +294,7 @@ void pamu_enable(void)
for (i = 0; i < CONFIG_NUM_PAMU; i++) {
setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
PAMU_PCR_PE);
- asm volatile("sync" : : : "memory");
+ sync();
base_addr += PAMU_OFFSET;
}
}
@@ -318,7 +318,7 @@ void pamu_reset(void)
out_be32(&regs->splal, 0);
clrbits_be32((void *)regs + PAMU_PCR_OFFSET, PAMU_PCR_PE);
- asm volatile("sync" : : : "memory");
+ sync();
base_addr += PAMU_OFFSET;
}
}
@@ -331,7 +331,7 @@ void pamu_disable(void)
for (i = 0; i < CONFIG_NUM_PAMU; i++) {
clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE);
- asm volatile("sync" : : : "memory");
+ sync();
base_addr += PAMU_OFFSET;
}
}
generated by cgit (git 2.34.1) at 2024-12-25 02:01:07 +0000