diff options
Diffstat (limited to 'arch/powerpc')
35 files changed, 126 insertions, 1011 deletions
diff --git a/arch/powerpc/cpu/Makefile b/arch/powerpc/cpu/Makefile index 88b5298be0..b182aa66f3 100644 --- a/arch/powerpc/cpu/Makefile +++ b/arch/powerpc/cpu/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_MPC83xx) += mpc8xxx/ obj-$(CONFIG_MPC85xx) += mpc8xxx/ obj-$(CONFIG_MPC86xx) += mpc8xxx/ diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds index 9658b21951..b32f74e002 100644 --- a/arch/powerpc/cpu/mpc512x/u-boot.lds +++ b/arch/powerpc/cpu/mpc512x/u-boot.lds @@ -24,7 +24,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) *(.fixup) diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds index 719846526f..6a5357124d 100644 --- a/arch/powerpc/cpu/mpc5xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xx/u-boot.lds @@ -33,7 +33,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds index cd9e23fbb7..aa80d3dbb1 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds @@ -28,7 +28,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds index 50cbf85d23..469fc293eb 100644 --- a/arch/powerpc/cpu/mpc8260/u-boot.lds +++ b/arch/powerpc/cpu/mpc8260/u-boot.lds @@ -27,7 +27,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc83xx/law.c b/arch/powerpc/cpu/mpc83xx/law.c index 66c88b697e..262ae7f711 100644 --- a/arch/powerpc/cpu/mpc83xx/law.c +++ b/arch/powerpc/cpu/mpc83xx/law.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/fsl_law.h> #include <asm/mmu.h> +#include <linux/log2.h> int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) { @@ -20,7 +21,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) if (start == 0) start_align = 1ull << (LAW_SIZE_2G + 1); else - start_align = 1ull << (ffs64(start) - 1); + start_align = 1ull << (__ffs64(start) - 1); law_sz = min(start_align, sz); law_sz_enc = __ilog2_u64(law_sz) - 1; @@ -40,7 +41,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) if (sz) { start += law_sz; - start_align = 1ull << (ffs64(start) - 1); + start_align = 1ull << (__ffs64(start) - 1); law_sz = min(start_align, sz); law_sz_enc = __ilog2_u64(law_sz) - 1; ecm = &immap->sysconf.ddrlaw[1]; diff --git a/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds index 774772beaf..4101eaf3f3 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds @@ -24,7 +24,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); } __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds index 3c177fa291..dbd8bbe23c 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds @@ -26,7 +26,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index ae0823af65..0b89157fca 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -149,6 +149,9 @@ config TARGET_XPEDITE550X config TARGET_UCP1020 bool "Support uCP1020" +config TARGET_CYRUS + bool "Support Varisys Cyrus" + endchoice source "board/freescale/b4860qds/Kconfig" @@ -185,6 +188,7 @@ source "board/gdsys/p1022/Kconfig" source "board/keymile/kmp204x/Kconfig" source "board/sbc8548/Kconfig" source "board/socrates/Kconfig" +source "board/varisys/cyrus/Kconfig" source "board/xes/xpedite520x/Kconfig" source "board/xes/xpedite537x/Kconfig" source "board/xes/xpedite550x/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index d4c3d9df9b..7270be1b28 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -13,6 +13,7 @@ #include <asm/processor.h> #include <linux/ctype.h> #include <asm/io.h> +#include <asm/fsl_fdt.h> #include <asm/fsl_portals.h> #include <hwconfig.h> #ifdef CONFIG_FSL_ESDHC @@ -943,3 +944,13 @@ int ft_verify_fdt(void *fdt) return 1; } + +void fdt_del_diu(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,diu")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index d954fe2fd2..e732969e41 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -131,7 +131,8 @@ void get_sys_info(sys_info_t *sys_info) * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) + defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \ + defined(CONFIG_PPC_T2081) svr = get_svr(); switch (SVR_SOC_VER(svr)) { case SVR_T4240: diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 8e0508f362..cf31eb2ef3 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -14,6 +14,8 @@ #include <addr_map.h> #endif +#include <linux/log2.h> + DECLARE_GLOBAL_DATA_PTR; void invalidate_tlb(u8 tlb) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index f933b21944..0399f93e6e 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -44,7 +44,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds index b83c55388c..f04456442c 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -22,7 +22,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 5ae7b3eedb..889a4c2400 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -29,7 +29,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 2cf0b25952..f15eaf3805 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -50,7 +50,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds index 58467c2cc8..6c48f40992 100644 --- a/arch/powerpc/cpu/mpc86xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds @@ -32,7 +32,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c index 659e6889bf..15cee3fd4a 100644 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ b/arch/powerpc/cpu/mpc8xx/video.c @@ -1089,7 +1089,6 @@ int drv_video_init (void) memset (&videodev, 0, sizeof (videodev)); strcpy (videodev.name, "video"); - videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */ videodev.putc = video_putc; /* 'putc' function */ videodev.puts = video_puts; /* 'puts' function */ diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index e95539e0a3..ac45e0e3df 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -1,9 +1,7 @@ # # Copyright 2009-2010 Freescale Semiconductor, Inc. # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# Version 2 as published by the Free Software Foundation. +# SPDX-License-Identifier: GPL-2.0 # MINIMAL= diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index 33d53a8cfe..24baad442e 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -11,6 +11,7 @@ #include <linux/compiler.h> #include <asm/fsl_law.h> #include <asm/io.h> +#include <linux/log2.h> DECLARE_GLOBAL_DATA_PTR; @@ -187,7 +188,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) if (start == 0) start_align = 1ull << (LAW_SIZE_32G + 1); else - start_align = 1ull << (ffs64(start) - 1); + start_align = 1ull << (__ffs64(start) - 1); law_sz = min(start_align, sz); law_sz_enc = __ilog2_u64(law_sz) - 1; @@ -202,7 +203,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) if (sz) { start += law_sz; - start_align = 1ull << (ffs64(start) - 1); + start_align = 1ull << (__ffs64(start) - 1); law_sz = min(start_align, sz); law_sz_enc = __ilog2_u64(law_sz) - 1; diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds index 198050853a..55dd4e1300 100644 --- a/arch/powerpc/cpu/ppc4xx/u-boot.lds +++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds @@ -46,7 +46,6 @@ SECTIONS _GOT2_TABLE_ = .; KEEP(*(.got2)) KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); _FIXUP_TABLE_ = .; KEEP(*(.fixup)) } diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index ad104b9315..5d9f5c2822 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + dtb-$(CONFIG_TARGET_CANYONLANDS) += arches.dtb canyonlands.dtb glacier.dtb targets += $(dtb-y) diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h index 43a2bb2b3e..87efcca68a 100644 --- a/arch/powerpc/include/asm/atomic.h +++ b/arch/powerpc/include/asm/atomic.h @@ -19,7 +19,7 @@ typedef struct { int counter; } atomic_t; extern void atomic_clear_mask(unsigned long mask, unsigned long *addr); extern void atomic_set_mask(unsigned long mask, unsigned long *addr); -extern __inline__ int atomic_add_return(int a, atomic_t *v) +static __inline__ int atomic_add_return(int a, atomic_t *v) { int t; @@ -35,7 +35,7 @@ extern __inline__ int atomic_add_return(int a, atomic_t *v) return t; } -extern __inline__ int atomic_sub_return(int a, atomic_t *v) +static __inline__ int atomic_sub_return(int a, atomic_t *v) { int t; @@ -51,7 +51,7 @@ extern __inline__ int atomic_sub_return(int a, atomic_t *v) return t; } -extern __inline__ int atomic_inc_return(atomic_t *v) +static __inline__ int atomic_inc_return(atomic_t *v) { int t; @@ -67,7 +67,7 @@ extern __inline__ int atomic_inc_return(atomic_t *v) return t; } -extern __inline__ int atomic_dec_return(atomic_t *v) +static __inline__ int atomic_dec_return(atomic_t *v) { int t; diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index a6bcf3c3fe..96491b6e4e 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -6,13 +6,7 @@ #define _PPC_BITOPS_H #include <asm/byteorder.h> - -extern void set_bit(int nr, volatile void *addr); -extern void clear_bit(int nr, volatile void *addr); -extern void change_bit(int nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void *addr); -extern int test_and_clear_bit(int nr, volatile void *addr); -extern int test_and_change_bit(int nr, volatile void *addr); +#include <asm-generic/bitops/__ffs.h> /* * Arguably these bit operations don't imply any memory barrier or @@ -34,7 +28,7 @@ extern int test_and_change_bit(int nr, volatile void *addr); * These used to be if'd out here because using : "cc" as a constraint * resulted in errors from egcs. Things may be OK with gcc-2.95. */ -extern __inline__ void set_bit(int nr, volatile void * addr) +static __inline__ void set_bit(int nr, volatile void * addr) { unsigned long old; unsigned long mask = 1 << (nr & 0x1f); @@ -51,7 +45,7 @@ extern __inline__ void set_bit(int nr, volatile void * addr) : "cc" ); } -extern __inline__ void clear_bit(int nr, volatile void *addr) +static __inline__ void clear_bit(int nr, volatile void *addr) { unsigned long old; unsigned long mask = 1 << (nr & 0x1f); @@ -68,7 +62,7 @@ extern __inline__ void clear_bit(int nr, volatile void *addr) : "cc"); } -extern __inline__ void change_bit(int nr, volatile void *addr) +static __inline__ void change_bit(int nr, volatile void *addr) { unsigned long old; unsigned long mask = 1 << (nr & 0x1f); @@ -85,7 +79,7 @@ extern __inline__ void change_bit(int nr, volatile void *addr) : "cc"); } -extern __inline__ int test_and_set_bit(int nr, volatile void *addr) +static __inline__ int test_and_set_bit(int nr, volatile void *addr) { unsigned int old, t; unsigned int mask = 1 << (nr & 0x1f); @@ -104,7 +98,7 @@ extern __inline__ int test_and_set_bit(int nr, volatile void *addr) return (old & mask) != 0; } -extern __inline__ int test_and_clear_bit(int nr, volatile void *addr) +static __inline__ int test_and_clear_bit(int nr, volatile void *addr) { unsigned int old, t; unsigned int mask = 1 << (nr & 0x1f); @@ -123,7 +117,7 @@ extern __inline__ int test_and_clear_bit(int nr, volatile void *addr) return (old & mask) != 0; } -extern __inline__ int test_and_change_bit(int nr, volatile void *addr) +static __inline__ int test_and_change_bit(int nr, volatile void *addr) { unsigned int old, t; unsigned int mask = 1 << (nr & 0x1f); @@ -143,7 +137,7 @@ extern __inline__ int test_and_change_bit(int nr, volatile void *addr) } #endif /* __INLINE_BITOPS */ -extern __inline__ int test_bit(int nr, __const__ volatile void *addr) +static __inline__ int test_bit(int nr, __const__ volatile void *addr) { __const__ unsigned int *p = (__const__ unsigned int *) addr; @@ -152,7 +146,7 @@ extern __inline__ int test_bit(int nr, __const__ volatile void *addr) /* Return the bit position of the most significant 1 bit in a word */ /* - the result is undefined when x == 0 */ -extern __inline__ int __ilog2(unsigned int x) +static __inline__ int __ilog2(unsigned int x) { int lz; @@ -160,7 +154,7 @@ extern __inline__ int __ilog2(unsigned int x) return 31 - lz; } -extern __inline__ int ffz(unsigned int x) +static __inline__ int ffz(unsigned int x) { if ((x = ~x) == 0) return 32; @@ -209,16 +203,6 @@ static inline int fls64(__u64 x) #error BITS_PER_LONG not 32 or 64 #endif -static inline int __ilog2_u64(u64 n) -{ - return fls64(n) - 1; -} - -static inline int ffs64(u64 x) -{ - return __ilog2_u64(x & -x) + 1ull; -} - #ifdef __KERNEL__ /* @@ -226,7 +210,7 @@ static inline int ffs64(u64 x) * the libc and compiler builtin ffs routines, therefore * differs in spirit from the above ffz (man ffs). */ -extern __inline__ int ffs(int x) +static __inline__ int ffs(int x) { return __ilog2(x & -x) + 1; } @@ -250,7 +234,7 @@ extern __inline__ int ffs(int x) #define find_first_zero_bit(addr, size) \ find_next_zero_bit((addr), (size), 0) -extern __inline__ unsigned long find_next_zero_bit(void * addr, +static __inline__ unsigned long find_next_zero_bit(void * addr, unsigned long size, unsigned long offset) { unsigned int * p = ((unsigned int *) addr) + (offset >> 5); @@ -298,7 +282,7 @@ found_middle: #define ext2_clear_bit(nr, addr) test_and_clear_bit((nr) ^ 0x18, addr) #else -extern __inline__ int ext2_set_bit(int nr, void * addr) +static __inline__ int ext2_set_bit(int nr, void * addr) { int mask; unsigned char *ADDR = (unsigned char *) addr; @@ -311,7 +295,7 @@ extern __inline__ int ext2_set_bit(int nr, void * addr) return oldbit; } -extern __inline__ int ext2_clear_bit(int nr, void * addr) +static __inline__ int ext2_clear_bit(int nr, void * addr) { int mask; unsigned char *ADDR = (unsigned char *) addr; @@ -325,7 +309,7 @@ extern __inline__ int ext2_clear_bit(int nr, void * addr) } #endif /* __KERNEL__ */ -extern __inline__ int ext2_test_bit(int nr, __const__ void * addr) +static __inline__ int ext2_test_bit(int nr, __const__ void * addr) { __const__ unsigned char *ADDR = (__const__ unsigned char *) addr; diff --git a/arch/powerpc/include/asm/byteorder.h b/arch/powerpc/include/asm/byteorder.h index 3f5bcf63a1..f731d18e76 100644 --- a/arch/powerpc/include/asm/byteorder.h +++ b/arch/powerpc/include/asm/byteorder.h @@ -5,7 +5,7 @@ #ifdef __GNUC__ -extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) +static __inline__ unsigned ld_le16(const volatile unsigned short *addr) { unsigned val; @@ -13,12 +13,12 @@ extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) return val; } -extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val) +static __inline__ void st_le16(volatile unsigned short *addr, const unsigned val) { __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); } -extern __inline__ unsigned ld_le32(const volatile unsigned *addr) +static __inline__ unsigned ld_le32(const volatile unsigned *addr) { unsigned val; @@ -26,7 +26,7 @@ extern __inline__ unsigned ld_le32(const volatile unsigned *addr) return val; } -extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) +static __inline__ void st_le32(volatile unsigned *addr, const unsigned val) { __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); } diff --git a/arch/powerpc/include/asm/fsl_dtsec.h b/arch/powerpc/include/asm/fsl_dtsec.h deleted file mode 100644 index 41b8398ecd..0000000000 --- a/arch/powerpc/include/asm/fsl_dtsec.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __DTSEC_H__ -#define __DTSEC_H__ - -#include <asm/types.h> - -struct dtsec { - u32 tsec_id; /* controller ID and version */ - u32 tsec_id2; /* controller ID and configuration */ - u32 ievent; /* interrupt event */ - u32 imask; /* interrupt mask */ - u32 res0; - u32 ecntrl; /* ethernet control and configuration */ - u32 ptv; /* pause time value */ - u32 tbipa; /* TBI PHY address */ - u32 res1[8]; - u32 tctrl; /* Transmit control register */ - u32 res2[3]; - u32 rctrl; /* Receive control register */ - u32 res3[11]; - u32 igaddr[8]; /* Individual group address */ - u32 gaddr[8]; /* group address */ - u32 res4[16]; - u32 maccfg1; /* MAC configuration register 1 */ - u32 maccfg2; /* MAC configuration register 2 */ - u32 ipgifg; /* inter-packet/inter-frame gap */ - u32 hafdup; /* half-duplex control */ - u32 maxfrm; /* Maximum frame size */ - u32 res5[3]; - u32 miimcfg; /* MII management configuration */ - u32 miimcom; /* MII management command */ - u32 miimadd; /* MII management address */ - u32 miimcon; /* MII management control */ - u32 miimstat; /* MII management status */ - u32 miimind; /* MII management indicator */ - u32 res6; - u32 ifstat; /* Interface status */ - u32 macstnaddr1; /* MAC station address 1 */ - u32 macstnaddr2; /* MAC station address 2 */ - u32 res7[46]; - /* transmit and receive counter */ - u32 tr64; /* Tx and Rx 64 bytes frame */ - u32 tr127; /* Tx and Rx 65 to 127 bytes frame */ - u32 tr255; /* Tx and Rx 128 to 255 bytes frame */ - u32 tr511; /* Tx and Rx 256 to 511 bytes frame */ - u32 tr1k; /* Tx and Rx 512 to 1023 bytes frame */ - u32 trmax; /* Tx and Rx 1024 to 1518 bytes frame */ - u32 trmgv; /* Tx and Rx 1519 to 1522 good VLAN frame */ - /* receive counters */ - u32 rbyt; /* Receive byte counter */ - u32 rpkt; /* Receive packet counter */ - u32 rfcs; /* Receive FCS error */ - u32 rmca; /* Receive multicast packet */ - u32 rbca; /* Receive broadcast packet */ - u32 rxcf; /* Receive control frame */ - u32 rxpf; /* Receive pause frame */ - u32 rxuo; /* Receive unknown OP code */ - u32 raln; /* Receive alignment error */ - u32 rflr; /* Receive frame length error */ - u32 rcde; /* Receive code error */ - u32 rcse; /* Receive carrier sense error */ - u32 rund; /* Receive undersize packet */ - u32 rovr; /* Receive oversize packet */ - u32 rfrg; /* Receive fragments counter */ - u32 rjbr; /* Receive jabber counter */ - u32 rdrp; /* Receive drop counter */ - /* transmit counters */ - u32 tbyt; /* Transmit byte counter */ - u32 tpkt; /* Transmit packet */ - u32 tmca; /* Transmit multicast packet */ - u32 tbca; /* Transmit broadcast packet */ - u32 txpf; /* Transmit pause control frame */ - u32 tdfr; /* Transmit deferral packet */ - u32 tedf; /* Transmit excessive deferral pkt */ - u32 tscl; /* Transmit single collision pkt */ - u32 tmcl; /* Transmit multiple collision pkt */ - u32 tlcl; /* Transmit late collision pkt */ - u32 txcl; /* Transmit excessive collision */ - u32 tncl; /* Transmit total collision */ - u32 res8; - u32 tdrp; /* Transmit drop frame */ - u32 tjbr; /* Transmit jabber frame */ - u32 tfcs; /* Transmit FCS error */ - u32 txcf; /* Transmit control frame */ - u32 tovr; /* Transmit oversize frame */ - u32 tund; /* Transmit undersize frame */ - u32 tfrg; /* Transmit fragments frame */ - /* counter controls */ - u32 car1; /* carry register 1 */ - u32 car2; /* carry register 2 */ - u32 cam1; /* carry register 1 mask */ - u32 cam2; /* carry register 2 mask */ - u32 res9[80]; -}; - - -/* TBI register addresses */ -#define TBI_CR 0x00 -#define TBI_SR 0x01 -#define TBI_ANA 0x04 -#define TBI_ANLPBPA 0x05 -#define TBI_ANEX 0x06 -#define TBI_TBICON 0x11 - -/* TBI MDIO register bit fields*/ -#define TBICON_CLK_SELECT 0x0020 -#define TBIANA_ASYMMETRIC_PAUSE 0x0100 -#define TBIANA_SYMMETRIC_PAUSE 0x0080 -#define TBIANA_HALF_DUPLEX 0x0040 -#define TBIANA_FULL_DUPLEX 0x0020 -#define TBICR_PHY_RESET 0x8000 -#define TBICR_ANEG_ENABLE 0x1000 -#define TBICR_RESTART_ANEG 0x0200 -#define TBICR_FULL_DUPLEX 0x0100 -#define TBICR_SPEED1_SET 0x0040 - -/* IEVENT - interrupt events register */ -#define IEVENT_BABR 0x80000000 /* Babbling receive error */ -#define IEVENT_RXC 0x40000000 /* pause control frame received */ -#define IEVENT_MSRO 0x04000000 /* MIB counter overflow */ -#define IEVENT_GTSC 0x02000000 /* Graceful transmit stop complete */ -#define IEVENT_BABT 0x01000000 /* Babbling transmit error */ -#define IEVENT_TXC 0x00800000 /* control frame transmitted */ -#define IEVENT_TXE 0x00400000 /* Transmit channel error */ -#define IEVENT_LC 0x00040000 /* Late collision occurred */ -#define IEVENT_CRL 0x00020000 /* Collision retry exceed limit */ -#define IEVENT_XFUN 0x00010000 /* Transmit FIFO underrun */ -#define IEVENT_ABRT 0x00008000 /* Transmit packet abort */ -#define IEVENT_MMRD 0x00000400 /* MII management read complete */ -#define IEVENT_MMWR 0x00000200 /* MII management write complete */ -#define IEVENT_GRSC 0x00000100 /* Graceful stop complete */ -#define IEVENT_TDPE 0x00000002 /* Internal data parity error on Tx */ -#define IEVENT_RDPE 0x00000001 /* Internal data parity error on Rx */ - -#define IEVENT_CLEAR_ALL 0xffffffff - -/* IMASK - interrupt mask register */ -#define IMASK_BREN 0x80000000 /* Babbling receive enable */ -#define IMASK_RXCEN 0x40000000 /* receive control enable */ -#define IMASK_MSROEN 0x04000000 /* MIB counter overflow enable */ -#define IMASK_GTSCEN 0x02000000 /* Graceful Tx stop complete enable */ -#define IMASK_BTEN 0x01000000 /* Babbling transmit error enable */ -#define IMASK_TXCEN 0x00800000 /* control frame transmitted enable */ -#define IMASK_TXEEN 0x00400000 /* Transmit channel error enable */ -#define IMASK_LCEN 0x00040000 /* Late collision interrupt enable */ -#define IMASK_CRLEN 0x00020000 /* Collision retry exceed limit */ -#define IMASK_XFUNEN 0x00010000 /* Transmit FIFO underrun enable */ -#define IMASK_ABRTEN 0x00008000 /* Transmit packet abort enable */ -#define IMASK_MMRDEN 0x00000400 /* MII management read complete enable */ -#define IMASK_MMWREN 0x00000200 /* MII management write complete enable */ -#define IMASK_GRSCEN 0x00000100 /* Graceful stop complete interrupt enable */ -#define IMASK_TDPEEN 0x00000002 /* Internal data parity error on Tx enable */ -#define IMASK_RDPEEN 0x00000001 /* Internal data parity error on Rx enable */ - -#define IMASK_MASK_ALL 0x00000000 - -/* ECNTRL - ethernet control register */ -#define ECNTRL_CFG_RO 0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */ -#define ECNTRL_CLRCNT 0x00004000 /* clear all statistics */ -#define ECNTRL_AUTOZ 0x00002000 /* auto zero MIB counter */ -#define ECNTRL_STEN 0x00001000 /* enable internal counters to update */ -#define ECNTRL_GMIIM 0x00000040 /* 1- GMII or RGMII interface mode */ -#define ECNTRL_TBIM 0x00000020 /* 1- Ten-bit interface mode */ -#define ECNTRL_RPM 0x00000010 /* 1- RGMII reduced-pin mode */ -#define ECNTRL_R100M 0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps - 0- RGMII 10 Mbps, SGMII 10 Mbps */ -#define ECNTRL_SGMIIM 0x00000002 /* 1- SGMII interface mode */ -#define ECNTRL_TBIM 0x00000020 /* 1- TBI Interface mode (for SGMII) */ - -#define ECNTRL_DEFAULT (ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM) - -/* TCTRL - Transmit control register */ -#define TCTRL_THDF 0x00000800 /* Transmit half-duplex flow control */ -#define TCTRL_TTSE 0x00000040 /* Transmit time-stamp enable */ -#define TCTRL_GTS 0x00000020 /* Graceful transmit stop */ -#define TCTRL_RFC_PAUSE 0x00000010 /* Receive flow control pause frame */ - -/* RCTRL - Receive control register */ -#define RCTRL_PAL_MASK 0x001f0000 /* packet alignment padding length */ -#define RCTRL_PAL_SHIFT 16 -#define RCTRL_CFA 0x00008000 /* control frame accept enable */ -#define RCTRL_GHTX 0x00000800 /* group address hash table extend */ -#define RCTRL_RTSE 0x00000040 /* receive 1588 time-stamp enable */ -#define RCTRL_GRS 0x00000020 /* graceful receive stop */ -#define RCTRL_BC_REJ 0x00000010 /* broadcast frame reject */ -#define RCTRL_BC_MPROM 0x00000008 /* all multicast/broadcast frames received */ -#define RCTRL_RSF 0x00000004 /* receive short frame(17~63 bytes) enable */ -#define RCTRL_EMEN 0x00000002 /* Exact match MAC address enable */ -#define RCTRL_UPROM 0x00000001 /* all unicast frame received */ - -/* MACCFG1 - MAC configuration 1 register */ -#define MACCFG1_SOFT_RST 0x80000000 /* place the MAC in reset */ -#define MACCFG1_RST_RXMAC 0x00080000 /* reset receive MAC control block */ -#define MACCFG1_RST_TXMAC 0x00040000 /* reet transmit MAC control block */ -#define MACCFG1_RST_RXFUN 0x00020000 /* reset receive function block */ -#define MACCFG1_RST_TXFUN 0x00010000 /* reset transmit function block */ -#define MACCFG1_LOOPBACK 0x00000100 /* MAC loopback */ -#define MACCFG1_RX_FLOW 0x00000020 /* Receive flow */ -#define MACCFG1_TX_FLOW 0x00000010 /* Transmit flow */ -#define MACCFG1_SYNC_RXEN 0x00000008 /* Frame reception enabled */ -#define MACCFG1_RX_EN 0x00000004 /* Rx enable */ -#define MACCFG1_SYNC_TXEN 0x00000002 /* Frame transmission is enabled */ -#define MACCFG1_TX_EN 0x00000001 /* Tx enable */ -#define MACCFG1_RXTX_EN (MACCFG1_RX_EN | MACCFG1_TX_EN) - -/* MACCFG2 - MAC configuration 2 register */ -#define MACCFG2_PRE_LEN_MASK 0x0000f000 /* preamble length */ -#define MACCFG2_PRE_LEN(x) ((x << 12) & MACCFG2_PRE_LEN_MASK) -#define MACCFG2_IF_MODE_MASK 0x00000300 -#define MACCFG2_IF_MODE_NIBBLE 0x00000100 /* MII, 10/100 Mbps MII/RMII */ -#define MACCFG2_IF_MODE_BYTE 0x00000200 /* GMII/TBI, 1000 GMII/TBI */ -#define MACCFG2_PRE_RX_EN 0x00000080 /* receive preamble enable */ -#define MACCFG2_PRE_TX_EN 0x00000040 /* tx preable enable */ -#define MACCFG2_HUGE_FRAME 0x00000020 /* >= max frame len enable */ -#define MACCFG2_LEN_CHECK 0x00000010 /* MAC check frame's length Rx */ -#define MACCFG2_MAG_EN 0x00000008 /* magic packet enable */ -#define MACCFG2_PAD_CRC 0x00000004 /* pad and append CRC */ -#define MACCFG2_CRC_EN 0x00000002 /* MAC appends a CRC on all frames */ -#define MACCFG2_FULL_DUPLEX 0x00000001 /* Full deplex mode */ - -struct fsl_enet_mac; - -void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs, - int max_rx_len); - -#endif diff --git a/arch/powerpc/include/asm/fsl_fdt.h b/arch/powerpc/include/asm/fsl_fdt.h new file mode 100644 index 0000000000..82e8f45644 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_fdt.h @@ -0,0 +1,11 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _FSL_FDT_H_ +#define _FSL_FDT_H_ + +void fdt_del_diu(void *blob); + +#endif diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h deleted file mode 100644 index 4d04415ba8..0000000000 --- a/arch/powerpc/include/asm/fsl_fman.h +++ /dev/null @@ -1,463 +0,0 @@ -/* - * MPC85xx Internal Memory Map - * - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FSL_FMAN_H__ -#define __FSL_FMAN_H__ - -#include <asm/types.h> - -typedef struct fm_bmi_common { - u32 fmbm_init; /* BMI initialization */ - u32 fmbm_cfg1; /* BMI configuration1 */ - u32 fmbm_cfg2; /* BMI configuration2 */ - u32 res0[0x5]; - u32 fmbm_ievr; /* interrupt event register */ - u32 fmbm_ier; /* interrupt enable register */ - u32 fmbm_ifr; /* interrupt force register */ - u32 res1[0x5]; - u32 fmbm_arb[0x8]; /* BMI arbitration */ - u32 res2[0x28]; - u32 fmbm_gde; /* global debug enable */ - u32 fmbm_pp[0x3f]; /* BMI port parameters */ - u32 res3; - u32 fmbm_pfs[0x3f]; /* BMI port FIFO size */ - u32 res4; - u32 fmbm_ppid[0x3f];/* port partition ID */ -} fm_bmi_common_t; - -typedef struct fm_qmi_common { - u32 fmqm_gc; /* general configuration register */ - u32 res0; - u32 fmqm_eie; /* error interrupt event register */ - u32 fmqm_eien; /* error interrupt enable register */ - u32 fmqm_eif; /* error interrupt force register */ - u32 fmqm_ie; /* interrupt event register */ - u32 fmqm_ien; /* interrupt enable register */ - u32 fmqm_if; /* interrupt force register */ - u32 fmqm_gs; /* global status register */ - u32 fmqm_ts; /* task status register */ - u32 fmqm_etfc; /* enqueue total frame counter */ - u32 fmqm_dtfc; /* dequeue total frame counter */ - u32 fmqm_dc0; /* dequeue counter 0 */ - u32 fmqm_dc1; /* dequeue counter 1 */ - u32 fmqm_dc2; /* dequeue counter 2 */ - u32 fmqm_dc3; /* dequeue counter 3 */ - u32 fmqm_dfnoc; /* dequeue FQID not override counter */ - u32 fmqm_dfcc; /* dequeue FQID from context counter */ - u32 fmqm_dffc; /* dequeue FQID from FD counter */ - u32 fmqm_dcc; /* dequeue confirm counter */ - u32 res1[0xc]; - u32 fmqm_dtrc; /* debug trap configuration register */ - u32 fmqm_efddd; /* enqueue frame descriptor dynamic debug */ - u32 res3[0x2]; - u32 res4[0xdc]; /* missing debug regs */ -} fm_qmi_common_t; - -typedef struct fm_bmi { - u8 res[1024]; -} fm_bmi_t; - -typedef struct fm_qmi { - u8 res[1024]; -} fm_qmi_t; - -struct fm_bmi_rx_port { - u32 fmbm_rcfg; /* Rx configuration */ - u32 fmbm_rst; /* Rx status */ - u32 fmbm_rda; /* Rx DMA attributes */ - u32 fmbm_rfp; /* Rx FIFO parameters */ - u32 fmbm_rfed; /* Rx frame end data */ - u32 fmbm_ricp; /* Rx internal context parameters */ - u32 fmbm_rim; /* Rx internal margins */ - u32 fmbm_rebm; /* Rx external buffer margins */ - u32 fmbm_rfne; /* Rx frame next engine */ - u32 fmbm_rfca; /* Rx frame command attributes */ - u32 fmbm_rfpne; /* Rx frame parser next engine */ - u32 fmbm_rpso; /* Rx parse start offset */ - u32 fmbm_rpp; /* Rx policer profile */ - u32 fmbm_rccb; /* Rx coarse classification base */ - u32 res1[0x2]; - u32 fmbm_rprai[0x8]; /* Rx parse results array Initialization */ - u32 fmbm_rfqid; /* Rx frame queue ID */ - u32 fmbm_refqid; /* Rx error frame queue ID */ - u32 fmbm_rfsdm; /* Rx frame status discard mask */ - u32 fmbm_rfsem; /* Rx frame status error mask */ - u32 fmbm_rfene; /* Rx frame enqueue next engine */ - u32 res2[0x23]; - u32 fmbm_ebmpi[0x8]; /* buffer manager pool information */ - u32 fmbm_acnt[0x8]; /* allocate counter */ - u32 res3[0x8]; - u32 fmbm_cgm[0x8]; /* congestion group map */ - u32 fmbm_mpd; /* BMan pool depletion */ - u32 res4[0x1F]; - u32 fmbm_rstc; /* Rx statistics counters */ - u32 fmbm_rfrc; /* Rx frame counters */ - u32 fmbm_rfbc; /* Rx bad frames counter */ - u32 fmbm_rlfc; /* Rx large frames counter */ - u32 fmbm_rffc; /* Rx filter frames counter */ - u32 fmbm_rfdc; /* Rx frame discard counter */ - u32 fmbm_rfldec; /* Rx frames list DMA error counter */ - u32 fmbm_rodc; /* Rx out of buffers discard counter */ - u32 fmbm_rbdc; /* Rx buffers deallocate counter */ - u32 res5[0x17]; - u32 fmbm_rpc; /* Rx performance counters */ - u32 fmbm_rpcp; /* Rx performance count parameters */ - u32 fmbm_rccn; /* Rx cycle counter */ - u32 fmbm_rtuc; /* Rx tasks utilization counter */ - u32 fmbm_rrquc; /* Rx receive queue utilization counter */ - u32 fmbm_rduc; /* Rx DMA utilization counter */ - u32 fmbm_rfuc; /* Rx FIFO utilization counter */ - u32 fmbm_rpac; /* Rx pause activation counter */ - u32 res6[0x18]; - u32 fmbm_rdbg; /* Rx debug configuration */ -}; - -/* FMBM_RCFG - Rx configuration */ -#define FMBM_RCFG_EN 0x80000000 /* port is enabled to receive data */ -#define FMBM_RCFG_FDOVR 0x02000000 /* frame discard override */ -#define FMBM_RCFG_IM 0x01000000 /* independent mode */ - -/* FMBM_RST - Rx status */ -#define FMBM_RST_BSY 0x80000000 /* Rx port is busy */ - -/* FMBM_RFCA - Rx frame command attributes */ -#define FMBM_RFCA_ORDER 0x80000000 -#define FMBM_RFCA_MR_MASK 0x003f0000 -#define FMBM_RFCA_MR(x) ((x << 16) & FMBM_RFCA_MR_MASK) - -/* FMBM_RSTC - Rx statistics */ -#define FMBM_RSTC_EN 0x80000000 /* statistics counters enable */ - -struct fm_bmi_tx_port { - u32 fmbm_tcfg; /* Tx configuration */ - u32 fmbm_tst; /* Tx status */ - u32 fmbm_tda; /* Tx DMA attributes */ - u32 fmbm_tfp; /* Tx FIFO parameters */ - u32 fmbm_tfed; /* Tx frame end data */ - u32 fmbm_ticp; /* Tx internal context parameters */ - u32 fmbm_tfne; /* Tx frame next engine */ - u32 fmbm_tfca; /* Tx frame command attributes */ - u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */ - u32 fmbm_tfeqid;/* Tx error frame queue ID */ - u32 fmbm_tfene; /* Tx frame enqueue next engine */ - u32 fmbm_trlmts;/* Tx rate limiter scale */ - u32 fmbm_trlmt; /* Tx rate limiter */ - u32 res0[0x73]; - u32 fmbm_tstc; /* Tx statistics counters */ - u32 fmbm_tfrc; /* Tx frame counter */ - u32 fmbm_tfdc; /* Tx frames discard counter */ - u32 fmbm_tfledc;/* Tx frame length error discard counter */ - u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */ - u32 fmbm_tbdc; /* Tx buffers deallocate counter */ - u32 res1[0x1a]; - u32 fmbm_tpc; /* Tx performance counters */ - u32 fmbm_tpcp; /* Tx performance count parameters */ - u32 fmbm_tccn; /* Tx cycle counter */ - u32 fmbm_ttuc; /* Tx tasks utilization counter */ - u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */ - u32 fmbm_tduc; /* Tx DMA utilization counter */ - u32 fmbm_tfuc; /* Tx FIFO utilization counter */ - u32 res2[0x19]; - u32 fmbm_tdcfg; /* Tx debug configuration */ -}; - -/* FMBM_TCFG - Tx configuration */ -#define FMBM_TCFG_EN 0x80000000 /* port is enabled to transmit data */ -#define FMBM_TCFG_IM 0x01000000 /* independent mode enable */ - -/* FMBM_TST - Tx status */ -#define FMBM_TST_BSY 0x80000000 /* Tx port is busy */ - -/* FMBM_TFCA - Tx frame command attributes */ -#define FMBM_TFCA_ORDER 0x80000000 -#define FMBM_TFCA_MR_MASK 0x003f0000 -#define FMBM_TFCA_MR(x) ((x << 16) & FMBM_TFCA_MR_MASK) - -/* FMBM_TSTC - Tx statistics counters */ -#define FMBM_TSTC_EN 0x80000000 - -/* FMBM_INIT - BMI initialization register */ -#define FMBM_INIT_START 0x80000000 /* init internal buffers */ - -/* FMBM_CFG1 - BMI configuration 1 */ -#define FMBM_CFG1_FBPS_MASK 0x03ff0000 /* Free buffer pool size */ -#define FMBM_CFG1_FBPS_SHIFT 16 -#define FMBM_CFG1_FBPO_MASK 0x000003ff /* Free buffer pool offset */ - -/* FMBM_IEVR - interrupt event */ -#define FMBM_IEVR_PEC 0x80000000 /* pipeline table ECC err detected */ -#define FMBM_IEVR_LEC 0x40000000 /* linked list RAM ECC error */ -#define FMBM_IEVR_SEC 0x20000000 /* statistics count RAM ECC error */ -#define FMBM_IEVR_CLEAR_ALL (FMBM_IEVR_PEC | FMBM_IEVR_LEC | FMBM_IEVR_SEC) - -/* FMBM_IER - interrupt enable */ -#define FMBM_IER_PECE 0x80000000 /* PEC interrupt enable */ -#define FMBM_IER_LECE 0x40000000 /* LEC interrupt enable */ -#define FMBM_IER_SECE 0x20000000 /* SEC interrupt enable */ - -#define FMBM_IER_DISABLE_ALL 0x00000000 - -/* FMBM_PP - BMI Port Parameters */ -#define FMBM_PP_MXT_MASK 0x3f000000 /* Max # tasks */ -#define FMBM_PP_MXT(x) (((x-1) << 24) & FMBM_PP_MXT_MASK) -#define FMBM_PP_MXD_MASK 0x00000f00 /* Max DMA */ -#define FMBM_PP_MXD(x) (((x-1) << 8) & FMBM_PP_MXD_MASK) - -/* FMBM_PFS - BMI Port FIFO Size */ -#define FMBM_PFS_IFSZ_MASK 0x000003ff /* Internal Fifo Size */ -#define FMBM_PFS_IFSZ(x) (x & FMBM_PFS_IFSZ_MASK) - -/* FMQM_GC - global configuration */ -#define FMQM_GC_ENQ_EN 0x80000000 /* enqueue enable */ -#define FMQM_GC_DEQ_EN 0x40000000 /* dequeue enable */ -#define FMQM_GC_STEN 0x10000000 /* enable global stat counters */ -#define FMQM_GC_ENQ_THR_MASK 0x00003f00 /* max number of enqueue Tnum */ -#define FMQM_GC_ENQ(x) ((x << 8) & FMQM_GC_ENQ_THR_MAS) -#define FMQM_GC_DEQ_THR_MASK 0x0000003f /* max number of dequeue Tnum */ -#define FMQM_GC_DEQ(x) (x & FMQM_GC_DEQ_THR_MASK) - -/* FMQM_EIE - error interrupt event register */ -#define FMQM_EIE_DEE 0x80000000 /* double-bit ECC error */ -#define FMQM_EIE_DFUPE 0x40000000 /* dequeue from unknown PortID */ -#define FMQM_EIE_CLEAR_ALL (FMQM_EIE_DEE | FMQM_EIE_DFUPE) - -/* FMQM_EIEN - error interrupt enable register */ -#define FMQM_EIEN_DEEN 0x80000000 /* double-bit ECC error */ -#define FMQM_EIEN_DFUPEN 0x40000000 /* dequeue from unknown PortID */ -#define FMQM_EIEN_DISABLE_ALL 0x00000000 - -/* FMQM_IE - interrupt event register */ -#define FMQM_IE_SEE 0x80000000 /* single-bit ECC error detected */ -#define FMQM_IE_CLEAR_ALL FMQM_IE_SEE - -/* FMQM_IEN - interrupt enable register */ -#define FMQM_IEN_SEE 0x80000000 /* single-bit ECC err IRQ enable */ -#define FMQM_IEN_DISABLE_ALL 0x00000000 - -/* NIA - next invoked action */ -#define NIA_ENG_RISC 0x00000000 -#define NIA_ENG_MASK 0x007c0000 - -/* action code */ -#define NIA_RISC_AC_CC 0x00000006 -#define NIA_RISC_AC_IM_TX 0x00000008 /* independent mode Tx */ -#define NIA_RISC_AC_IM_RX 0x0000000a /* independent mode Rx */ -#define NIA_RISC_AC_HC 0x0000000c - -typedef struct fm_parser { - u8 res[1024]; -} fm_parser_t; - -typedef struct fm_policer { - u8 res[4*1024]; -} fm_policer_t; - -typedef struct fm_keygen { - u8 res[4*1024]; -} fm_keygen_t; - -typedef struct fm_dma { - u32 fmdmsr; /* status register */ - u32 fmdmmr; /* mode register */ - u32 fmdmtr; /* bus threshold register */ - u32 fmdmhy; /* bus hysteresis register */ - u32 fmdmsetr; /* SOS emergency threshold register */ - u32 fmdmtah; /* transfer bus address high register */ - u32 fmdmtal; /* transfer bus address low register */ - u32 fmdmtcid; /* transfer bus communication ID register */ - u32 fmdmra; /* DMA bus internal ram address register */ - u32 fmdmrd; /* DMA bus internal ram data register */ - u32 res0[0xb]; - u32 fmdmdcr; /* debug counter */ - u32 fmdmemsr; /* emrgency smoother register */ - u32 res1; - u32 fmdmplr[32]; /* FM DMA PID-LIODN # register */ - u32 res[0x3c8]; -} fm_dma_t; - -/* FMDMSR - Fman DMA status register */ -#define FMDMSR_CMDQNE 0x10000000 /* command queue not empty */ -#define FMDMSR_BER 0x08000000 /* bus err event occurred on bus */ -#define FMDMSR_RDB_ECC 0x04000000 /* read buffer ECC error */ -#define FMDMSR_WRB_SECC 0x02000000 /* write buf ECC err sys side */ -#define FMDMSR_WRB_FECC 0x01000000 /* write buf ECC err Fman side */ -#define FMDMSR_DPEXT_SECC 0x00800000 /* DP external ECC err sys side */ -#define FMDMSR_DPEXT_FECC 0x00400000 /* DP external ECC err Fman side */ -#define FMDMSR_DPDAT_SECC 0x00200000 /* DP data ECC err on sys side */ -#define FMDMSR_DPDAT_FECC 0x00100000 /* DP data ECC err on Fman side */ -#define FMDMSR_SPDAT_FECC 0x00080000 /* SP data ECC error Fman side */ - -#define FMDMSR_CLEAR_ALL (FMDMSR_BER | FMDMSR_RDB_ECC \ - | FMDMSR_WRB_SECC | FMDMSR_WRB_FECC \ - | FMDMSR_DPEXT_SECC | FMDMSR_DPEXT_FECC \ - | FMDMSR_DPDAT_SECC | FMDMSR_DPDAT_FECC \ - | FMDMSR_SPDAT_FECC) - -/* FMDMMR - FMan DMA mode register */ -#define FMDMMR_SBER 0x10000000 /* stop the DMA if a bus error */ - -typedef struct fm_fpm { - u32 fpmtnc; /* TNUM control */ - u32 fpmprc; /* Port_ID control */ - u32 res0; - u32 fpmflc; /* flush control */ - u32 fpmdis1; /* dispatch thresholds1 */ - u32 fpmdis2; /* dispatch thresholds2 */ - u32 fmepi; /* error pending interrupts */ - u32 fmrie; /* rams interrupt enable */ - u32 fpmfcevent[0x4];/* FMan controller event 0-3 */ - u32 res1[0x4]; - u32 fpmfcmask[0x4]; /* FMan controller mask 0-3 */ - u32 res2[0x4]; - u32 fpmtsc1; /* timestamp control1 */ - u32 fpmtsc2; /* timestamp control2 */ - u32 fpmtsp; /* time stamp */ - u32 fpmtsf; /* time stamp fraction */ - u32 fpmrcr; /* rams control and event */ - u32 res3[0x3]; - u32 fpmdrd[0x4]; /* data_ram data 0-3 */ - u32 res4[0xc]; - u32 fpmdra; /* data ram access */ - u32 fm_ip_rev_1; /* IP block revision 1 */ - u32 fm_ip_rev_2; /* IP block revision 2 */ - u32 fmrstc; /* reset command */ - u32 fmcld; /* classifier debug control */ - u32 fmnpi; /* normal pending interrupts */ - u32 res5; - u32 fmfpee; /* event and enable */ - u32 fpmcev[0x4]; /* CPU event 0-3 */ - u32 res6[0x4]; - u32 fmfp_ps[0x40]; /* port status */ - u32 res7[0x260]; - u32 fpmts[0x80]; /* task status */ - u32 res8[0xa0]; -} fm_fpm_t; - -/* FMFP_PRC - FPM Port_ID Control Register */ -#define FMFPPRC_PORTID_MASK 0x3f000000 -#define FMFPPRC_PORTID_SHIFT 24 -#define FMFPPRC_ORA_SHIFT 16 -#define FMFPPRC_RISC1 0x00000001 -#define FMFPPRC_RISC2 0x00000002 -#define FMFPPRC_RISC_ALL (FMFPPRC_RISC1 | FMFPPRC_RSIC2) - -/* FPM Flush Control Register */ -#define FMFP_FLC_DISP_LIM_NONE 0x00000000 /* no dispatch limitation */ - -/* FMFP_EE - FPM event and enable register */ -#define FMFPEE_DECC 0x80000000 /* double ECC err on FPM ram */ -#define FMFPEE_STL 0x40000000 /* stall of task ... */ -#define FMFPEE_SECC 0x20000000 /* single ECC error */ -#define FMFPEE_RFM 0x00010000 /* release FMan */ -#define FMFPEE_DECC_EN 0x00008000 /* double ECC interrupt enable */ -#define FMFPEE_STL_EN 0x00004000 /* stall of task interrupt enable */ -#define FMFPEE_SECC_EN 0x00002000 /* single ECC err interrupt enable */ -#define FMFPEE_EHM 0x00000008 /* external halt enable */ -#define FMFPEE_UEC 0x00000004 /* FMan is not halted */ -#define FMFPEE_CER 0x00000002 /* only errornous task stalled */ -#define FMFPEE_DER 0x00000001 /* DMA error is just reported */ - -#define FMFPEE_CLEAR_EVENT (FMFPEE_DECC | FMFPEE_STL | FMFPEE_SECC | \ - FMFPEE_EHM | FMFPEE_UEC | FMFPEE_CER | \ - FMFPEE_DER | FMFPEE_RFM) - -/* FMFP_RCR - FMan Rams Control and Event */ -#define FMFP_RCR_MDEC 0x00008000 /* double ECC error in muram */ -#define FMFP_RCR_IDEC 0x00004000 /* double ECC error in iram */ - -typedef struct fm_imem { - u32 iadd; /* instruction address register */ - u32 idata; /* instruction data register */ - u32 itcfg; /* timing config register */ - u32 iready; /* ready register */ - u8 res[0xff0]; -} fm_imem_t; -#define IRAM_IADD_AIE 0x80000000 /* address auto increase enable */ -#define IRAM_READY 0x80000000 /* ready to use */ - -typedef struct fm_soft_parser { - u8 res[4*1024]; -} fm_soft_parser_t; - -typedef struct fm_dtesc { - u8 res[4*1024]; -} fm_dtsec_t; - -typedef struct fm_mdio { - u8 res0[0x120]; - u32 miimcfg; /* MII management configuration reg */ - u32 miimcom; /* MII management command reg */ - u32 miimadd; /* MII management address reg */ - u32 miimcon; /* MII management control reg */ - u32 miimstat; /* MII management status reg */ - u32 miimind; /* MII management indication reg */ - u8 res1[0x1000 - 0x138]; -} fm_mdio_t; - -typedef struct fm_10gec { - u8 res[4*1024]; -} fm_10gec_t; - -typedef struct fm_10gec_mdio { - u8 res[4*1024]; -} fm_10gec_mdio_t; - -typedef struct fm_memac { - u8 res[4*1024]; -} fm_memac_t; - -typedef struct fm_memac_mdio { - u8 res[4*1024]; -} fm_memac_mdio_t; - -typedef struct fm_1588 { - u8 res[4*1024]; -} fm_1588_t; - -typedef struct ccsr_fman { - u8 muram[0x80000]; - fm_bmi_common_t fm_bmi_common; - fm_qmi_common_t fm_qmi_common; - u8 res0[2048]; - struct { - fm_bmi_t fm_bmi; - fm_qmi_t fm_qmi; - fm_parser_t fm_parser; - u8 res[1024]; - } port[63]; - fm_policer_t fm_policer; - fm_keygen_t fm_keygen; - fm_dma_t fm_dma; - fm_fpm_t fm_fpm; - fm_imem_t fm_imem; - u8 res1[8*1024]; - fm_soft_parser_t fm_soft_parser; - u8 res2[96*1024]; -#ifdef CONFIG_SYS_FMAN_V3 - struct { - fm_memac_t fm_memac; - fm_memac_mdio_t fm_memac_mdio; - } memac[10]; - u8 res4[32*1024]; - fm_memac_mdio_t fm_dedicated_mdio[2]; -#else - struct { - fm_dtsec_t fm_dtesc; - fm_mdio_t fm_mdio; - } mac_1g[8]; /* support up to 8 1g controllers */ - struct { - fm_10gec_t fm_10gec; - fm_10gec_mdio_t fm_10gec_mdio; - } mac_10g[1]; - u8 res4[48*1024]; -#endif - fm_1588_t fm_1588; - u8 res5[4*1024]; -} ccsr_fman_t; - -#endif /*__FSL_FMAN_H__*/ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 3b504875e0..8e1d22adef 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -10,6 +10,7 @@ #define _FSL_LAW_H_ #include <asm/io.h> +#include <linux/log2.h> #define LAW_EN 0x80000000 diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h index e5aab2a71f..ec25e16829 100644 --- a/arch/powerpc/include/asm/fsl_srio.h +++ b/arch/powerpc/include/asm/fsl_srio.h @@ -7,6 +7,8 @@ #ifndef _FSL_SRIO_H_ #define _FSL_SRIO_H_ +#include <linux/log2.h> + enum atmu_size { ATMU_SIZE_4K = 0xb, ATMU_SIZE_8K, diff --git a/arch/powerpc/include/asm/fsl_tgec.h b/arch/powerpc/include/asm/fsl_tgec.h deleted file mode 100644 index 92fb777c25..0000000000 --- a/arch/powerpc/include/asm/fsl_tgec.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __TGEC_H__ -#define __TGEC_H__ - -#include <phy.h> - -struct tgec { - /* 10GEC general control and status registers */ - u32 tgec_id; /* Controller ID register */ - u32 res0; - u32 command_config; /* Control and configuration register */ - u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */ - u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */ - u32 maxfrm; /* Maximum frame length register */ - u32 pause_quant; /* Pause quanta register */ - u32 res1[4]; - u32 hashtable_ctrl; /* Hash table control register */ - u32 res2[4]; - u32 status; /* MAC status register */ - u32 tx_ipg_length; /* Transmitter inter-packet-gap register */ - u32 mac_addr_2; /* Lower 32 bits of the 2nd 48-bit MAC addr */ - u32 mac_addr_3; /* Upper 16 bits of the 2nd 48-bit MAC addr */ - u32 res3[4]; - u32 imask; /* Interrupt mask register */ - u32 ievent; /* Interrupt event register */ - u32 res4[6]; - /* 10GEC statistics counter registers */ - u32 tx_frame_u; /* Tx frame counter upper */ - u32 tx_frame_l; /* Tx frame counter lower */ - u32 rx_frame_u; /* Rx frame counter upper */ - u32 rx_frame_l; /* Rx frame counter lower */ - u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */ - u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */ - u32 rx_align_err_u; /* Rx alignment error upper */ - u32 rx_align_err_l; /* Rx alignment error lower */ - u32 tx_pause_frame_u; /* Tx valid pause frame upper */ - u32 tx_pause_frame_l; /* Tx valid pause frame lower */ - u32 rx_pause_frame_u; /* Rx valid pause frame upper */ - u32 rx_pause_frame_l; /* Rx valid pause frame upper */ - u32 rx_long_err_u; /* Rx too long frame error upper */ - u32 rx_long_err_l; /* Rx too long frame error lower */ - u32 rx_frame_err_u; /* Rx frame length error upper */ - u32 rx_frame_err_l; /* Rx frame length error lower */ - u32 tx_vlan_u; /* Tx VLAN frame upper */ - u32 tx_vlan_l; /* Tx VLAN frame lower */ - u32 rx_vlan_u; /* Rx VLAN frame upper */ - u32 rx_vlan_l; /* Rx VLAN frame lower */ - u32 tx_oct_u; /* Tx octets upper */ - u32 tx_oct_l; /* Tx octets lower */ - u32 rx_oct_u; /* Rx octets upper */ - u32 rx_oct_l; /* Rx octets lower */ - u32 rx_uni_u; /* Rx unicast frame upper */ - u32 rx_uni_l; /* Rx unicast frame lower */ - u32 rx_multi_u; /* Rx multicast frame upper */ - u32 rx_multi_l; /* Rx multicast frame lower */ - u32 rx_brd_u; /* Rx broadcast frame upper */ - u32 rx_brd_l; /* Rx broadcast frame lower */ - u32 tx_frame_err_u; /* Tx frame error upper */ - u32 tx_frame_err_l; /* Tx frame error lower */ - u32 tx_uni_u; /* Tx unicast frame upper */ - u32 tx_uni_l; /* Tx unicast frame lower */ - u32 tx_multi_u; /* Tx multicast frame upper */ - u32 tx_multi_l; /* Tx multicast frame lower */ - u32 tx_brd_u; /* Tx broadcast frame upper */ - u32 tx_brd_l; /* Tx broadcast frame lower */ - u32 rx_drop_u; /* Rx dropped packets upper */ - u32 rx_drop_l; /* Rx dropped packets lower */ - u32 rx_eoct_u; /* Rx ethernet octets upper */ - u32 rx_eoct_l; /* Rx ethernet octets lower */ - u32 rx_pkt_u; /* Rx packets upper */ - u32 rx_pkt_l; /* Rx packets lower */ - u32 tx_undsz_u; /* Undersized packet upper */ - u32 tx_undsz_l; /* Undersized packet lower */ - u32 rx_64_u; /* Rx 64 oct packet upper */ - u32 rx_64_l; /* Rx 64 oct packet lower */ - u32 rx_127_u; /* Rx 65 to 127 oct packet upper */ - u32 rx_127_l; /* Rx 65 to 127 oct packet lower */ - u32 rx_255_u; /* Rx 128 to 255 oct packet upper */ - u32 rx_255_l; /* Rx 128 to 255 oct packet lower */ - u32 rx_511_u; /* Rx 256 to 511 oct packet upper */ - u32 rx_511_l; /* Rx 256 to 511 oct packet lower */ - u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */ - u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */ - u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */ - u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */ - u32 rx_1519_u; /* Rx 1519 to max oct packet upper */ - u32 rx_1519_l; /* Rx 1519 to max oct packet lower */ - u32 tx_oversz_u; /* oversized packet upper */ - u32 tx_oversz_l; /* oversized packet lower */ - u32 tx_jabber_u; /* Jabber packet upper */ - u32 tx_jabber_l; /* Jabber packet lower */ - u32 tx_frag_u; /* Fragment packet upper */ - u32 tx_frag_l; /* Fragment packet lower */ - u32 rx_err_u; /* Rx frame error upper */ - u32 rx_err_l; /* Rx frame error lower */ - u32 res5[0x39a]; -}; - -/* EC10G_ID - 10-gigabit ethernet MAC controller ID */ -#define EC10G_ID_VER_MASK 0x0000ff00 -#define EC10G_ID_VER_SHIFT 8 -#define EC10G_ID_REV_MASK 0x000000ff - -/* COMMAND_CONFIG - command and configuration register */ -#define TGEC_CMD_CFG_EN_TIMESTAMP 0x00100000 /* enable IEEE1588 */ -#define TGEC_CMD_CFG_TX_ADDR_INS_SEL 0x00080000 /* Tx mac addr w/ second */ -#define TGEC_CMD_CFG_NO_LEN_CHK 0x00020000 /* payload len chk disable */ -#define TGEC_CMD_CFG_SEND_IDLE 0x00010000 /* send XGMII idle seqs */ -#define TGEC_CMD_CFG_RX_ER_DISC 0x00004000 /* Rx err frm discard enb */ -#define TGEC_CMD_CFG_CMD_FRM_EN 0x00002000 /* CMD frame RX enable */ -#define TGEC_CMD_CFG_STAT_CLR 0x00001000 /* clear stats */ -#define TGEC_CMD_CFG_TX_ADDR_INS 0x00000200 /* overwrite src MAC addr */ -#define TGEC_CMD_CFG_PAUSE_IGNORE 0x00000100 /* ignore pause frames */ -#define TGEC_CMD_CFG_PAUSE_FWD 0x00000080 /* fwd pause frames */ -#define TGEC_CMD_CFG_CRC_FWD 0x00000040 /* fwd Rx CRC frames */ -#define TGEC_CMD_CFG_PAD_EN 0x00000020 /* MAC remove Rx padding */ -#define TGEC_CMD_CFG_PROM_EN 0x00000010 /* promiscuous mode enable */ -#define TGEC_CMD_CFG_WAN_MODE 0x00000008 /* WAN mode enable */ -#define TGEC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */ -#define TGEC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */ -#define TGEC_CMD_CFG_RXTX_EN (TGEC_CMD_CFG_RX_EN | TGEC_CMD_CFG_TX_EN) - -/* HASHTABLE_CTRL - Hashtable control register */ -#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */ -#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff - -/* TX_IPG_LENGTH - Transmit inter-packet gap length register */ -#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff - -/* IMASK - interrupt mask register */ -#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */ -#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */ -#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */ -#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */ -#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */ -#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */ -#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */ -#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */ -#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */ -#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */ -#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */ -#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */ -#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */ -#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */ -#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */ -#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */ - -#define IMASK_MASK_ALL 0x00000000 - -/* IEVENT - interrupt event register */ -#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */ -#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */ -#define IEVENT_REM_FAULT 0x00004000 /* remote fault */ -#define IEVENT_LOC_FAULT 0x00002000 /* local fault */ -#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */ -#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */ -#define IEVENT_TX_ER 0x00000200 /* Tx frame error */ -#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */ -#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */ -#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */ -#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */ -#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */ -#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */ -#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */ -#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */ -#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */ - -#define IEVENT_CLEAR_ALL 0xffffffff - -struct tgec_mdio_controller { - u32 res0[0xc]; - u32 mdio_stat; /* MDIO configuration and status */ - u32 mdio_ctl; /* MDIO control */ - u32 mdio_data; /* MDIO data */ - u32 mdio_addr; /* MDIO address */ -}; - -#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) -#define MDIO_STAT_BSY (1 << 0) -#define MDIO_STAT_RD_ER (1 << 1) -#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) -#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) -#define MDIO_CTL_PRE_DIS (1 << 10) -#define MDIO_CTL_SCAN_EN (1 << 11) -#define MDIO_CTL_POST_INC (1 << 14) -#define MDIO_CTL_READ (1 << 15) - -#define MDIO_DATA(x) (x & 0xffff) -#define MDIO_DATA_BSY (1 << 31) - -struct fsl_enet_mac; - -void init_tgec(struct fsl_enet_mac *mac, void *base, void *phyregs, - int max_rx_len); - -#endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 0c9d85ec96..101b8db0ee 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -19,7 +19,7 @@ #include <fsl_sec.h> #include <fsl_sfp.h> #include <asm/fsl_lbc.h> -#include <asm/fsl_fman.h> +#include <fsl_fman.h> #include <fsl_immap.h> typedef struct ccsr_local { diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index a5257e9b62..a54fc468d5 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -163,7 +163,7 @@ static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) * is actually performed (i.e. the data has come back) before we start * executing any following instructions. */ -extern inline u8 in_8(const volatile unsigned char __iomem *addr) +static inline u8 in_8(const volatile unsigned char __iomem *addr) { u8 ret; @@ -174,7 +174,7 @@ extern inline u8 in_8(const volatile unsigned char __iomem *addr) return ret; } -extern inline void out_8(volatile unsigned char __iomem *addr, u8 val) +static inline void out_8(volatile unsigned char __iomem *addr, u8 val) { __asm__ __volatile__("sync;\n" "stb%U0%X0 %1,%0;\n" @@ -182,7 +182,7 @@ extern inline void out_8(volatile unsigned char __iomem *addr, u8 val) : "r" (val)); } -extern inline u16 in_le16(const volatile unsigned short __iomem *addr) +static inline u16 in_le16(const volatile unsigned short __iomem *addr) { u16 ret; @@ -193,7 +193,7 @@ extern inline u16 in_le16(const volatile unsigned short __iomem *addr) return ret; } -extern inline u16 in_be16(const volatile unsigned short __iomem *addr) +static inline u16 in_be16(const volatile unsigned short __iomem *addr) { u16 ret; @@ -203,18 +203,18 @@ extern inline u16 in_be16(const volatile unsigned short __iomem *addr) return ret; } -extern inline void out_le16(volatile unsigned short __iomem *addr, u16 val) +static inline void out_le16(volatile unsigned short __iomem *addr, u16 val) { __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); } -extern inline void out_be16(volatile unsigned short __iomem *addr, u16 val) +static inline void out_be16(volatile unsigned short __iomem *addr, u16 val) { __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } -extern inline u32 in_le32(const volatile unsigned __iomem *addr) +static inline u32 in_le32(const volatile unsigned __iomem *addr) { u32 ret; @@ -225,7 +225,7 @@ extern inline u32 in_le32(const volatile unsigned __iomem *addr) return ret; } -extern inline u32 in_be32(const volatile unsigned __iomem *addr) +static inline u32 in_be32(const volatile unsigned __iomem *addr) { u32 ret; @@ -235,13 +235,13 @@ extern inline u32 in_be32(const volatile unsigned __iomem *addr) return ret; } -extern inline void out_le32(volatile unsigned __iomem *addr, u32 val) +static inline void out_le32(volatile unsigned __iomem *addr, u32 val) { __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); } -extern inline void out_be32(volatile unsigned __iomem *addr, u32 val) +static inline void out_be32(volatile unsigned __iomem *addr, u32 val) { __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } diff --git a/arch/powerpc/include/asm/iopin_8260.h b/arch/powerpc/include/asm/iopin_8260.h index 619f3a8abe..617584d7c7 100644 --- a/arch/powerpc/include/asm/iopin_8260.h +++ b/arch/powerpc/include/asm/iopin_8260.h @@ -23,140 +23,140 @@ iopin_t; #define IOPIN_PORTC 2 #define IOPIN_PORTD 3 -extern __inline__ void +static __inline__ void iopin_set_high(iopin_t *iopin) { volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } -extern __inline__ void +static __inline__ void iopin_set_low(iopin_t *iopin) { volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } -extern __inline__ uint +static __inline__ uint iopin_is_high(iopin_t *iopin) { volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } -extern __inline__ uint +static __inline__ uint iopin_is_low(iopin_t *iopin) { volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata; return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } -extern __inline__ void +static __inline__ void iopin_set_out(iopin_t *iopin) { volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } -extern __inline__ void +static __inline__ void iopin_set_in(iopin_t *iopin) { volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } -extern __inline__ uint +static __inline__ uint iopin_is_out(iopin_t *iopin) { volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } -extern __inline__ uint +static __inline__ uint iopin_is_in(iopin_t *iopin) { volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira; return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } -extern __inline__ void +static __inline__ void iopin_set_odr(iopin_t *iopin) { volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } -extern __inline__ void +static __inline__ void iopin_set_act(iopin_t *iopin) { volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } -extern __inline__ uint +static __inline__ uint iopin_is_odr(iopin_t *iopin) { volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } -extern __inline__ uint +static __inline__ uint iopin_is_act(iopin_t *iopin) { volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra; return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } -extern __inline__ void +static __inline__ void iopin_set_ded(iopin_t *iopin) { volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } -extern __inline__ void +static __inline__ void iopin_set_gen(iopin_t *iopin) { volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } -extern __inline__ uint +static __inline__ uint iopin_is_ded(iopin_t *iopin) { volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } -extern __inline__ uint +static __inline__ uint iopin_is_gen(iopin_t *iopin) { volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara; return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } -extern __inline__ void +static __inline__ void iopin_set_opt2(iopin_t *iopin) { volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } -extern __inline__ void +static __inline__ void iopin_set_opt1(iopin_t *iopin) { volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } -extern __inline__ uint +static __inline__ uint iopin_is_opt2(iopin_t *iopin) { volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } -extern __inline__ uint +static __inline__ uint iopin_is_opt1(iopin_t *iopin) { volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora; diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h index 0123bafcad..8db0fa2a1c 100644 --- a/arch/powerpc/include/asm/iopin_8xx.h +++ b/arch/powerpc/include/asm/iopin_8xx.h @@ -26,7 +26,7 @@ typedef struct { #define IOPIN_PORTC 2 #define IOPIN_PORTD 3 -extern __inline__ void +static __inline__ void iopin_set_high(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -44,7 +44,7 @@ iopin_set_high(iopin_t *iopin) } } -extern __inline__ void +static __inline__ void iopin_set_low(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -62,7 +62,7 @@ iopin_set_low(iopin_t *iopin) } } -extern __inline__ uint +static __inline__ uint iopin_is_high(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -81,7 +81,7 @@ iopin_is_high(iopin_t *iopin) return 0; } -extern __inline__ uint +static __inline__ uint iopin_is_low(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -100,7 +100,7 @@ iopin_is_low(iopin_t *iopin) return 0; } -extern __inline__ void +static __inline__ void iopin_set_out(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -118,7 +118,7 @@ iopin_set_out(iopin_t *iopin) } } -extern __inline__ void +static __inline__ void iopin_set_in(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -136,7 +136,7 @@ iopin_set_in(iopin_t *iopin) } } -extern __inline__ uint +static __inline__ uint iopin_is_out(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -155,7 +155,7 @@ iopin_is_out(iopin_t *iopin) return 0; } -extern __inline__ uint +static __inline__ uint iopin_is_in(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -174,7 +174,7 @@ iopin_is_in(iopin_t *iopin) return 0; } -extern __inline__ void +static __inline__ void iopin_set_odr(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -186,7 +186,7 @@ iopin_set_odr(iopin_t *iopin) } } -extern __inline__ void +static __inline__ void iopin_set_act(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -198,7 +198,7 @@ iopin_set_act(iopin_t *iopin) } } -extern __inline__ uint +static __inline__ uint iopin_is_odr(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -211,7 +211,7 @@ iopin_is_odr(iopin_t *iopin) return 0; } -extern __inline__ uint +static __inline__ uint iopin_is_act(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -224,7 +224,7 @@ iopin_is_act(iopin_t *iopin) return 0; } -extern __inline__ void +static __inline__ void iopin_set_ded(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -242,7 +242,7 @@ iopin_set_ded(iopin_t *iopin) } } -extern __inline__ void +static __inline__ void iopin_set_gen(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -260,7 +260,7 @@ iopin_set_gen(iopin_t *iopin) } } -extern __inline__ uint +static __inline__ uint iopin_is_ded(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -279,7 +279,7 @@ iopin_is_ded(iopin_t *iopin) return 0; } -extern __inline__ uint +static __inline__ uint iopin_is_gen(iopin_t *iopin) { if (iopin->port == IOPIN_PORTA) { @@ -298,7 +298,7 @@ iopin_is_gen(iopin_t *iopin) return 0; } -extern __inline__ void +static __inline__ void iopin_set_opt2(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -307,7 +307,7 @@ iopin_set_opt2(iopin_t *iopin) } } -extern __inline__ void +static __inline__ void iopin_set_opt1(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -316,7 +316,7 @@ iopin_set_opt1(iopin_t *iopin) } } -extern __inline__ uint +static __inline__ uint iopin_is_opt2(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -326,7 +326,7 @@ iopin_is_opt2(iopin_t *iopin) return 0; } -extern __inline__ uint +static __inline__ uint iopin_is_opt1(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -336,7 +336,7 @@ iopin_is_opt1(iopin_t *iopin) return 0; } -extern __inline__ void +static __inline__ void iopin_set_falledge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -345,7 +345,7 @@ iopin_set_falledge(iopin_t *iopin) } } -extern __inline__ void +static __inline__ void iopin_set_anyedge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -354,7 +354,7 @@ iopin_set_anyedge(iopin_t *iopin) } } -extern __inline__ uint +static __inline__ uint iopin_is_falledge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { @@ -364,7 +364,7 @@ iopin_is_falledge(iopin_t *iopin) return 0; } -extern __inline__ uint +static __inline__ uint iopin_is_anyedge(iopin_t *iopin) { if (iopin->port == IOPIN_PORTC) { |