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-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig48
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h32
2 files changed, 48 insertions, 32 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index ec58cd12fc..e4873f5e82 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -569,6 +569,54 @@ config SYS_CCSRBAR_DEFAULT
if changed by pre-boot regime. The value here must match
the current value in SoC. If not sure, do not change.
+config SYS_FSL_NUM_LAWS
+ int "Number of local access windows"
+ depends on FSL_LAW
+ default 32 if ARCH_B4420 || \
+ ARCH_B4860 || \
+ ARCH_P2041 || \
+ ARCH_P3041 || \
+ ARCH_P4080 || \
+ ARCH_P5020 || \
+ ARCH_P5040 || \
+ ARCH_T2080 || \
+ ARCH_T2081 || \
+ ARCH_T4160 || \
+ ARCH_T4240
+ default 16 if ARCH_T1013 || \
+ ARCH_T1014 || \
+ ARCH_T1020 || \
+ ARCH_T1022 || \
+ ARCH_T1023 || \
+ ARCH_T1024 || \
+ ARCH_T1040 || \
+ ARCH_T1042
+ default 12 if ARCH_BSC9131 || \
+ ARCH_BSC9132 || \
+ ARCH_C29X || \
+ ARCH_MPC8536 || \
+ ARCH_MPC8572 || \
+ ARCH_P1010 || \
+ ARCH_P1011 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1023 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020
+ default 10 if ARCH_MPC8544 || \
+ ARCH_MPC8548 || \
+ ARCH_MPC8568 || \
+ ARCH_MPC8569
+ default 8 if ARCH_MPC8540 || \
+ ARCH_MPC8541 || \
+ ARCH_MPC8555 || \
+ ARCH_MPC8560
+ help
+ Number of local access windows. This is fixed per SoC.
+ If not sure, do not change.
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 474fd1af7d..4877b75981 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -32,30 +32,25 @@
#endif
#if defined(CONFIG_ARCH_MPC8536)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8540)
-#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#elif defined(CONFIG_ARCH_MPC8541)
-#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#elif defined(CONFIG_ARCH_MPC8544)
-#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8548)
-#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -72,16 +67,13 @@
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
#elif defined(CONFIG_ARCH_MPC8555)
-#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#elif defined(CONFIG_ARCH_MPC8560)
-#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#elif defined(CONFIG_ARCH_MPC8568)
-#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x10000UL
@@ -94,7 +86,6 @@
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_MPC8569)
-#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x20000UL
#define MAX_QE_RISC 4
@@ -108,7 +99,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_MPC8572)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_DDR_115
@@ -118,7 +108,6 @@
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
@@ -144,7 +133,6 @@
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_ARCH_P1011)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -156,7 +144,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P1020)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -170,7 +157,6 @@
#endif
#elif defined(CONFIG_ARCH_P1021)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -185,7 +171,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#elif defined(CONFIG_ARCH_P1022)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -198,7 +183,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A004477
#elif defined(CONFIG_ARCH_P1023)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 2
@@ -215,7 +199,6 @@
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_ARCH_P1024)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -228,7 +211,6 @@
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_ARCH_P1025)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
@@ -243,7 +225,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -262,7 +243,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@@ -298,7 +278,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@@ -336,7 +315,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 4
@@ -386,7 +364,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@@ -420,7 +397,6 @@
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@@ -449,7 +425,6 @@
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
@@ -467,7 +442,6 @@
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 2
@@ -515,7 +489,6 @@
#endif
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_SRDS_3
@@ -557,7 +530,6 @@
#define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
#define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
#define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_MAPLE
@@ -625,7 +597,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
-#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
@@ -671,7 +642,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
-#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
@@ -709,7 +679,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_QMAN_V3
-#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
@@ -756,7 +725,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2_1
#define CONFIG_SYS_FSL_SEC_COMPAT 6
generated by cgit (git 2.34.1) at 2024-12-27 08:44:54 +0000