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-rw-r--r--arch/riscv/cpu/cpu.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c32de8a4c3..e9a8b437ed 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -15,7 +15,10 @@
* The variables here must be stored in the data section since they are used
* before the bss section is available.
*/
+#ifdef CONFIG_OF_PRIOR_STAGE
phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#endif
+#ifndef CONFIG_XIP
u32 hart_lottery __attribute__((section(".data"))) = 0;
/*
@@ -23,6 +26,7 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
* finished initialization of global data.
*/
u32 available_harts_lock = 1;
+#endif
static inline bool supports_extension(char ext)
{