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-rw-r--r--arch/riscv/cpu/cpu.c15
-rw-r--r--arch/riscv/cpu/start.S2
2 files changed, 17 insertions, 0 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 5804aa8e73..bbd6c15352 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -91,13 +91,28 @@ int arch_cpu_init_dm(void)
* Enable perf counters for cycle, time,
* and instret counters only
*/
+#ifdef CONFIG_RISCV_PRIV_1_9
+ csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
+ csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
+#else
csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
+#endif
/* Disable paging */
if (supports_extension('s'))
+#ifdef CONFIG_RISCV_PRIV_1_9
+ csr_read_clear(CSR_MSTATUS, SR_VM);
+#else
csr_write(CSR_SATP, 0);
+#endif
}
+#ifdef CONFIG_SMP
+ ret = riscv_init_ipi();
+ if (ret)
+ return ret;
+#endif
+
return 0;
}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 5f1c220e0c..f408e41ab9 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -65,6 +65,8 @@ _start:
#else
li t0, SIE_SSIE
#endif
+ /* Clear any pending IPIs */
+ csrc MODE_PREFIX(ip), t0
csrs MODE_PREFIX(ie), t0
#endif