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-rw-r--r--arch/sh/include/asm/cpu_sh4.h4
-rw-r--r--arch/sh/include/asm/cpu_sh7724.h209
-rw-r--r--arch/sh/include/asm/cpu_sh7785.h119
3 files changed, 0 insertions, 332 deletions
diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h
index b558d6935c..5fc9c962d8 100644
--- a/arch/sh/include/asm/cpu_sh4.h
+++ b/arch/sh/include/asm/cpu_sh4.h
@@ -30,8 +30,6 @@
# include <asm/cpu_sh7722.h>
#elif defined (CONFIG_CPU_SH7723)
# include <asm/cpu_sh7723.h>
-#elif defined (CONFIG_CPU_SH7724)
-# include <asm/cpu_sh7724.h>
#elif defined (CONFIG_CPU_SH7734)
# include <asm/cpu_sh7734.h>
#elif defined (CONFIG_CPU_SH7752)
@@ -44,8 +42,6 @@
# include <asm/cpu_sh7763.h>
#elif defined (CONFIG_CPU_SH7780)
# include <asm/cpu_sh7780.h>
-#elif defined (CONFIG_CPU_SH7785)
-# include <asm/cpu_sh7785.h>
#else
# error "Unknown SH4 variant"
#endif
diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h
deleted file mode 100644
index 7b217959ed..0000000000
--- a/arch/sh/include/asm/cpu_sh7724.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008, 2011 Renesas Solutions Corp.
- *
- * SH7724 Internal I/O register
- */
-
-#ifndef _ASM_CPU_SH7724_H_
-#define _ASM_CPU_SH7724_H_
-
-#define CACHE_OC_NUM_WAYS 4
-#define CCR_CACHE_INIT 0x0000090d
-
-/* EXP */
-#define TRA 0xFF000020
-#define EXPEVT 0xFF000024
-#define INTEVT 0xFF000028
-
-/* MMU */
-#define PTEH 0xFF000000
-#define PTEL 0xFF000004
-#define TTB 0xFF000008
-#define TEA 0xFF00000C
-#define MMUCR 0xFF000010
-#define PASCR 0xFF000070
-#define IRMCR 0xFF000078
-
-/* CACHE */
-#define CCR 0xFF00001C
-#define RAMCR 0xFF000074
-
-/* INTC */
-
-/* BSC */
-#define MMSELR 0xFF800020
-#define CMNCR 0xFEC10000
-#define CS0BCR 0xFEC10004
-#define CS2BCR 0xFEC10008
-#define CS4BCR 0xFEC10010
-#define CS5ABCR 0xFEC10014
-#define CS5BBCR 0xFEC10018
-#define CS6ABCR 0xFEC1001C
-#define CS6BBCR 0xFEC10020
-#define CS0WCR 0xFEC10024
-#define CS2WCR 0xFEC10028
-#define CS4WCR 0xFEC10030
-#define CS5AWCR 0xFEC10034
-#define CS5BWCR 0xFEC10038
-#define CS6AWCR 0xFEC1003C
-#define CS6BWCR 0xFEC10040
-#define RBWTCNT 0xFEC10054
-
-/* SBSC */
-#define SBSC_SDCR 0xFE400008
-#define SBSC_SDWCR 0xFE40000C
-#define SBSC_SDPCR 0xFE400010
-#define SBSC_RTCSR 0xFE400014
-#define SBSC_RTCNT 0xFE400018
-#define SBSC_RTCOR 0xFE40001C
-#define SBSC_RFCR 0xFE400020
-
-/* DSBC */
-#define DBKIND 0xFD000008
-#define DBSTATE 0xFD00000C
-#define DBEN 0xFD000010
-#define DBCMDCNT 0xFD000014
-#define DBCKECNT 0xFD000018
-#define DBCONF 0xFD000020
-#define DBTR0 0xFD000030
-#define DBTR1 0xFD000034
-#define DBTR2 0xFD000038
-#define DBTR3 0xFD00003C
-#define DBRFPDN0 0xFD000040
-#define DBRFPDN1 0xFD000044
-#define DBRFPDN2 0xFD000048
-#define DBRFSTS 0xFD00004C
-#define DBMRCNT 0xFD000060
-#define DBPDCNT0 0xFD000108
-
-/* DMAC */
-
-/* CPG */
-#define FRQCRA 0xA4150000
-#define FRQCRB 0xA4150004
-#define FRQCR FRQCRA
-#define VCLKCR 0xA4150004
-#define SCLKACR 0xA4150008
-#define SCLKBCR 0xA415000C
-#define IRDACLKCR 0xA4150018
-#define PLLCR 0xA4150024
-#define DLLFRQ 0xA4150050
-
-/* LOW POWER MODE */
-#define STBCR 0xA4150020
-#define MSTPCR0 0xA4150030
-#define MSTPCR1 0xA4150034
-#define MSTPCR2 0xA4150038
-
-/* RWDT */
-#define RWTCNT 0xA4520000
-#define RWTCSR 0xA4520004
-#define WTCNT RWTCNT
-
-/* TMU */
-#define TMU_BASE 0xFFD80000
-
-/* TPU */
-
-/* CMT */
-#define CMSTR 0xA44A0000
-#define CMCSR 0xA44A0060
-#define CMCNT 0xA44A0064
-#define CMCOR 0xA44A0068
-
-/* MSIOF */
-
-/* SCIF */
-#define SCIF0_BASE 0xFFE00000
-#define SCIF1_BASE 0xFFE10000
-#define SCIF2_BASE 0xFFE20000
-#define SCIF3_BASE 0xa4e30000
-#define SCIF4_BASE 0xa4e40000
-#define SCIF5_BASE 0xa4e50000
-
-/* RTC */
-/* IrDA */
-/* KEYSC */
-/* USB */
-/* IIC */
-/* FLCTL */
-/* VPU */
-/* VIO(CEU) */
-/* VIO(VEU) */
-/* VIO(BEU) */
-/* 2DG */
-/* LCDC */
-/* VOU */
-/* TSIF */
-/* SIU */
-/* ATAPI */
-
-/* PFC */
-#define PACR 0xA4050100
-#define PBCR 0xA4050102
-#define PCCR 0xA4050104
-#define PDCR 0xA4050106
-#define PECR 0xA4050108
-#define PFCR 0xA405010A
-#define PGCR 0xA405010C
-#define PHCR 0xA405010E
-#define PJCR 0xA4050110
-#define PKCR 0xA4050112
-#define PLCR 0xA4050114
-#define PMCR 0xA4050116
-#define PNCR 0xA4050118
-#define PQCR 0xA405011A
-#define PRCR 0xA405011C
-#define PSCR 0xA405011E
-#define PTCR 0xA4050140
-#define PUCR 0xA4050142
-#define PVCR 0xA4050144
-#define PWCR 0xA4050146
-#define PXCR 0xA4050148
-#define PYCR 0xA405014A
-#define PZCR 0xA405014C
-#define PSELA 0xA405014E
-#define PSELB 0xA4050150
-#define PSELC 0xA4050152
-#define PSELD 0xA4050154
-#define PSELE 0xA4050156
-#define HIZCRA 0xA4050158
-#define HIZCRB 0xA405015A
-#define HIZCRC 0xA405015C
-#define HIZCRD 0xA405015E
-#define MSELCRA 0xA4050180
-#define MSELCRB 0xA4050182
-#define PULCR 0xA4050184
-#define DRVCRA 0xA405018A
-#define DRVCRB 0xA405018C
-
-/* I/O Port */
-#define PADR 0xA4050120
-#define PBDR 0xA4050122
-#define PCDR 0xA4050124
-#define PDDR 0xA4050126
-#define PEDR 0xA4050128
-#define PFDR 0xA405012A
-#define PGDR 0xA405012C
-#define PHDR 0xA405012E
-#define PJDR 0xA4050130
-#define PKDR 0xA4050132
-#define PLDR 0xA4050134
-#define PMDR 0xA4050136
-#define PNDR 0xA4050138
-#define PQDR 0xA405013A
-#define PRDR 0xA405013C
-#define PSDR 0xA405013E
-#define PTDR 0xA4050160
-#define PUDR 0xA4050162
-#define PVDR 0xA4050164
-#define PWDR 0xA4050166
-#define PXDR 0xA4050168
-#define PYDR 0xA405016A
-#define PZDR 0xA405016C
-
-/* UBC */
-/* H-UDI */
-
-#endif /* _ASM_CPU_SH7724_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7785.h b/arch/sh/include/asm/cpu_sh7785.h
deleted file mode 100644
index b0388957f9..0000000000
--- a/arch/sh/include/asm/cpu_sh7785.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-#ifndef _ASM_CPU_SH7785_H_
-#define _ASM_CPU_SH7785_H_
-
-/*
- * Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
- * Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
- */
-
-#define CACHE_OC_NUM_WAYS 1
-#define CCR_CACHE_INIT 0x0000090b
-
-/* Exceptions */
-#define TRA 0xFF000020
-#define EXPEVT 0xFF000024
-#define INTEVT 0xFF000028
-
-/* Cache Controller */
-#define CCR 0xFF00001C
-#define QACR0 0xFF000038
-#define QACR1 0xFF00003C
-#define RAMCR 0xFF000074
-
-/* Watchdog Timer and Reset */
-#define WTCNT WDTCNT
-#define WDTST 0xFFCC0000
-#define WDTCSR 0xFFCC0004
-#define WDTBST 0xFFCC0008
-#define WDTCNT 0xFFCC0010
-#define WDTBCNT 0xFFCC0018
-
-/* Timer Unit */
-#define TMU_BASE 0xFFD80000
-
-/* Serial Communication Interface with FIFO */
-#define SCIF1_BASE 0xffeb0000
-
-/* LBSC */
-#define MMSELR 0xfc400020
-#define LBSC_BASE 0xff800000
-#define BCR (LBSC_BASE + 0x1000)
-#define CS0BCR (LBSC_BASE + 0x2000)
-#define CS1BCR (LBSC_BASE + 0x2010)
-#define CS2BCR (LBSC_BASE + 0x2020)
-#define CS3BCR (LBSC_BASE + 0x2030)
-#define CS4BCR (LBSC_BASE + 0x2040)
-#define CS5BCR (LBSC_BASE + 0x2050)
-#define CS6BCR (LBSC_BASE + 0x2060)
-#define CS0WCR (LBSC_BASE + 0x2008)
-#define CS1WCR (LBSC_BASE + 0x2018)
-#define CS2WCR (LBSC_BASE + 0x2028)
-#define CS3WCR (LBSC_BASE + 0x2038)
-#define CS4WCR (LBSC_BASE + 0x2048)
-#define CS5WCR (LBSC_BASE + 0x2058)
-#define CS6WCR (LBSC_BASE + 0x2068)
-#define CS5PCR (LBSC_BASE + 0x2070)
-#define CS6PCR (LBSC_BASE + 0x2080)
-
-/* PCI Controller */
-#define SH7780_PCIECR 0xFE000008
-#define SH7780_PCIVID 0xFE040000
-#define SH7780_PCIDID 0xFE040002
-#define SH7780_PCICMD 0xFE040004
-#define SH7780_PCISTATUS 0xFE040006
-#define SH7780_PCIRID 0xFE040008
-#define SH7780_PCIPIF 0xFE040009
-#define SH7780_PCISUB 0xFE04000A
-#define SH7780_PCIBCC 0xFE04000B
-#define SH7780_PCICLS 0xFE04000C
-#define SH7780_PCILTM 0xFE04000D
-#define SH7780_PCIHDR 0xFE04000E
-#define SH7780_PCIBIST 0xFE04000F
-#define SH7780_PCIIBAR 0xFE040010
-#define SH7780_PCIMBAR0 0xFE040014
-#define SH7780_PCIMBAR1 0xFE040018
-#define SH7780_PCISVID 0xFE04002C
-#define SH7780_PCISID 0xFE04002E
-#define SH7780_PCICP 0xFE040034
-#define SH7780_PCIINTLINE 0xFE04003C
-#define SH7780_PCIINTPIN 0xFE04003D
-#define SH7780_PCIMINGNT 0xFE04003E
-#define SH7780_PCIMAXLAT 0xFE04003F
-#define SH7780_PCICID 0xFE040040
-#define SH7780_PCINIP 0xFE040041
-#define SH7780_PCIPMC 0xFE040042
-#define SH7780_PCIPMCSR 0xFE040044
-#define SH7780_PCIPMCSRBSE 0xFE040046
-#define SH7780_PCI_CDD 0xFE040047
-#define SH7780_PCICR 0xFE040100
-#define SH7780_PCILSR0 0xFE040104
-#define SH7780_PCILSR1 0xFE040108
-#define SH7780_PCILAR0 0xFE04010C
-#define SH7780_PCILAR1 0xFE040110
-#define SH7780_PCIIR 0xFE040114
-#define SH7780_PCIIMR 0xFE040118
-#define SH7780_PCIAIR 0xFE04011C
-#define SH7780_PCICIR 0xFE040120
-#define SH7780_PCIAINT 0xFE040130
-#define SH7780_PCIAINTM 0xFE040134
-#define SH7780_PCIBMIR 0xFE040138
-#define SH7780_PCIPAR 0xFE0401C0
-#define SH7780_PCIPINT 0xFE0401CC
-#define SH7780_PCIPINTM 0xFE0401D0
-#define SH7780_PCIMBR0 0xFE0401E0
-#define SH7780_PCIMBMR0 0xFE0401E4
-#define SH7780_PCIMBR1 0xFE0401E8
-#define SH7780_PCIMBMR1 0xFE0401EC
-#define SH7780_PCIMBR2 0xFE0401F0
-#define SH7780_PCIMBMR2 0xFE0401F4
-#define SH7780_PCIIOBR 0xFE0401F8
-#define SH7780_PCIIOBMR 0xFE0401FC
-#define SH7780_PCICSCR0 0xFE040210
-#define SH7780_PCICSCR1 0xFE040214
-#define SH7780_PCICSAR0 0xFE040218
-#define SH7780_PCICSAR1 0xFE04021C
-#define SH7780_PCIPDR 0xFE040220
-
-#endif /* _ASM_CPU_SH7780_H_ */
generated by cgit (git 2.34.1) at 2025-01-15 07:36:59 +0000