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-rw-r--r--arch/x86/cpu/qemu/Kconfig7
-rw-r--r--arch/x86/cpu/qemu/qemu.c29
2 files changed, 36 insertions, 0 deletions
diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig
index 4f9862194a..6808c9a6b9 100644
--- a/arch/x86/cpu/qemu/Kconfig
+++ b/arch/x86/cpu/qemu/Kconfig
@@ -17,4 +17,11 @@ config SYS_CAR_SIZE
hex
default 0x10000
+config ACPI_PM1_BASE
+ hex
+ default 0xe400
+ help
+ ACPI Power Managment 1 (PM1) i/o-mapped base address.
+ This device is defined in ACPI specification, with 16 bytes in size.
+
endif
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 5a7b92944a..f8af566dea 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -15,6 +15,31 @@
static bool i440fx;
+static void enable_pm_piix(void)
+{
+ u8 en;
+ u16 cmd;
+
+ /* Set the PM I/O base */
+ x86_pci_write_config32(PIIX_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
+
+ /* Enable access to the PM I/O space */
+ cmd = x86_pci_read_config16(PIIX_PM, PCI_COMMAND);
+ cmd |= PCI_COMMAND_IO;
+ x86_pci_write_config16(PIIX_PM, PCI_COMMAND, cmd);
+
+ /* PM I/O Space Enable (PMIOSE) */
+ en = x86_pci_read_config8(PIIX_PM, PMREGMISC);
+ en |= PMIOSE;
+ x86_pci_write_config8(PIIX_PM, PMREGMISC, en);
+}
+
+static void enable_pm_ich9(void)
+{
+ /* Set the PM I/O base */
+ x86_pci_write_config32(ICH9_PM, PMBA, CONFIG_ACPI_PM1_BASE | 1);
+}
+
static void qemu_chipset_init(void)
{
u16 device, xbcs;
@@ -53,10 +78,14 @@ static void qemu_chipset_init(void)
xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
xbcs |= APIC_EN;
x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
+
+ enable_pm_piix();
} else {
/* Configure PCIe ECAM base address */
x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
CONFIG_PCIE_ECAM_BASE | BAR_EN);
+
+ enable_pm_ich9();
}
qemu_fwcfg_init();