summaryrefslogtreecommitdiff
path: root/arch/x86/include/asm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/x86/include/asm')
-rw-r--r--arch/x86/include/asm/arch-tangier/acpi/southcluster.asl87
1 files changed, 87 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
index e166e510cb..baad98b1c7 100644
--- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
+++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
@@ -320,6 +320,93 @@ Device (PCI0)
})
}
}
+
+ Device (IPC1)
+ {
+ Name (_ADR, 0x00130000)
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA_VISIBLE)
+ }
+
+ Device (PMIC)
+ {
+ Name (_ADR, Zero)
+ Name (_HID, "INTC100E")
+ Name (_CID, "INTC100E")
+ Name (_DDN, "Basin Cove PMIC")
+ Name (_DEP, Package ()
+ {
+ IPC1
+ })
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (STA_VISIBLE)
+ }
+
+ Method (_CRS, 0, Serialized)
+ {
+ Name (RBUF, ResourceTemplate()
+ {
+ /*
+ * Shadow registers in SRAM for PMIC:
+ * SRAM PMIC register
+ * --------------------
+ * 0x00- Unknown
+ * 0x03 THRMIRQ (0x04)
+ * 0x04 BCUIRQ (0x05)
+ * 0x05 ADCIRQ (0x06)
+ * 0x06 CHGRIRQ0 (0x07)
+ * 0x07 CHGRIRQ1 (0x08)
+ * 0x08- Unknown
+ * 0x0a PBSTATUS (0x27)
+ * 0x0b- Unknown
+ */
+ Memory32Fixed(ReadWrite, 0xFFFFF610, 0x00000010)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 30 }
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 23 }
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 52 }
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 51 }
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 50 }
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 27 }
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 49 }
+ })
+ Return (RBUF)
+ }
+
+ OperationRegion (PMOP, 0x8D, Zero, 0x0100)
+ Field (PMOP, DWordAcc, NoLock, Preserve)
+ {
+ SEL1, 32,
+ SEL2, 32,
+ VCCL, 32,
+ VNNL, 32,
+ AONL, 32,
+ CNTC, 32,
+ CNTN, 32,
+ AONN, 32,
+ CNT1, 32,
+ CNT2, 32,
+ CNT3, 32,
+ FLEX, 32,
+ PRG1, 32,
+ PRG2, 32,
+ PRG3, 32,
+ VLDO, 32,
+ }
+
+ Name (AVBL, Zero)
+ Method (_REG, 2, NotSerialized)
+ {
+ If ((Arg0 == 0x8D))
+ {
+ AVBL = Arg1
+ }
+ }
+ }
+ }
}
Device (FLIS)