diff options
Diffstat (limited to 'arch/x86/include/asm')
| -rw-r--r-- | arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h | 5 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h | 9 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-apollolake/fsp_bindings.h | 1 | ||||
| -rw-r--r-- | arch/x86/include/asm/irq.h | 6 |
4 files changed, 16 insertions, 5 deletions
diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h index 5275b75f3b..78c338e9ff 100644 --- a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h @@ -122,7 +122,10 @@ struct __packed fsp_m_config { /* 0x150 */ void *variable_nvs_buffer_ptr; - u8 reserved_fspm_upd[12]; + u64 start_timer_ticker_of_pfet_assert; + u8 rt_en; + u8 skip_pcie_power_sequence; + u8 reserved_fspm_upd[2]; }; /** FSP-M UPD Configuration */ diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h index 451a7a254a..be80f5db09 100644 --- a/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h @@ -351,7 +351,10 @@ struct __packed fsp_s_config { u8 port_usb20_hs_npre_drv_sel[8]; /* 0x370 */ - u8 reserved_fsps_upd[16]; + u8 os_selection; + u8 dptf_enabled; + u8 pwm_enabled; + u8 reserved_fsps_upd[13]; }; /** struct fsps_upd - FSP-S Configuration */ @@ -563,4 +566,8 @@ struct __packed fsps_upd { #define PCIE_RP_SELECTABLE_DEEMPHASIS_6_DB 0 #define PCIE_RP_SELECTABLE_DEEMPHASIS_3_5_DB 1 +#define OS_SELECTION_WINDOWS 0 +#define OS_SELECTION_ANDROID 1 +#define OS_SELECTION_LINUX 3 + #endif diff --git a/arch/x86/include/asm/arch-apollolake/fsp_bindings.h b/arch/x86/include/asm/arch-apollolake/fsp_bindings.h index b4939519ce..a80e66bbfa 100644 --- a/arch/x86/include/asm/arch-apollolake/fsp_bindings.h +++ b/arch/x86/include/asm/arch-apollolake/fsp_bindings.h @@ -17,6 +17,7 @@ enum conf_type { FSP_UINT8, FSP_UINT16, FSP_UINT32, + FSP_UINT64, FSP_STRING, FSP_LPDDR4_SWIZZLE, }; diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index e5c916070c..bee0760c2d 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -12,8 +12,8 @@ * Intel interrupt router configuration mechanism * * There are two known ways of Intel interrupt router configuration mechanism - * so far. On most cases, the IRQ routing configuraiton is controlled by PCI - * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0). + * so far. On most cases, the IRQ routing configuration is controlled by PCI + * configuration registers on the legacy bridge, normally PCI BDF(0, 31, 0). * On some newer platforms like BayTrail and Braswell, the IRQ routing is now * in the IBASE register block where IBASE is memory-mapped. */ @@ -36,7 +36,7 @@ struct pirq_regmap { * @link_base: link value base number * @link_num: number of PIRQ links supported * @has_regmap: has mapping table between PIRQ link and routing register offset - * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means + * @irq_mask: IRQ mask representing the 16 IRQs in 8259, bit N is 1 means * IRQ N is available to be routed * @lb_bdf: irq router's PCI bus/device/function number encoding * @ibase: IBASE register block base address |