diff options
Diffstat (limited to 'arch/x86')
38 files changed, 1186 insertions, 171 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c8eae24c07..27295ef384 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -717,6 +717,7 @@ config HAVE_ITSS config HAVE_P2SB bool "Enable P2SB" + depends on P2SB help Select this to include the driver for the Primary to Sideband Bridge (P2SB) which is found on several Intel diff --git a/arch/x86/cpu/acpi_gpe.c b/arch/x86/cpu/acpi_gpe.c index 8aa2009bd6..70badb15a3 100644 --- a/arch/x86/cpu/acpi_gpe.c +++ b/arch/x86/cpu/acpi_gpe.c @@ -8,7 +8,10 @@ #include <dm.h> #include <irq.h> #include <log.h> +#include <acpi/acpi_device.h> #include <asm/io.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/x86-irq.h> /** * struct acpi_gpe_priv - private driver information @@ -62,13 +65,36 @@ static int acpi_gpe_ofdata_to_platdata(struct udevice *dev) static int acpi_gpe_of_xlate(struct irq *irq, struct ofnode_phandle_args *args) { irq->id = args->args[0]; + irq->flags = args->args[1]; return 0; } +#if CONFIG_IS_ENABLED(ACPIGEN) +static int acpi_gpe_get_acpi(const struct irq *irq, struct acpi_irq *acpi_irq) +{ + memset(acpi_irq, '\0', sizeof(*acpi_irq)); + acpi_irq->pin = irq->id; + acpi_irq->mode = irq->flags & IRQ_TYPE_EDGE_BOTH ? + ACPI_IRQ_EDGE_TRIGGERED : ACPI_IRQ_LEVEL_TRIGGERED; + acpi_irq->polarity = irq->flags & + (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW) ? + ACPI_IRQ_ACTIVE_LOW : ACPI_IRQ_ACTIVE_HIGH; + acpi_irq->shared = irq->flags & X86_IRQ_TYPE_SHARED ? + ACPI_IRQ_SHARED : ACPI_IRQ_EXCLUSIVE; + acpi_irq->wake = irq->flags & X86_IRQ_TYPE_WAKE ? ACPI_IRQ_WAKE : + ACPI_IRQ_NO_WAKE; + + return 0; +} +#endif + static const struct irq_ops acpi_gpe_ops = { .read_and_clear = acpi_gpe_read_and_clear, .of_xlate = acpi_gpe_of_xlate, +#if CONFIG_IS_ENABLED(ACPIGEN) + .get_acpi = acpi_gpe_get_acpi, +#endif }; static const struct udevice_id acpi_gpe_ids[] = { diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c index 707ceb3e64..9f32f2e27e 100644 --- a/arch/x86/cpu/apollolake/cpu_spl.c +++ b/arch/x86/cpu/apollolake/cpu_spl.c @@ -247,12 +247,13 @@ static int arch_cpu_init_spl(void) ret = pmc_init(pmc); if (ret < 0) return log_msg_ret("Could not init PMC", ret); -#ifdef CONFIG_HAVE_ACPI_RESUME - ret = pmc_prev_sleep_state(pmc); - if (ret < 0) - return log_msg_ret("Could not get PMC sleep state", ret); - gd->arch.prev_sleep_state = ret; -#endif + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + ret = pmc_prev_sleep_state(pmc); + if (ret < 0) + return log_msg_ret("Could not get PMC sleep state", + ret); + gd->arch.prev_sleep_state = ret; + } return 0; } diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index 1301100cd5..cef937573b 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -16,19 +16,29 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd) { struct fsp_m_config *cfg = &upd->config; struct fspm_arch_upd *arch = &upd->arch; + int cache_ret = 0; ofnode node; + int ret; arch->nvs_buffer_ptr = NULL; - prepare_mrc_cache(upd); - arch->stack_base = (void *)0xfef96000; + cache_ret = prepare_mrc_cache(upd); + if (cache_ret && cache_ret != -ENOENT) + return log_msg_ret("mrc", cache_ret); + arch->stack_base = (void *)(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - + arch->stack_size); arch->boot_loader_tolum_size = 0; - arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION; + arch->boot_mode = cache_ret ? FSP_BOOT_WITH_FULL_CONFIGURATION : + FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; node = dev_ofnode(dev); if (!ofnode_valid(node)) return log_msg_ret("fsp-m settings", -ENOENT); - return fsp_m_update_config_from_dtb(node, cfg); + ret = fsp_m_update_config_from_dtb(node, cfg); + if (ret) + return log_msg_ret("dtb", cache_ret); + + return cache_ret; } /* diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index 767ddfe680..e54b0ac104 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -12,6 +12,7 @@ #include <irq.h> #include <log.h> #include <malloc.h> +#include <p2sb.h> #include <acpi/acpi_s3.h> #include <asm/intel_pinctrl.h> #include <asm/io.h> @@ -21,10 +22,11 @@ #include <asm/pci.h> #include <asm/arch/cpu.h> #include <asm/arch/systemagent.h> +#include <asm/arch/fsp_bindings.h> #include <asm/arch/fsp/fsp_configs.h> #include <asm/arch/fsp/fsp_s_upd.h> +#include <dm/uclass-internal.h> #include <linux/bitops.h> -#include <asm/arch/fsp_bindings.h> #define PCH_P2SB_E0 0xe0 #define HIDE_BIT BIT(0) @@ -36,29 +38,20 @@ int fsps_update_config(struct udevice *dev, ulong rom_offset, ofnode node; if (IS_ENABLED(CONFIG_HAVE_VBT)) { - struct binman_entry vbt; - void *vbt_buf; + void *buf; int ret; - ret = binman_entry_find("intel-vbt", &vbt); + ret = binman_entry_map(ofnode_null(), "intel-vbt", &buf, NULL); if (ret) return log_msg_ret("Cannot find VBT", ret); - vbt.image_pos += rom_offset; - vbt_buf = malloc(vbt.size); - if (!vbt_buf) - return log_msg_ret("Alloc VBT", -ENOMEM); + if (*(u32 *)buf != VBT_SIGNATURE) + return log_msg_ret("VBT signature", -EINVAL); /* * Load VBT before devicetree-specific config. This only * supports memory-mapped SPI at present. */ - bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi"); - memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size); - bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI); - if (*(u32 *)vbt_buf != VBT_SIGNATURE) - return log_msg_ret("VBT signature", -EINVAL); - - cfg->graphics_config_ptr = (ulong)vbt_buf; + cfg->graphics_config_ptr = (ulong)buf; } node = dev_read_subnode(dev, "fsp-s"); @@ -68,12 +61,6 @@ int fsps_update_config(struct udevice *dev, ulong rom_offset, return fsp_s_update_config_from_dtb(node, cfg); } -static void p2sb_set_hide_bit(pci_dev_t dev, int hide) -{ - pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT, - hide ? HIDE_BIT : 0, PCI_SIZE_8); -} - /* Configure package power limits */ static int set_power_limits(struct udevice *dev) { @@ -146,15 +133,15 @@ static int set_power_limits(struct udevice *dev) int p2sb_unhide(void) { - pci_dev_t dev = PCI_BDF(0, 0xd, 0); - ulong val; - - p2sb_set_hide_bit(dev, 0); - - pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16); + struct udevice *dev; + int ret; - if (val != PCI_VENDOR_ID_INTEL) - return log_msg_ret("p2sb unhide", -EIO); + ret = uclass_find_first_device(UCLASS_P2SB, &dev); + if (ret) + return log_msg_ret("p2sb", ret); + ret = p2sb_set_hide(dev, false); + if (ret) + return log_msg_ret("hide", ret); return 0; } @@ -173,11 +160,6 @@ int arch_fsps_preinit(void) ret = irq_first_device_type(X86_IRQT_ITSS, &itss); if (ret) return log_msg_ret("no itss", ret); - /* - * Snapshot the current GPIO IRQ polarities. FSP is setting a default - * policy that doesn't honour boards' requirements - */ - irq_snapshot_polarities(itss); /* * Clear the GPI interrupt status and enable registers. These @@ -192,16 +174,16 @@ int arch_fsps_preinit(void) int arch_fsp_init_r(void) { -#ifdef CONFIG_HAVE_ACPI_RESUME - bool s3wake = gd->arch.prev_sleep_state == ACPI_S3; -#else - bool s3wake = false; -#endif + bool s3wake; struct udevice *dev, *itss; int ret; if (!ll_boot_init()) return 0; + + s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && + gd->arch.prev_sleep_state == ACPI_S3; + /* * This must be called before any devices are probed. Put any probing * into arch_fsps_preinit() above. @@ -216,7 +198,11 @@ int arch_fsp_init_r(void) ret = irq_first_device_type(X86_IRQT_ITSS, &itss); if (ret) return log_msg_ret("no itss", ret); - /* Restore GPIO IRQ polarities back to previous settings */ + + /* + * Restore GPIO IRQ polarities back to previous settings. This was + * stored in reserve_arch() - see X86_IRQT_ITSS + */ irq_restore_polarities(itss); /* soc_init() */ diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index 65f2006a0a..07757b88a3 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -139,7 +139,7 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, header->checksum = table_compute_checksum(fadt, header->length); } -void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +int acpi_create_gnvs(struct acpi_global_nvs *gnvs) { struct udevice *dev; int ret; @@ -159,9 +159,10 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs) gnvs->iuart_en = 1; else gnvs->iuart_en = 0; + + return 0; } -#ifdef CONFIG_HAVE_ACPI_RESUME /* * The following two routines are called at a very early stage, even before * FSP 2nd phase API fsp_init() is called. Registers off ACPI_BASE_ADDRESS @@ -204,4 +205,3 @@ void chipset_clear_sleep_state(void) pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); } -#endif diff --git a/arch/x86/cpu/broadwell/power_state.c b/arch/x86/cpu/broadwell/power_state.c index 99d6f72cf6..62fd2e8d2c 100644 --- a/arch/x86/cpu/broadwell/power_state.c +++ b/arch/x86/cpu/broadwell/power_state.c @@ -23,11 +23,10 @@ static int prev_sleep_state(struct chipset_power_state *ps) if (ps->pm1_sts & WAK_STS) { switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { -#if CONFIG_HAVE_ACPI_RESUME case SLP_TYP_S3: - prev_sleep_state = SLEEP_STATE_S3; + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + prev_sleep_state = SLEEP_STATE_S3; break; -#endif case SLP_TYP_S5: prev_sleep_state = SLEEP_STATE_S5; break; diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index d44db1347b..22a93254a9 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -42,7 +42,7 @@ int print_cpuinfo(void) return default_print_cpuinfo(); } -static void board_final_cleanup(void) +static void board_final_init(void) { /* * Un-cache the ROM so the kernel has one @@ -80,7 +80,7 @@ int last_stage_init(void) if (CONFIG_IS_ENABLED(USB_KEYBOARD)) usb_init(); - board_final_cleanup(); + board_final_init(); return 0; } diff --git a/arch/x86/cpu/coreboot/tables.c b/arch/x86/cpu/coreboot/tables.c index a5d31d1dea..1594b4a8b2 100644 --- a/arch/x86/cpu/coreboot/tables.c +++ b/arch/x86/cpu/coreboot/tables.c @@ -10,6 +10,8 @@ #include <net.h> #include <asm/arch/sysinfo.h> +DECLARE_GLOBAL_DATA_PTR; + /* * This needs to be in the .data section so that it's copied over during * relocation. By default it's put in the .bss section which is simply filled @@ -243,6 +245,10 @@ int get_coreboot_info(struct sysinfo_t *info) if (addr < 0) return addr; ret = cb_parse_header((void *)addr, 0x1000, info); + if (!ret) + return -ENOENT; + gd->arch.coreboot_table = addr; + gd->flags |= GD_FLG_SKIP_LL_INIT; - return ret == 1 ? 0 : -ENOENT; + return 0; } diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index a814e7d7a6..98ed66e67d 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -25,6 +25,7 @@ #include <dm.h> #include <errno.h> #include <init.h> +#include <irq.h> #include <log.h> #include <malloc.h> #include <syscon.h> @@ -163,10 +164,10 @@ int default_print_cpuinfo(void) cpu_has_64bit() ? "x86_64" : "x86", cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); -#ifdef CONFIG_HAVE_ACPI_RESUME - debug("ACPI previous sleep state: %s\n", - acpi_ss_string(gd->arch.prev_sleep_state)); -#endif + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + debug("ACPI previous sleep state: %s\n", + acpi_ss_string(gd->arch.prev_sleep_state)); + } return 0; } @@ -178,10 +179,10 @@ void show_boot_progress(int val) #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB) /* - * Implement a weak default function for boards that optionally - * need to clean up the system before jumping to the kernel. + * Implement a weak default function for boards that need to do some final init + * before the system is ready. */ -__weak void board_final_cleanup(void) +__weak void board_final_init(void) { } @@ -189,14 +190,14 @@ int last_stage_init(void) { struct acpi_fadt __maybe_unused *fadt; - board_final_cleanup(); + board_final_init(); -#ifdef CONFIG_HAVE_ACPI_RESUME - fadt = acpi_find_fadt(); + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + fadt = acpi_find_fadt(); - if (fadt && gd->arch.prev_sleep_state == ACPI_S3) - acpi_resume(fadt); -#endif + if (fadt && gd->arch.prev_sleep_state == ACPI_S3) + acpi_resume(fadt); + } write_tables(); @@ -269,25 +270,36 @@ int cpu_init_r(void) #ifndef CONFIG_EFI_STUB int reserve_arch(void) { -#ifdef CONFIG_ENABLE_MRC_CACHE - mrccache_reserve(); -#endif + struct udevice *itss; + int ret; + + if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) + mrccache_reserve(); #ifdef CONFIG_SEABIOS high_table_reserve(); #endif -#ifdef CONFIG_HAVE_ACPI_RESUME - acpi_s3_reserve(); + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + acpi_s3_reserve(); -#ifdef CONFIG_HAVE_FSP - /* - * Save stack address to CMOS so that at next S3 boot, - * we can use it as the stack address for fsp_contiue() - */ - fsp_save_s3_stack(); -#endif /* CONFIG_HAVE_FSP */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ + if (IS_ENABLED(CONFIG_HAVE_FSP)) { + /* + * Save stack address to CMOS so that at next S3 boot, + * we can use it as the stack address for fsp_contiue() + */ + fsp_save_s3_stack(); + } + } + ret = irq_first_device_type(X86_IRQT_ITSS, &itss); + if (!ret) { + /* + * Snapshot the current GPIO IRQ polarities. FSP-S is about to + * run and will set a default policy that doesn't honour boards' + * requirements + */ + irq_snapshot_polarities(itss); + } return 0; } diff --git a/arch/x86/cpu/efi/app.c b/arch/x86/cpu/efi/app.c index 10677ecbc2..f754489784 100644 --- a/arch/x86/cpu/efi/app.c +++ b/arch/x86/cpu/efi/app.c @@ -24,7 +24,7 @@ int print_cpuinfo(void) return default_print_cpuinfo(); } -void board_final_cleanup(void) +void board_final_init(void) { } diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index d27324cb4e..a6a6afec8c 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -455,10 +455,15 @@ int x86_cpu_init_f(void) int x86_cpu_reinit_f(void) { + long addr; + setup_identity(); setup_pci_ram_top(); - if (locate_coreboot_table() >= 0) + addr = locate_coreboot_table(); + if (addr >= 0) { + gd->arch.coreboot_table = addr; gd->flags |= GD_FLG_SKIP_LL_INIT; + } return 0; } diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c index 963afa8f5b..fe84ebe29f 100644 --- a/arch/x86/cpu/intel_common/itss.c +++ b/arch/x86/cpu/intel_common/itss.c @@ -65,14 +65,23 @@ static int snapshot_polarities(struct udevice *dev) int i; reg_start = start / IRQS_PER_IPC; - reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC; + reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC); + log_info("ITSS IRQ Polarities snapshot %p\n", priv->irq_snapshot); for (i = reg_start; i < reg_end; i++) { uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i; priv->irq_snapshot[i] = pcr_read32(dev, reg); + log_debug(" - %d, reg %x: irq_snapshot[i] %x\n", i, reg, + priv->irq_snapshot[i]); } + /* Save the snapshot for use after relocation */ + gd->start_addr_sp -= sizeof(*priv); + gd->start_addr_sp &= ~0xf; + gd->arch.itss_priv = (void *)gd->start_addr_sp; + memcpy(gd->arch.itss_priv, priv, sizeof(*priv)); + return 0; } @@ -91,16 +100,26 @@ static void show_polarities(struct udevice *dev, const char *msg) static int restore_polarities(struct udevice *dev) { struct itss_priv *priv = dev_get_priv(dev); + struct itss_priv *old_priv; const int start = GPIO_IRQ_START; const int end = GPIO_IRQ_END; int reg_start; int reg_end; int i; + /* Get the snapshot which was stored by the pre-reloc device */ + old_priv = gd->arch.itss_priv; + if (!old_priv) + return log_msg_ret("priv", -EFAULT); + memcpy(priv->irq_snapshot, old_priv->irq_snapshot, + sizeof(priv->irq_snapshot)); + show_polarities(dev, "Before"); + log_info("priv->irq_snapshot %p\n", priv->irq_snapshot); reg_start = start / IRQS_PER_IPC; - reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC; + reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC); + for (i = reg_start; i < reg_end; i++) { u32 mask; @@ -125,6 +144,8 @@ static int restore_polarities(struct udevice *dev) mask &= ~((1U << irq_start) - 1); reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i; + log_debug(" - %d, reg %x: mask %x, irq_snapshot[i] %x\n", + i, reg, mask, priv->irq_snapshot[i]); pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]); } diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c index ec35d04ae5..361d4c90cb 100644 --- a/arch/x86/cpu/intel_common/p2sb.c +++ b/arch/x86/cpu/intel_common/p2sb.c @@ -16,6 +16,9 @@ #include <asm/pci.h> #include <linux/bitops.h> +#define PCH_P2SB_E0 0xe0 +#define HIDE_BIT BIT(0) + struct p2sb_platdata { #if CONFIG_IS_ENABLED(OF_PLATDATA) struct dtd_intel_p2sb dtplat; @@ -127,6 +130,40 @@ static int p2sb_probe(struct udevice *dev) return 0; } +static void p2sb_set_hide_bit(struct udevice *dev, bool hide) +{ + dm_pci_clrset_config8(dev, PCH_P2SB_E0 + 1, HIDE_BIT, + hide ? HIDE_BIT : 0); +} + +static int intel_p2sb_set_hide(struct udevice *dev, bool hide) +{ + u16 vendor; + + if (!CONFIG_IS_ENABLED(PCI)) + return -EPERM; + p2sb_set_hide_bit(dev, hide); + + dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor); + if (hide && vendor != 0xffff) + return log_msg_ret("hide", -EEXIST); + else if (!hide && vendor != PCI_VENDOR_ID_INTEL) + return log_msg_ret("unhide", -ENOMEDIUM); + + return 0; +} + +static int p2sb_remove(struct udevice *dev) +{ + int ret; + + ret = intel_p2sb_set_hide(dev, true); + if (ret) + return log_msg_ret("hide", ret); + + return 0; +} + static int p2sb_child_post_bind(struct udevice *dev) { #if !CONFIG_IS_ENABLED(OF_PLATDATA) @@ -143,6 +180,10 @@ static int p2sb_child_post_bind(struct udevice *dev) return 0; } +struct p2sb_ops p2sb_ops = { + .set_hide = intel_p2sb_set_hide, +}; + static const struct udevice_id p2sb_ids[] = { { .compatible = "intel,p2sb" }, { } @@ -153,9 +194,12 @@ U_BOOT_DRIVER(p2sb_drv) = { .id = UCLASS_P2SB, .of_match = p2sb_ids, .probe = p2sb_probe, + .remove = p2sb_remove, + .ops = &p2sb_ops, .ofdata_to_platdata = p2sb_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct p2sb_platdata), .per_child_platdata_auto_alloc_size = sizeof(struct p2sb_child_platdata), .child_post_bind = p2sb_child_post_bind, + .flags = DM_FLAG_OS_PREPARE, }; diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 26cda3b337..b0406a04e9 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -133,8 +133,10 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, header->checksum = table_compute_checksum(fadt, header->length); } -void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +int acpi_create_gnvs(struct acpi_global_nvs *gnvs) { /* quark is a uni-processor */ gnvs->pcnt = 1; + + return 0; } diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index ddad02e375..30b4711b9a 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -363,7 +363,7 @@ int arch_misc_init(void) return 0; } -void board_final_cleanup(void) +void board_final_init(void) { struct quark_rcba *rcba; u32 base, val; diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 01524635e9..4ad515ce08 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -124,6 +124,7 @@ car_init_ret: #endif #else /* + * Instructions for FSP1, but not FSP2: * U-Boot enters here twice. For the first time it comes from * car_init_done() with esp points to a temporary stack and esi * set to zero. For the second time it comes from fsp_init_done() diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 4ec8fdd6f8..41bd177e09 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -107,7 +107,7 @@ u32 acpi_fill_csrt(u32 current) return current; } -void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +int acpi_create_gnvs(struct acpi_global_nvs *gnvs) { struct udevice *dev; int ret; @@ -122,4 +122,6 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs) if (ret > 0) gnvs->pcnt = ret; } + + return 0; } diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 965d9f387d..a17a9c2800 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -117,6 +117,7 @@ reg = <0x00000000 0 0 0 0>; compatible = "intel,apl-hostbridge"; pciex-region-size = <0x10000000>; + fspm,training-delay = <21>; /* * Parameters used by the FSP-S binary blob. This is * really unfortunate since these parameters mostly diff --git a/arch/x86/include/asm/acpi_nhlt.h b/arch/x86/include/asm/acpi_nhlt.h new file mode 100644 index 0000000000..4720321381 --- /dev/null +++ b/arch/x86/include/asm/acpi_nhlt.h @@ -0,0 +1,314 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Google LLC + * + * Modified from coreboot nhlt.h + */ + +#ifndef _NHLT_H_ +#define _NHLT_H_ + +struct acpi_ctx; +struct nhlt; +struct nhlt_endpoint; +struct nhlt_format; +struct nhlt_format_config; + +/* + * Non HD Audio ACPI support. This table is typically used for Intel Smart + * Sound Technology DSP. It provides a way to encode opaque settings in + * the ACPI tables. + * + * While the structure fields of the NHLT structs are exposed below + * the SoC/chipset code should be the only other user manipulating the + * fields directly aside from the library itself. + * + * The NHLT table consists of endpoints which in turn contain different + * supporting stream formats. Each endpoint may contain a device specific + * configuration payload as well as each stream format. + * + * Most code should use the SoC variants of the functions because + * there is required logic needed to be performed by the SoC. The SoC + * code should be abstracting the inner details of these functions that + * specically apply to NHLT objects for that SoC. + * + * An example sequence: + * + * nhlt = nhlt_init() + * ep = nhlt_add_endpoint() + * nhlt_endpoint_append_config(ep) + * nhlt_endpoint_add_formats(ep) + * nhlt_soc_serialise() + */ + +/* Obtain an nhlt object for adding endpoints. Returns NULL on error. */ +struct nhlt *nhlt_init(void); + +/* Return the size of the NHLT table including ACPI header. */ +size_t nhlt_current_size(struct nhlt *nhlt); + +/* + * Helper functions for adding NHLT devices utilizing an nhlt_endp_descriptor + * to drive the logic. + */ + +struct nhlt_endp_descriptor { + /* NHLT endpoint types. */ + int link; + int device; + int direction; + u16 vid; + u16 did; + /* Optional endpoint specific configuration data. */ + const void *cfg; + size_t cfg_size; + /* Formats supported for endpoint. */ + const struct nhlt_format_config *formats; + size_t num_formats; +}; + +/* + * Add the number of endpoints described by each descriptor. The virtual bus + * id for each descriptor is the default value of 0. + * Returns < 0 on error, 0 on success. + */ +int nhlt_add_endpoints(struct nhlt *nhlt, + const struct nhlt_endp_descriptor *epds, + size_t num_epds); + +/* + * Add the number of endpoints associated with a single NHLT SSP instance id. + * Each endpoint described in the endpoint descriptor array uses the provided + * virtual bus id. Returns < 0 on error, 0 on success. + */ +int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id, + const struct nhlt_endp_descriptor *epds, + size_t num_epds); + +/* + * Add endpoint to NHLT object. Returns NULL on error. + * + * generic nhlt_add_endpoint() is called by the SoC code to provide + * the specific assumptions/uses for NHLT for that platform. All fields + * are the NHLT enumerations found within this header file. + */ +struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type, + int device_type, int dir, + u16 vid, u16 did); + +/* + * Append blob of configuration to the endpoint proper. Returns 0 on + * success, < 0 on error. A copy of the configuration is made so any + * resources pointed to by config can be freed after the call. + */ +int nhlt_endpoint_append_config(struct nhlt_endpoint *endpoint, + const void *config, size_t config_sz); + +/* Add a format type to the provided endpoint. Returns NULL on error. */ +struct nhlt_format *nhlt_add_format(struct nhlt_endpoint *endpoint, + int num_channels, int sample_freq_khz, + int container_bits_per_sample, + int valid_bits_per_sample, + u32 speaker_mask); + +/* + * Append blob of configuration to the format proper. Returns 0 on + * success, < 0 on error. A copy of the configuration is made so any + * resources pointed to by config can be freed after the call. + */ +int nhlt_format_append_config(struct nhlt_format *format, const void *config, + size_t config_sz); + +/* + * Add num_formats described by formats to the endpoint. This function + * effectively wraps nhlt_add_format() and nhlt_format_config() using the + * data found in each nhlt_format_config object. Returns 0 on success, < 0 + * on error. + */ +int nhlt_endpoint_add_formats(struct nhlt_endpoint *endpoint, + const struct nhlt_format_config *formats, + size_t num_formats); + +/* + * Increment the instance id for a given link type. This function is + * used for marking a device being completely added to the NHLT object. + * Subsequent endpoints added to the nhlt object with the same link type + * will use incremented instance id. + */ +void nhlt_next_instance(struct nhlt *nhlt, int link_type); + +/* + * Serialize NHLT object to ACPI table. Take in the beginning address of where + * the table will reside and return the address of the next ACPI table. On + * error 0 will be returned. The NHLT object is no longer valid after this + * function is called. + */ +uintptr_t nhlt_serialise(struct nhlt *nhlt, uintptr_t acpi_addr); + +/* + * Serialize NHLT object to ACPI table. Take in the beginning address of where + * the table will reside oem_id and oem_table_id and return the address of the + * next ACPI table. On error 0 will be returned. The NHLT object is no longer + * valid after this function is called. + */ +int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt, + const char *oem_id, const char *oem_table_id, + u32 oem_revision); + +int nhlt_setup(struct nhlt *nhlt, ofnode node); + +/* Link and device types. */ +enum { + NHLT_LINK_HDA, + NHLT_LINK_DSP, + NHLT_LINK_PDM, + NHLT_LINK_SSP, + NHLT_MAX_LINK_TYPES, +}; + +enum { + NHLT_SSP_DEV_BT, /* Bluetooth */ + NHLT_SSP_DEV_MODEM, + NHLT_SSP_DEV_FM, + NHLT_SSP_DEV_RESERVED, + NHLT_SSP_DEV_I2S = 4, +}; + +enum { + NHLT_PDM_DEV, +}; + +/* Endpoint direction. */ +enum { + NHLT_DIR_RENDER, + NHLT_DIR_CAPTURE, + NHLT_DIR_BIDIRECTIONAL, +}; + +/* + * Channel mask for an endpoint. While they are prefixed with 'SPEAKER' the + * channel masks are also used for capture devices + */ +enum { + SPEAKER_FRONT_LEFT = BIT(0), + SPEAKER_FRONT_RIGHT = BIT(1), + SPEAKER_FRONT_CENTER = BIT(2), + SPEAKER_LOW_FREQUENCY = BIT(3), + SPEAKER_BACK_LEFT = BIT(4), + SPEAKER_BACK_RIGHT = BIT(5), + SPEAKER_FRONT_LEFT_OF_CENTER = BIT(6), + SPEAKER_FRONT_RIGHT_OF_CENTER = BIT(7), + SPEAKER_BACK_CENTER = BIT(8), + SPEAKER_SIDE_LEFT = BIT(9), + SPEAKER_SIDE_RIGHT = BIT(10), + SPEAKER_TOP_CENTER = BIT(11), + SPEAKER_TOP_FRONT_LEFT = BIT(12), + SPEAKER_TOP_FRONT_CENTER = BIT(13), + SPEAKER_TOP_FRONT_RIGHT = BIT(14), + SPEAKER_TOP_BACK_LEFT = BIT(15), + SPEAKER_TOP_BACK_CENTER = BIT(16), + SPEAKER_TOP_BACK_RIGHT = BIT(17), +}; + +/* + * Supporting structures. Only SoC/chipset and the library code directly should + * be manipulating these structures + */ +struct sub_format { + u32 data1; + u16 data2; + u16 data3; + u8 data4[8]; +}; + +struct nhlt_specific_config { + u32 size; + void *capabilities; +}; + +struct nhlt_waveform { + u16 tag; + u16 num_channels; + u32 samples_per_second; + u32 bytes_per_second; + u16 block_align; + u16 bits_per_sample; + u16 extra_size; + u16 valid_bits_per_sample; + u32 channel_mask; + struct sub_format sub_format; +}; + +struct nhlt_format { + struct nhlt_waveform waveform; + struct nhlt_specific_config config; +}; + +/* + * This struct is used by nhlt_endpoint_add_formats() for easily adding + * waveform formats with associated settings file. + */ +struct nhlt_format_config { + int num_channels; + int sample_freq_khz; + int container_bits_per_sample; + int valid_bits_per_sample; + u32 speaker_mask; + const char *settings_file; +}; + +/* Arbitrary max number of formats per endpoint. */ +#define MAX_FORMATS 2 +struct nhlt_endpoint { + u32 length; + u8 link_type; + u8 instance_id; + u16 vendor_id; + u16 device_id; + u16 revision_id; + u32 subsystem_id; + u8 device_type; + u8 direction; + u8 virtual_bus_id; + struct nhlt_specific_config config; + u8 num_formats; + struct nhlt_format formats[MAX_FORMATS]; +}; + +#define MAX_ENDPOINTS 8 +struct nhlt { + u32 subsystem_id; + u8 num_endpoints; + struct nhlt_endpoint endpoints[MAX_ENDPOINTS]; + u8 current_instance_id[NHLT_MAX_LINK_TYPES]; +}; + +struct nhlt_tdm_config { + u8 virtual_slot; + u8 config_type; +}; + +enum { + NHLT_TDM_BASIC, + NHLT_TDM_MIC_ARRAY, +}; + +struct nhlt_dmic_array_config { + struct nhlt_tdm_config tdm_config; + u8 array_type; +}; + +/* + * Microphone array definitions may be found here: + * https://msdn.microsoft.com/en-us/library/windows/hardware/dn613960%28v=vs.85%29.aspx + */ +enum { + NHLT_MIC_ARRAY_2CH_SMALL = 0xa, + NHLT_MIC_ARRAY_2CH_BIG = 0xb, + NHLT_MIC_ARRAY_4CH_1ST_GEOM = 0xc, + NHLT_MIC_ARRAY_4CH_L_SHAPED = 0xd, + NHLT_MIC_ARRAY_4CH_2ND_GEOM = 0xe, + NHLT_MIC_ARRAY_VENDOR_DEFINED = 0xf, +}; + +#endif diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 928475cef4..733085c178 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -35,7 +35,15 @@ int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end); u32 acpi_fill_mcfg(u32 current); u32 acpi_fill_csrt(u32 current); -void acpi_create_gnvs(struct acpi_global_nvs *gnvs); + +/** + * acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table + * + * @gnvs: Table to fill in + * @return 0 if OK, -ve on error + */ +int acpi_create_gnvs(struct acpi_global_nvs *gnvs); + ulong write_acpi_tables(ulong start); /** diff --git a/arch/x86/include/asm/fsp2/fsp_internal.h b/arch/x86/include/asm/fsp2/fsp_internal.h index f751fbf961..b4a4fbbd84 100644 --- a/arch/x86/include/asm/fsp2/fsp_internal.h +++ b/arch/x86/include/asm/fsp2/fsp_internal.h @@ -57,7 +57,8 @@ int arch_fsps_preinit(void); * * @dev: Hostbridge device containing config * @upd: Config data to fill in - * @return 0 if OK, -ve on error + * @return 0 if OK, -ENOENT if OK but no MRC-cache data was found, other -ve on + * error */ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd); diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 4aee2f3e8c..3e4044593c 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -116,14 +116,14 @@ struct arch_global_data { u32 high_table_ptr; u32 high_table_limit; #endif -#ifdef CONFIG_HAVE_ACPI_RESUME int prev_sleep_state; /* Previous sleep state ACPI_S0/1../5 */ ulong backup_mem; /* Backup memory address for S3 */ -#endif #ifdef CONFIG_FSP_VERSION2 struct fsp_header *fsp_s_hdr; /* Pointer to FSP-S header */ #endif + void *itss_priv; /* Private ITSS data pointer */ ulong acpi_start; /* Start address of ACPI tables */ + ulong coreboot_table; /* Address of coreboot table */ }; #endif diff --git a/arch/x86/include/asm/intel_pinctrl.h b/arch/x86/include/asm/intel_pinctrl.h index e2524b089d..00868d1725 100644 --- a/arch/x86/include/asm/intel_pinctrl.h +++ b/arch/x86/include/asm/intel_pinctrl.h @@ -99,7 +99,6 @@ struct pad_group { * groups exist inside a community * * @name: Community name - * @acpi_path: ACPI path * @num_gpi_regs: number of gpi registers in community * @max_pads_per_group: number of pads in each group; number of pads bit-mapped * in each GPI status/en and Host Own Reg @@ -120,7 +119,6 @@ struct pad_group { */ struct pad_community { const char *name; - const char *acpi_path; size_t num_gpi_regs; size_t max_pads_per_group; uint first_pad; @@ -263,11 +261,23 @@ int pinctrl_read_pads(struct udevice *dev, ofnode node, const char *prop, int pinctrl_count_pads(struct udevice *dev, u32 *pads, int size); /** - * intel_pinctrl_get_config_reg_addr() - Get address of the pin config registers + * intel_pinctrl_get_config_reg_offset() - Get offset of pin config registers * + * This works out the register offset of a pin within the p2sb region. + * + * @dev: Pinctrl device + * @offset: GPIO offset within this device + * @return register offset of first register within the GPIO p2sb region + */ +u32 intel_pinctrl_get_config_reg_offset(struct udevice *dev, uint offset); + +/** + * intel_pinctrl_get_config_reg_addr() - Get address of pin config registers + * + * This works out the absolute address of the registers for a pin * @dev: Pinctrl device * @offset: GPIO offset within this device - * @return register offset within the GPIO p2sb region + * @return register address of first register within the GPIO p2sb region */ u32 intel_pinctrl_get_config_reg_addr(struct udevice *dev, uint offset); @@ -288,6 +298,7 @@ u32 intel_pinctrl_get_config_reg(struct udevice *dev, uint offset); * @pad: Pad to check * @devp: Returns pinctrl device containing that pad * @offsetp: Returns offset of pad within that pinctrl device + * @return 0 if OK, -ENOTBLK if pad number is invalid */ int intel_pinctrl_get_pad(uint pad, struct udevice **devp, uint *offsetp); diff --git a/arch/x86/include/asm/itss.h b/arch/x86/include/asm/itss.h index c75d8fe8c2..f7d3240384 100644 --- a/arch/x86/include/asm/itss.h +++ b/arch/x86/include/asm/itss.h @@ -16,7 +16,7 @@ #define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 -#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1) / IRQS_PER_IPC) +#define NUM_IPC_REGS DIV_ROUND_UP(ITSS_MAX_IRQ, IRQS_PER_IPC) /* Max PXRC registers in ITSS */ #define MAX_PXRC_CONFIG (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1) diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index bd3f44014c..d732661f6d 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -83,8 +83,6 @@ int default_print_cpuinfo(void); /* Set up a UART which can be used with printch(), printhex8(), etc. */ int setup_internal_uart(int enable); -void setup_pcat_compatibility(void); - void isa_unmap_rom(u32 addr); u32 isa_map_rom(u32 bus_addr, int size); diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 1079bf2022..1185a88c27 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -22,6 +22,7 @@ obj-y += init_helpers.o obj-y += interrupts.o obj-y += lpc-uclass.o obj-y += mpspec.o +obj-$(CONFIG_$(SPL_TPL_)ACPIGEN) += acpi_nhlt.o obj-y += northbridge-uclass.o obj-$(CONFIG_I8259_PIC) += i8259.o obj-$(CONFIG_I8254_TIMER) += i8254.o diff --git a/arch/x86/lib/acpi_nhlt.c b/arch/x86/lib/acpi_nhlt.c new file mode 100644 index 0000000000..c64dd9c008 --- /dev/null +++ b/arch/x86/lib/acpi_nhlt.c @@ -0,0 +1,482 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Google LLC + * + * Modified from coreboot nhlt.c + */ + +#define LOG_CATEGORY LOGC_ACPI + +#include <common.h> +#include <binman.h> +#include <dm.h> +#include <log.h> +#include <malloc.h> +#include <tables_csum.h> +#include <acpi/acpi_table.h> +#include <asm/acpi_nhlt.h> +#include <asm/unaligned.h> +#include <dm/acpi.h> + +#define NHLT_RID 1 +#define NHLT_SSID 1 +#define WAVEFORMAT_TAG 0xfffe +#define DEFAULT_VIRTUAL_BUS_ID 0 + +static const struct sub_format pcm_subformat = { + .data1 = 0x00000001, + .data2 = 0x0000, + .data3 = 0x0010, + .data4 = { 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71 }, +}; + +struct nhlt *nhlt_init(void) +{ + struct nhlt *nhlt; + + nhlt = malloc(sizeof(*nhlt)); + + if (!nhlt) + return NULL; + + memset(nhlt, 0, sizeof(*nhlt)); + nhlt->subsystem_id = NHLT_SSID; + + return nhlt; +} + +struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type, + int device_type, int dir, + u16 vid, u16 did) +{ + struct nhlt_endpoint *endp; + + if (link_type < NHLT_LINK_HDA || link_type >= NHLT_MAX_LINK_TYPES) + return NULL; + + if (nhlt->num_endpoints >= MAX_ENDPOINTS) + return NULL; + + endp = &nhlt->endpoints[nhlt->num_endpoints]; + + endp->link_type = link_type; + endp->instance_id = nhlt->current_instance_id[link_type]; + endp->vendor_id = vid; + endp->device_id = did; + endp->revision_id = NHLT_RID; + endp->subsystem_id = nhlt->subsystem_id; + endp->device_type = device_type; + endp->direction = dir; + endp->virtual_bus_id = DEFAULT_VIRTUAL_BUS_ID; + + nhlt->num_endpoints++; + + return endp; +} + +static int append_specific_config(struct nhlt_specific_config *spec_cfg, + const void *config, size_t config_sz) +{ + size_t new_sz; + void *new_cfg; + + new_sz = spec_cfg->size + config_sz; + new_cfg = malloc(new_sz); + if (!new_cfg) + return -ENOMEM; + + /* Append new config */ + memcpy(new_cfg, spec_cfg->capabilities, spec_cfg->size); + memcpy(new_cfg + spec_cfg->size, config, config_sz); + + free(spec_cfg->capabilities); + + /* Update with new config data */ + spec_cfg->size = new_sz; + spec_cfg->capabilities = new_cfg; + + return 0; +} + +int nhlt_endpoint_append_config(struct nhlt_endpoint *endp, const void *config, + size_t config_sz) +{ + return append_specific_config(&endp->config, config, config_sz); +} + +struct nhlt_format *nhlt_add_format(struct nhlt_endpoint *endp, + int num_channels, int sample_freq_khz, + int container_bits_per_sample, + int valid_bits_per_sample, + uint32_t speaker_mask) +{ + struct nhlt_format *fmt; + struct nhlt_waveform *wave; + + if (endp->num_formats >= MAX_FORMATS) + return NULL; + + fmt = &endp->formats[endp->num_formats]; + wave = &fmt->waveform; + + wave->tag = WAVEFORMAT_TAG; + wave->num_channels = num_channels; + wave->samples_per_second = sample_freq_khz * 1000; + wave->bits_per_sample = container_bits_per_sample; + wave->extra_size = sizeof(wave->valid_bits_per_sample); + wave->extra_size += sizeof(wave->channel_mask); + wave->extra_size += sizeof(wave->sub_format); + wave->valid_bits_per_sample = valid_bits_per_sample; + wave->channel_mask = speaker_mask; + memcpy(&wave->sub_format, &pcm_subformat, sizeof(wave->sub_format)); + + /* Calculate the dervied fields */ + wave->block_align = wave->num_channels * wave->bits_per_sample / 8; + wave->bytes_per_second = wave->block_align * wave->samples_per_second; + + endp->num_formats++; + + return fmt; +} + +int nhlt_format_append_config(struct nhlt_format *fmt, const void *config, + size_t config_sz) +{ + return append_specific_config(&fmt->config, config, config_sz); +} + +int nhlt_endpoint_add_formats(struct nhlt_endpoint *endp, + const struct nhlt_format_config *formats, + size_t num_formats) +{ + ofnode node; + size_t i; + + node = binman_section_find_node("private-files"); + + for (i = 0; i < num_formats; i++) { + const struct nhlt_format_config *cfg = &formats[i]; + struct nhlt_format *fmt; + void *data; + int size; + int ret; + + fmt = nhlt_add_format(endp, cfg->num_channels, + cfg->sample_freq_khz, + cfg->container_bits_per_sample, + cfg->valid_bits_per_sample, + cfg->speaker_mask); + if (!fmt) + return -ENOSPC; + + if (!cfg->settings_file) + continue; + + ret = binman_entry_map(node, cfg->settings_file, &data, &size); + if (ret) { + log_warning("Failed to find settings file %s\n", + cfg->settings_file); + return log_msg_ret("settings", ret); + } + + ret = nhlt_format_append_config(fmt, data, size); + if (ret) + return log_msg_ret("append", ret); + } + + return 0; +} + +void nhlt_next_instance(struct nhlt *nhlt, int link_type) +{ + if (link_type < NHLT_LINK_HDA || link_type >= NHLT_MAX_LINK_TYPES) + return; + + nhlt->current_instance_id[link_type]++; +} + +static size_t calc_specific_config_size(struct nhlt_specific_config *cfg) +{ + return sizeof(cfg->size) + cfg->size; +} + +static size_t calc_format_size(struct nhlt_format *fmt) +{ + size_t sz = 0; + + /* Wave format first */ + sz += sizeof(fmt->waveform.tag); + sz += sizeof(fmt->waveform.num_channels); + sz += sizeof(fmt->waveform.samples_per_second); + sz += sizeof(fmt->waveform.bytes_per_second); + sz += sizeof(fmt->waveform.block_align); + sz += sizeof(fmt->waveform.bits_per_sample); + sz += sizeof(fmt->waveform.extra_size); + sz += sizeof(fmt->waveform.valid_bits_per_sample); + sz += sizeof(fmt->waveform.channel_mask); + sz += sizeof(fmt->waveform.sub_format); + + sz += calc_specific_config_size(&fmt->config); + + return sz; +} + +static size_t calc_endpoint_size(struct nhlt_endpoint *endp) +{ + int i; + size_t sz = 0; + + sz += sizeof(endp->length) + sizeof(endp->link_type); + sz += sizeof(endp->instance_id) + sizeof(endp->vendor_id); + sz += sizeof(endp->device_id) + sizeof(endp->revision_id); + sz += sizeof(endp->subsystem_id) + sizeof(endp->device_type); + sz += sizeof(endp->direction) + sizeof(endp->virtual_bus_id); + sz += calc_specific_config_size(&endp->config); + sz += sizeof(endp->num_formats); + + for (i = 0; i < endp->num_formats; i++) + sz += calc_format_size(&endp->formats[i]); + + /* Adjust endpoint length to reflect current configuration */ + endp->length = sz; + + return sz; +} + +static size_t calc_endpoints_size(struct nhlt *nhlt) +{ + size_t sz = 0; + int i; + + for (i = 0; i < nhlt->num_endpoints; i++) + sz += calc_endpoint_size(&nhlt->endpoints[i]); + + return sz; +} + +static size_t calc_size(struct nhlt *nhlt) +{ + return sizeof(nhlt->num_endpoints) + calc_endpoints_size(nhlt); +} + +size_t nhlt_current_size(struct nhlt *nhlt) +{ + return calc_size(nhlt) + sizeof(struct acpi_table_header); +} + +static void nhlt_free_resources(struct nhlt *nhlt) +{ + int i, j; + + /* Free all specific configs */ + for (i = 0; i < nhlt->num_endpoints; i++) { + struct nhlt_endpoint *endp = &nhlt->endpoints[i]; + + free(endp->config.capabilities); + for (j = 0; j < endp->num_formats; j++) { + struct nhlt_format *fmt = &endp->formats[j]; + + free(fmt->config.capabilities); + } + } + + /* Free nhlt object proper */ + free(nhlt); +} + +struct cursor { + u8 *buf; +}; + +static void ser8(struct cursor *cur, uint val) +{ + *cur->buf = val; + cur->buf += sizeof(val); +} + +static void ser16(struct cursor *cur, uint val) +{ + put_unaligned_le16(val, cur->buf); + cur->buf += sizeof(val); +} + +static void ser32(struct cursor *cur, uint val) +{ + put_unaligned_le32(val, cur->buf); + cur->buf += sizeof(val); +} + +static void serblob(struct cursor *cur, void *from, size_t sz) +{ + memcpy(cur->buf, from, sz); + cur->buf += sz; +} + +static void serialise_specific_config(struct nhlt_specific_config *cfg, + struct cursor *cur) +{ + ser32(cur, cfg->size); + serblob(cur, cfg->capabilities, cfg->size); +} + +static void serialise_waveform(struct nhlt_waveform *wave, struct cursor *cur) +{ + ser16(cur, wave->tag); + ser16(cur, wave->num_channels); + ser32(cur, wave->samples_per_second); + ser32(cur, wave->bytes_per_second); + ser16(cur, wave->block_align); + ser16(cur, wave->bits_per_sample); + ser16(cur, wave->extra_size); + ser16(cur, wave->valid_bits_per_sample); + ser32(cur, wave->channel_mask); + ser32(cur, wave->sub_format.data1); + ser16(cur, wave->sub_format.data2); + ser16(cur, wave->sub_format.data3); + serblob(cur, wave->sub_format.data4, sizeof(wave->sub_format.data4)); +} + +static void serialise_format(struct nhlt_format *fmt, struct cursor *cur) +{ + serialise_waveform(&fmt->waveform, cur); + serialise_specific_config(&fmt->config, cur); +} + +static void serialise_endpoint(struct nhlt_endpoint *endp, struct cursor *cur) +{ + int i; + + ser32(cur, endp->length); + ser8(cur, endp->link_type); + ser8(cur, endp->instance_id); + ser16(cur, endp->vendor_id); + ser16(cur, endp->device_id); + ser16(cur, endp->revision_id); + ser32(cur, endp->subsystem_id); + ser8(cur, endp->device_type); + ser8(cur, endp->direction); + ser8(cur, endp->virtual_bus_id); + serialise_specific_config(&endp->config, cur); + ser8(cur, endp->num_formats); + + for (i = 0; i < endp->num_formats; i++) + serialise_format(&endp->formats[i], cur); +} + +static void nhlt_serialise_endpoints(struct nhlt *nhlt, struct cursor *cur) +{ + int i; + + ser8(cur, nhlt->num_endpoints); + + for (i = 0; i < nhlt->num_endpoints; i++) + serialise_endpoint(&nhlt->endpoints[i], cur); +} + +int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt, + const char *oem_id, const char *oem_table_id, + uint32_t oem_revision) +{ + struct cursor cur; + struct acpi_table_header *header; + size_t sz; + size_t oem_id_len; + size_t oem_table_id_len; + int ret; + + log_info("ACPI: * NHLT\n"); + sz = nhlt_current_size(nhlt); + + /* Create header */ + header = (void *)ctx->current; + memset(header, '\0', sizeof(struct acpi_table_header)); + acpi_fill_header(header, "NHLT"); + header->length = sz; + header->revision = acpi_get_table_revision(ACPITAB_NHLT); + + if (oem_id) { + oem_id_len = min((int)strlen(oem_id), 6); + memcpy(header->oem_id, oem_id, oem_id_len); + } + if (oem_table_id) { + oem_table_id_len = min((int)strlen(oem_table_id), 8); + memcpy(header->oem_table_id, oem_table_id, oem_table_id_len); + } + header->oem_revision = oem_revision; + + cur.buf = (void *)(header + 1); + nhlt_serialise_endpoints(nhlt, &cur); + + header->checksum = table_compute_checksum(header, sz); + nhlt_free_resources(nhlt); + + ret = acpi_add_table(ctx, ctx->current); + if (ret) + return log_msg_ret("add", ret); + acpi_inc_align(ctx, sz); + + return 0; +} + +static int _nhlt_add_single_endpoint(struct nhlt *nhlt, int virtual_bus_id, + const struct nhlt_endp_descriptor *epd) +{ + struct nhlt_endpoint *endp; + int ret; + + endp = nhlt_add_endpoint(nhlt, epd->link, epd->device, epd->direction, + epd->vid, epd->did); + if (!endp) + return -EINVAL; + + endp->virtual_bus_id = virtual_bus_id; + + ret = nhlt_endpoint_append_config(endp, epd->cfg, epd->cfg_size); + if (ret) + return ret; + + ret = nhlt_endpoint_add_formats(endp, epd->formats, epd->num_formats); + if (ret) + return log_msg_ret("formats", ret); + + return 0; +} + +static int _nhlt_add_endpoints(struct nhlt *nhlt, int virtual_bus_id, + const struct nhlt_endp_descriptor *epds, + size_t num_epds) +{ + size_t i; + int ret; + + for (i = 0; i < num_epds; i++) { + ret = _nhlt_add_single_endpoint(nhlt, virtual_bus_id, &epds[i]); + if (ret) + return log_ret(ret); + } + + return 0; +} + +int nhlt_add_endpoints(struct nhlt *nhlt, + const struct nhlt_endp_descriptor *epds, size_t num_epds) +{ + int ret; + + ret = _nhlt_add_endpoints(nhlt, DEFAULT_VIRTUAL_BUS_ID, epds, num_epds); + + return ret; +} + +int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id, + const struct nhlt_endp_descriptor *epds, + size_t num_epds) +{ + int ret; + + ret = _nhlt_add_endpoints(nhlt, virtual_bus_id, epds, num_epds); + if (!ret) + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return ret; +} diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 6985ef4ba5..3a93fedfc3 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -14,6 +14,7 @@ #include <mapmem.h> #include <serial.h> #include <version.h> +#include <acpi/acpigen.h> #include <acpi/acpi_table.h> #include <asm/acpi/global_nvs.h> #include <asm/ioapic.h> @@ -22,6 +23,7 @@ #include <asm/tables.h> #include <asm/arch/global_nvs.h> #include <dm/acpi.h> +#include <linux/err.h> /* * IASL compiles the dsdt entries and writes the hex values @@ -153,7 +155,7 @@ static void acpi_create_madt(struct acpi_madt *madt) /* Fill out header fields */ acpi_fill_header(header, "APIC"); header->length = sizeof(struct acpi_madt); - header->revision = 4; + header->revision = ACPI_MADT_REV_ACPI_3_0; madt->lapic_addr = LAPIC_DEFAULT_BASE; madt->flags = ACPI_MADT_PCAT_COMPAT; @@ -210,13 +212,14 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg) __weak u32 acpi_fill_csrt(u32 current) { - return current; + return 0; } -static void acpi_create_csrt(struct acpi_csrt *csrt) +static int acpi_create_csrt(struct acpi_csrt *csrt) { struct acpi_table_header *header = &(csrt->header); u32 current = (u32)csrt + sizeof(struct acpi_csrt); + uint ptr; memset((void *)csrt, 0, sizeof(struct acpi_csrt)); @@ -225,11 +228,16 @@ static void acpi_create_csrt(struct acpi_csrt *csrt) header->length = sizeof(struct acpi_csrt); header->revision = 0; - current = acpi_fill_csrt(current); + ptr = acpi_fill_csrt(current); + if (!ptr) + return -ENOENT; + current = ptr; /* (Re)calculate length and checksum */ header->length = current - (u32)csrt; header->checksum = table_compute_checksum((void *)csrt, header->length); + + return 0; } static void acpi_create_spcr(struct acpi_spcr *spcr) @@ -354,6 +362,25 @@ static void acpi_create_spcr(struct acpi_spcr *spcr) header->checksum = table_compute_checksum((void *)spcr, header->length); } +void acpi_create_ssdt(struct acpi_ctx *ctx, struct acpi_table_header *ssdt, + const char *oem_table_id) +{ + memset((void *)ssdt, '\0', sizeof(struct acpi_table_header)); + + acpi_fill_header(ssdt, "SSDT"); + ssdt->revision = acpi_get_table_revision(ACPITAB_SSDT); + ssdt->aslc_revision = 1; + ssdt->length = sizeof(struct acpi_table_header); + + acpi_inc(ctx, sizeof(struct acpi_table_header)); + + acpi_fill_ssdt(ctx); + + /* (Re)calculate length and checksum. */ + ssdt->length = ctx->current - (void *)ssdt; + ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length); +} + /* * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c */ @@ -363,6 +390,7 @@ ulong write_acpi_tables(ulong start_addr) struct acpi_facs *facs; struct acpi_table_header *dsdt; struct acpi_fadt *fadt; + struct acpi_table_header *ssdt; struct acpi_mcfg *mcfg; struct acpi_madt *madt; struct acpi_csrt *csrt; @@ -385,11 +413,20 @@ ulong write_acpi_tables(ulong start_addr) debug("ACPI: * DSDT\n"); dsdt = ctx->current; + + /* Put the table header first */ memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header)); acpi_inc(ctx, sizeof(struct acpi_table_header)); + + /* If the table is not empty, allow devices to inject things */ + if (dsdt->length >= sizeof(struct acpi_table_header)) + acpi_inject_dsdt(ctx); + + /* Copy in the AML code itself if any (after the header) */ memcpy(ctx->current, (char *)&AmlCode + sizeof(struct acpi_table_header), dsdt->length - sizeof(struct acpi_table_header)); + acpi_inc_align(ctx, dsdt->length - sizeof(struct acpi_table_header)); /* Pack GNVS into the ACPI table area */ @@ -404,12 +441,23 @@ ulong write_acpi_tables(ulong start_addr) } } - /* Update DSDT checksum since we patched the GNVS address */ + /* + * Recalculate the length and update the DSDT checksum since we patched + * the GNVS address. Set the checksum to zero since it is part of the + * region being checksummed. + */ + dsdt->length = ctx->current - (void *)dsdt; dsdt->checksum = 0; dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length); - /* Fill in platform-specific global NVS variables */ - acpi_create_gnvs(ctx->current); + /* + * Fill in platform-specific global NVS variables. If this fails we + * cannot return the error but this should only happen while debugging. + */ + addr = acpi_create_gnvs(ctx->current); + if (IS_ERR_VALUE(addr)) + printf("Error: Failed to create GNVS\n"); + acpi_inc_align(ctx, sizeof(struct acpi_global_nvs)); debug("ACPI: * FADT\n"); @@ -418,11 +466,13 @@ ulong write_acpi_tables(ulong start_addr) acpi_create_fadt(fadt, facs, dsdt); acpi_add_table(ctx, fadt); - debug("ACPI: * MADT\n"); - madt = ctx->current; - acpi_create_madt(madt); - acpi_inc_align(ctx, madt->header.length); - acpi_add_table(ctx, madt); + debug("ACPI: * SSDT\n"); + ssdt = (struct acpi_table_header *)ctx->current; + acpi_create_ssdt(ctx, ssdt, OEM_TABLE_ID); + if (ssdt->length > sizeof(struct acpi_table_header)) { + acpi_inc_align(ctx, ssdt->length); + acpi_add_table(ctx, ssdt); + } debug("ACPI: * MCFG\n"); mcfg = ctx->current; @@ -430,11 +480,18 @@ ulong write_acpi_tables(ulong start_addr) acpi_inc_align(ctx, mcfg->header.length); acpi_add_table(ctx, mcfg); + debug("ACPI: * MADT\n"); + madt = ctx->current; + acpi_create_madt(madt); + acpi_inc_align(ctx, madt->header.length); + acpi_add_table(ctx, madt); + debug("ACPI: * CSRT\n"); csrt = ctx->current; - acpi_create_csrt(csrt); - acpi_inc_align(ctx, csrt->header.length); - acpi_add_table(ctx, csrt); + if (!acpi_create_csrt(csrt)) { + acpi_inc_align(ctx, csrt->header.length); + acpi_add_table(ctx, csrt); + } debug("ACPI: * SPCR\n"); spcr = ctx->current; diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c index 331c1b7e5a..6cd3244301 100644 --- a/arch/x86/lib/coreboot_table.c +++ b/arch/x86/lib/coreboot_table.c @@ -21,11 +21,11 @@ int high_table_reserve(void) gd->arch.high_table_ptr = gd->start_addr_sp; /* clear the memory */ -#ifdef CONFIG_HAVE_ACPI_RESUME - if (gd->arch.prev_sleep_state != ACPI_S3) -#endif + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && + gd->arch.prev_sleep_state != ACPI_S3) { memset((void *)gd->arch.high_table_ptr, 0, CONFIG_HIGH_TABLE_SIZE); + } gd->start_addr_sp &= ~0xf; diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index cf32b3e512..ea52954725 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -47,7 +47,7 @@ int fsp_init_phase_pci(void) return status ? -EPERM : 0; } -void board_final_cleanup(void) +void board_final_init(void) { u32 status; @@ -60,7 +60,6 @@ void board_final_cleanup(void) debug("OK\n"); } -#ifdef CONFIG_HAVE_ACPI_RESUME int fsp_save_s3_stack(void) { struct udevice *dev; @@ -84,4 +83,3 @@ int fsp_save_s3_stack(void) return 0; } -#endif diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index ad5a0f79ad..01d498c21e 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -117,17 +117,21 @@ unsigned int install_e820_map(unsigned int max_entries, entries[num_entries].type = E820_RESERVED; num_entries++; -#ifdef CONFIG_HAVE_ACPI_RESUME - /* - * Everything between U-Boot's stack and ram top needs to be - * reserved in order for ACPI S3 resume to work. - */ - entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE; - entries[num_entries].size = gd->ram_top - gd->start_addr_sp + - CONFIG_STACK_SIZE; - entries[num_entries].type = E820_RESERVED; - num_entries++; -#endif + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + ulong stack_size; + + stack_size = CONFIG_IS_ENABLED(HAVE_ACPI_RESUME, + (CONFIG_STACK_SIZE), (0)); + /* + * Everything between U-Boot's stack and ram top needs to be + * reserved in order for ACPI S3 resume to work. + */ + entries[num_entries].addr = gd->start_addr_sp - stack_size; + entries[num_entries].size = gd->ram_top - gd->start_addr_sp + + stack_size; + entries[num_entries].type = E820_RESERVED; + num_entries++; + } return num_entries; } diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c index 43d32b7abe..da351cf097 100644 --- a/arch/x86/lib/fsp1/fsp_common.c +++ b/arch/x86/lib/fsp1/fsp_common.c @@ -46,10 +46,12 @@ int arch_fsp_init(void) void *nvs; int stack = CONFIG_FSP_TEMP_RAM_ADDR; int boot_mode = BOOT_FULL_CONFIG; -#ifdef CONFIG_HAVE_ACPI_RESUME - int prev_sleep_state = chipset_prev_sleep_state(); - gd->arch.prev_sleep_state = prev_sleep_state; -#endif + int prev_sleep_state; + + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { + prev_sleep_state = chipset_prev_sleep_state(); + gd->arch.prev_sleep_state = prev_sleep_state; + } if (!gd->arch.hob_list) { if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) @@ -57,8 +59,8 @@ int arch_fsp_init(void) else nvs = NULL; -#ifdef CONFIG_HAVE_ACPI_RESUME - if (prev_sleep_state == ACPI_S3) { + if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && + prev_sleep_state == ACPI_S3) { if (nvs == NULL) { /* If waking from S3 and no cache then */ debug("No MRC cache found in S3 resume path\n"); @@ -79,7 +81,7 @@ int arch_fsp_init(void) stack = cmos_read32(CMOS_FSP_STACK_ADDR); boot_mode = BOOT_ON_S3_RESUME; } -#endif + /* * The first time we enter here, call fsp_init(). * Note the execution does not return to this function, diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index 1c82b81831..c9f6402e6a 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -27,11 +27,10 @@ int dram_init(void) return 0; } if (spl_phase() == PHASE_SPL) { -#ifdef CONFIG_HAVE_ACPI_RESUME - bool s3wake = gd->arch.prev_sleep_state == ACPI_S3; -#else bool s3wake = false; -#endif + + s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && + gd->arch.prev_sleep_state == ACPI_S3; ret = fsp_memory_init(s3wake, IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH)); diff --git a/arch/x86/lib/fsp2/fsp_meminit.c b/arch/x86/lib/fsp2/fsp_meminit.c index faf9c29aef..ce0b0aff76 100644 --- a/arch/x86/lib/fsp2/fsp_meminit.c +++ b/arch/x86/lib/fsp2/fsp_meminit.c @@ -9,6 +9,7 @@ #include <common.h> #include <binman.h> #include <bootstage.h> +#include <dm.h> #include <log.h> #include <asm/mrccache.h> #include <asm/fsp/fsp_infoheader.h> @@ -63,8 +64,10 @@ int fsp_memory_init(bool s3wake, bool use_spi_flash) struct fsp_header *hdr; struct hob_header *hob; struct udevice *dev; + int delay; int ret; + log_debug("Locating FSP\n"); ret = fsp_locate_fsp(FSP_M, &entry, use_spi_flash, &dev, &hdr, NULL); if (ret) return log_msg_ret("locate FSP", ret); @@ -76,21 +79,32 @@ int fsp_memory_init(bool s3wake, bool use_spi_flash) return log_msg_ret("Bad UPD signature", -EPERM); memcpy(&upd, fsp_upd, sizeof(upd)); + delay = dev_read_u32_default(dev, "fspm,training-delay", 0); ret = fspm_update_config(dev, &upd); - if (ret) - return log_msg_ret("Could not setup config", ret); - - debug("SDRAM init..."); + if (ret) { + if (ret != -ENOENT) + return log_msg_ret("Could not setup config", ret); + } else { + delay = 0; + } + + if (delay) + printf("SDRAM training (%d seconds)...", delay); + else + log_debug("SDRAM init..."); bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_M, "fsp-m"); func = (fsp_memory_init_func)(hdr->img_base + hdr->fsp_mem_init); ret = func(&upd, &hob); bootstage_accum(BOOTSTAGE_ID_ACCUM_FSP_M); cpu_reinit_fpu(); + if (delay) + printf("done\n"); + else + log_debug("done\n"); if (ret) return log_msg_ret("SDRAM init fail\n", ret); gd->arch.hob_list = hob; - debug("done\n"); ret = fspm_done(dev); if (ret) diff --git a/arch/x86/lib/fsp2/fsp_silicon_init.c b/arch/x86/lib/fsp2/fsp_silicon_init.c index 45c0c7d90b..0f221a864f 100644 --- a/arch/x86/lib/fsp2/fsp_silicon_init.c +++ b/arch/x86/lib/fsp2/fsp_silicon_init.c @@ -32,6 +32,7 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash) &rom_offset); if (ret) return log_msg_ret("locate FSP", ret); + binman_set_rom_offset(rom_offset); gd->arch.fsp_s_hdr = hdr; /* Copy over the default config */ diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 574d331d76..7bad5dd303 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <log.h> #include <malloc.h> #include <smbios.h> #include <acpi/acpi_table.h> @@ -20,21 +21,32 @@ */ typedef ulong (*table_write)(ulong addr); -static table_write table_write_funcs[] = { +/** + * struct table_info - Information about each table to write + * + * @name: Name of table (for debugging) + * @write: Function to call to write this table + */ +struct table_info { + const char *name; + table_write write; +}; + +static struct table_info table_list[] = { #ifdef CONFIG_GENERATE_PIRQ_TABLE - write_pirq_routing_table, + { "pirq", write_pirq_routing_table }, #endif #ifdef CONFIG_GENERATE_SFI_TABLE - write_sfi_table, + { "sfi", write_sfi_table, }, #endif #ifdef CONFIG_GENERATE_MP_TABLE - write_mp_table, + { "mp", write_mp_table, }, #endif #ifdef CONFIG_GENERATE_ACPI_TABLE - write_acpi_tables, + { "acpi", write_acpi_tables, }, #endif #ifdef CONFIG_GENERATE_SMBIOS_TABLE - write_smbios_table, + { "smbios", write_smbios_table, }, #endif }; @@ -58,19 +70,22 @@ void write_tables(void) u32 rom_table_end; #ifdef CONFIG_SEABIOS u32 high_table, table_size; - struct memory_area cfg_tables[ARRAY_SIZE(table_write_funcs) + 1]; + struct memory_area cfg_tables[ARRAY_SIZE(table_list) + 1]; #endif int i; - for (i = 0; i < ARRAY_SIZE(table_write_funcs); i++) { - rom_table_end = table_write_funcs[i](rom_table_start); + debug("Writing tables to %x:\n", rom_table_start); + for (i = 0; i < ARRAY_SIZE(table_list); i++) { + const struct table_info *table = &table_list[i]; + + rom_table_end = table->write(rom_table_start); rom_table_end = ALIGN(rom_table_end, ROM_TABLE_ALIGN); #ifdef CONFIG_SEABIOS table_size = rom_table_end - rom_table_start; high_table = (u32)high_table_malloc(table_size); if (high_table) { - table_write_funcs[i](high_table); + table->write(high_table); cfg_tables[i].start = high_table; cfg_tables[i].size = table_size; @@ -79,6 +94,8 @@ void write_tables(void) } #endif + debug("- wrote '%s' to %x, end %x\n", table->name, + rom_table_start, rom_table_end); rom_table_start = rom_table_end; } @@ -87,4 +104,5 @@ void write_tables(void) cfg_tables[i].size = 0; write_coreboot_table(CB_TABLE_ADDR, cfg_tables); #endif + debug("- done writing tables\n"); } diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 64d14e8911..d2b6002008 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -304,13 +304,6 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, return 0; } -void setup_pcat_compatibility(void) - __attribute__((weak, alias("__setup_pcat_compatibility"))); - -void __setup_pcat_compatibility(void) -{ -} - int do_zboot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct boot_params *base_ptr; @@ -323,9 +316,6 @@ int do_zboot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) disable_interrupts(); - /* Setup board for maximum PC/AT Compatibility */ - setup_pcat_compatibility(); - if (argc >= 2) { /* argv[1] holds the address of the bzImage */ s = argv[1]; |