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-rw-r--r--arch/x86/cpu/apollolake/cpu.c7
-rw-r--r--arch/x86/cpu/cpu_x86.c2
-rw-r--r--arch/x86/cpu/intel_common/p2sb.c30
-rw-r--r--arch/x86/cpu/start.S2
-rw-r--r--arch/x86/cpu/start16.S2
-rw-r--r--arch/x86/dts/chromebook_coral.dts2
-rw-r--r--arch/x86/include/asm/cpu_x86.h12
-rw-r--r--arch/x86/lib/mrccache.c2
8 files changed, 34 insertions, 25 deletions
diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c
index 3d05c82a5c..aa7a3dbd63 100644
--- a/arch/x86/cpu/apollolake/cpu.c
+++ b/arch/x86/cpu/apollolake/cpu.c
@@ -14,15 +14,10 @@ static int apl_get_info(struct udevice *dev, struct cpu_info *info)
return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
}
-static int apl_get_count(struct udevice *dev)
-{
- return 4;
-}
-
static const struct cpu_ops cpu_x86_apl_ops = {
.get_desc = cpu_x86_get_desc,
.get_info = apl_get_info,
- .get_count = apl_get_count,
+ .get_count = cpu_x86_get_count,
.get_vendor = cpu_x86_get_vendor,
};
diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c
index 1aaf851bb4..3f2ba0881e 100644
--- a/arch/x86/cpu/cpu_x86.c
+++ b/arch/x86/cpu/cpu_x86.c
@@ -52,7 +52,7 @@ int cpu_x86_get_desc(struct udevice *dev, char *buf, int size)
return 0;
}
-static int cpu_x86_get_count(struct udevice *dev)
+int cpu_x86_get_count(struct udevice *dev)
{
int node, cpu;
int num = 0;
diff --git a/arch/x86/cpu/intel_common/p2sb.c b/arch/x86/cpu/intel_common/p2sb.c
index b72f50a627..d5b4846e0a 100644
--- a/arch/x86/cpu/intel_common/p2sb.c
+++ b/arch/x86/cpu/intel_common/p2sb.c
@@ -16,7 +16,7 @@
struct p2sb_platdata {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
- struct dtd_intel_apl_p2sb dtplat;
+ struct dtd_intel_p2sb dtplat;
#endif
ulong mmio_base;
pci_dev_t bdf;
@@ -43,14 +43,14 @@ struct p2sb_platdata {
#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
/*
- * apl_p2sb_early_init() - Enable decoding for HPET range
+ * p2sb_early_init() - Enable decoding for HPET range
*
* This is needed by FSP-M which uses the High Precision Event Timer.
*
* @dev: P2SB device
* @return 0 if OK, -ve on error
*/
-static int apl_p2sb_early_init(struct udevice *dev)
+static int p2sb_early_init(struct udevice *dev)
{
struct p2sb_platdata *plat = dev_get_platdata(dev);
pci_dev_t pdev = plat->bdf;
@@ -76,7 +76,7 @@ static int apl_p2sb_early_init(struct udevice *dev)
return 0;
}
-static int apl_p2sb_spl_init(struct udevice *dev)
+static int p2sb_spl_init(struct udevice *dev)
{
/* Enable decoding for HPET. Needed for FSP global pointer storage */
dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
@@ -85,7 +85,7 @@ static int apl_p2sb_spl_init(struct udevice *dev)
return 0;
}
-int apl_p2sb_ofdata_to_platdata(struct udevice *dev)
+int p2sb_ofdata_to_platdata(struct udevice *dev)
{
struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
struct p2sb_platdata *plat = dev_get_platdata(dev);
@@ -117,10 +117,10 @@ int apl_p2sb_ofdata_to_platdata(struct udevice *dev)
return 0;
}
-static int apl_p2sb_probe(struct udevice *dev)
+static int p2sb_probe(struct udevice *dev)
{
if (spl_phase() == PHASE_TPL) {
- return apl_p2sb_early_init(dev);
+ return p2sb_early_init(dev);
} else {
struct p2sb_platdata *plat = dev_get_platdata(dev);
@@ -130,7 +130,7 @@ static int apl_p2sb_probe(struct udevice *dev)
return -EINVAL;
if (spl_phase() == PHASE_SPL)
- return apl_p2sb_spl_init(dev);
+ return p2sb_spl_init(dev);
}
return 0;
@@ -152,17 +152,17 @@ static int p2sb_child_post_bind(struct udevice *dev)
return 0;
}
-static const struct udevice_id apl_p2sb_ids[] = {
- { .compatible = "intel,apl-p2sb" },
+static const struct udevice_id p2sb_ids[] = {
+ { .compatible = "intel,p2sb" },
{ }
};
-U_BOOT_DRIVER(apl_p2sb_drv) = {
- .name = "intel_apl_p2sb",
+U_BOOT_DRIVER(p2sb_drv) = {
+ .name = "intel_p2sb",
.id = UCLASS_P2SB,
- .of_match = apl_p2sb_ids,
- .probe = apl_p2sb_probe,
- .ofdata_to_platdata = apl_p2sb_ofdata_to_platdata,
+ .of_match = p2sb_ids,
+ .probe = p2sb_probe,
+ .ofdata_to_platdata = p2sb_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
.per_child_platdata_auto_alloc_size =
sizeof(struct p2sb_child_platdata),
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 26cf995db2..01524635e9 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -50,7 +50,7 @@ _x86boot_start:
movl %cr0, %eax
orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
- invd
+ wbinvd
/*
* Zero the BIST (Built-In Self Test) value since we don't have it.
diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S
index 292e750508..54f4ff6662 100644
--- a/arch/x86/cpu/start16.S
+++ b/arch/x86/cpu/start16.S
@@ -28,7 +28,7 @@ start16:
movl %cr0, %eax
orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
- invd
+ wbinvd
/* load the temporary Global Descriptor Table */
data32 cs lidt idt_ptr
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index 44a4619a66..af52e11c89 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -136,7 +136,7 @@
p2sb: p2sb@d,0 {
u-boot,dm-pre-reloc;
reg = <0x02006810 0 0 0 0>;
- compatible = "intel,apl-p2sb";
+ compatible = "intel,p2sb";
early-regs = <IOMAP_P2SB_BAR 0x100000>;
n {
diff --git a/arch/x86/include/asm/cpu_x86.h b/arch/x86/include/asm/cpu_x86.h
index 19223f2c3b..ae8f4dcd5d 100644
--- a/arch/x86/include/asm/cpu_x86.h
+++ b/arch/x86/include/asm/cpu_x86.h
@@ -31,6 +31,18 @@ int cpu_x86_bind(struct udevice *dev);
int cpu_x86_get_desc(struct udevice *dev, char *buf, int size);
/**
+ * cpu_x86_get_count() - Get the number of cores for an x86 CPU
+ *
+ * This function is suitable to use as the get_count() method for
+ * the CPU uclass.
+ *
+ * @dev: Device to check (UCLASS_CPU)
+ * @return: Number of cores if successful,
+ * -ENOENT if not "/cpus" entry is found in the device tree
+ */
+int cpu_x86_get_count(struct udevice *dev);
+
+/**
* cpu_x86_get_vendor() - Get a vendor string for an x86 CPU
*
* This uses cpu_vendor_name() and is suitable to use as the get_vendor()
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 8914960226..d1c44f290c 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -241,6 +241,8 @@ int mrccache_get_region(enum mrc_type_t type, struct udevice **devp,
* memory map cannot be read.
*/
ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
+ if (!ret && !dev)
+ ret = -ENODEV;
if (ret)
return log_msg_ret("Cannot find SPI flash\n", ret);
ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);