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-rw-r--r--arch/x86/cpu/Makefile4
-rw-r--r--arch/x86/cpu/coreboot/Kconfig1
-rw-r--r--arch/x86/cpu/coreboot/Makefile8
-rw-r--r--arch/x86/cpu/coreboot/coreboot.c3
-rw-r--r--arch/x86/cpu/coreboot/coreboot_spl.c12
-rw-r--r--arch/x86/cpu/cpu.c25
-rw-r--r--arch/x86/cpu/i386/cpu.c36
-rw-r--r--arch/x86/cpu/intel_common/Makefile2
-rw-r--r--arch/x86/cpu/x86_64/cpu.c2
-rw-r--r--arch/x86/dts/coreboot-u-boot.dtsi18
-rw-r--r--arch/x86/lib/spl.c23
11 files changed, 92 insertions, 42 deletions
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 307267a8fb..ee0499f5d7 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -54,9 +54,11 @@ obj-$(CONFIG_INTEL_QUARK) += quark/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
obj-$(CONFIG_INTEL_TANGIER) += tangier/
obj-$(CONFIG_APIC) += lapic.o ioapic.o
-obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o
obj-$(CONFIG_$(SPL_TPL_)ACPI_GPE) += acpi_gpe.o
obj-$(CONFIG_QFW) += qfw_cpu.o
+ifndef CONFIG_SYS_COREBOOT
+obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o
+endif
ifndef CONFIG_$(SPL_)X86_64
obj-$(CONFIG_SMP) += mp_init.o
endif
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index c8e6a889d0..497d6284ac 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -25,5 +25,6 @@ config SYS_COREBOOT
imply FS_CBFS
imply CBMEM_CONSOLE
imply X86_TSC_READ_BASE
+ select BINMAN if X86_64
endif
diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile
index 35b15bb1da..605f90304e 100644
--- a/arch/x86/cpu/coreboot/Makefile
+++ b/arch/x86/cpu/coreboot/Makefile
@@ -11,8 +11,14 @@
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ifndef CONFIG_SPL
obj-y += car.o
+endif
+ifdef CONFIG_SPL_BUILD
+obj-y += coreboot_spl.o
+else
+obj-y += sdram.o
+endif
obj-y += coreboot.o
obj-y += tables.o
-obj-y += sdram.o
obj-y += timestamp.o
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 0c4c6348d1..624caf67a6 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -27,7 +27,8 @@ int arch_cpu_init(void)
timestamp_init();
- return x86_cpu_init_f();
+ return IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() :
+ x86_cpu_init_f();
}
int checkcpu(void)
diff --git a/arch/x86/cpu/coreboot/coreboot_spl.c b/arch/x86/cpu/coreboot/coreboot_spl.c
new file mode 100644
index 0000000000..36661871e9
--- /dev/null
+++ b/arch/x86/cpu/coreboot/coreboot_spl.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#include <common.h>
+#include <init.h>
+
+int dram_init(void)
+{
+ return 0;
+}
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 8526e856d7..2e5d0ddd9f 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -290,3 +290,28 @@ int reserve_arch(void)
return 0;
}
#endif
+
+long detect_coreboot_table_at(ulong start, ulong size)
+{
+ u32 *ptr, *end;
+
+ size /= 4;
+ for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
+ if (*ptr == 0x4f49424c) /* "LBIO" */
+ return (long)ptr;
+ }
+
+ return -ENOENT;
+}
+
+long locate_coreboot_table(void)
+{
+ long addr;
+
+ /* We look for LBIO in the first 4K of RAM and again at 960KB */
+ addr = detect_coreboot_table_at(0x0, 0x1000);
+ if (addr < 0)
+ addr = detect_coreboot_table_at(0xf0000, 0x1000);
+
+ return addr;
+}
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 0312a26bbb..435e50edad 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -24,6 +24,7 @@
#include <malloc.h>
#include <spl.h>
#include <asm/control_regs.h>
+#include <asm/coreboot_tables.h>
#include <asm/cpu.h>
#include <asm/mp.h>
#include <asm/msr.h>
@@ -447,31 +448,6 @@ int x86_cpu_init_f(void)
return 0;
}
-long detect_coreboot_table_at(ulong start, ulong size)
-{
- u32 *ptr, *end;
-
- size /= 4;
- for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
- if (*ptr == 0x4f49424c) /* "LBIO" */
- return (long)ptr;
- }
-
- return -ENOENT;
-}
-
-long locate_coreboot_table(void)
-{
- long addr;
-
- /* We look for LBIO in the first 4K of RAM and again at 960KB */
- addr = detect_coreboot_table_at(0x0, 0x1000);
- if (addr < 0)
- addr = detect_coreboot_table_at(0xf0000, 0x1000);
-
- return addr;
-}
-
int x86_cpu_reinit_f(void)
{
setup_identity();
@@ -638,16 +614,6 @@ int cpu_jump_to_64bit_uboot(ulong target)
func = (func_t)ptr;
- /*
- * Copy U-Boot from ROM
- * TODO(sjg@chromium.org): Figure out a way to get the text base
- * correctly here, and in the device-tree binman definition.
- *
- * Also consider using FIT so we get the correct image length and
- * parameters.
- */
- memcpy((char *)target, (char *)0xfff00000, 0x100000);
-
/* Jump to U-Boot */
func((ulong)pgtable, 0, (ulong)target);
diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index 1736bd2b53..374803b876 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -32,6 +32,8 @@ obj-$(CONFIG_HAVE_P2SB) += p2sb.o
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_SYS_COREBOOT
obj-y += cpu_from_spl.o
endif
endif
+endif
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 90925e46ea..4b64339f25 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -53,6 +53,7 @@ int misc_init_r(void)
return 0;
}
+#ifndef CONFIG_SYS_COREBOOT
int checkcpu(void)
{
return 0;
@@ -62,6 +63,7 @@ int print_cpuinfo(void)
{
return 0;
}
+#endif
int x86_cpu_reinit_f(void)
{
diff --git a/arch/x86/dts/coreboot-u-boot.dtsi b/arch/x86/dts/coreboot-u-boot.dtsi
new file mode 100644
index 0000000000..38efc48d83
--- /dev/null
+++ b/arch/x86/dts/coreboot-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <config.h>
+
+/ {
+ binman {
+ filename = "u-boot-x86-with-spl.bin";
+ u-boot-spl {
+ };
+ u-boot {
+ offset = <0x10000>;
+ };
+ };
+};
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 90baec2a17..212b4d596d 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -63,7 +63,7 @@ static int x86_spl_init(void)
* is not needed. We could make this a CONFIG option or perhaps
* place it immediately below CONFIG_SYS_TEXT_BASE.
*/
- char *ptr = (char *)0x110000;
+ __maybe_unused char *ptr = (char *)0x110000;
#else
struct udevice *punit;
#endif
@@ -111,7 +111,8 @@ static int x86_spl_init(void)
__func__, ret);
}
-#ifndef CONFIG_TPL
+#ifndef CONFIG_SYS_COREBOOT
+# ifndef CONFIG_TPL
memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
/* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
@@ -140,7 +141,7 @@ static int x86_spl_init(void)
return ret;
}
mtrr_commit(true);
-#else
+# else
ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
if (ret)
debug("Could not find PUNIT (err=%d)\n", ret);
@@ -148,6 +149,7 @@ static int x86_spl_init(void)
ret = set_max_freq();
if (ret)
debug("Failed to set CPU frequency (err=%d)\n", ret);
+# endif
#endif
return 0;
@@ -162,7 +164,7 @@ void board_init_f(ulong flags)
debug("Error %d\n", ret);
panic("x86_spl_init fail");
}
-#ifdef CONFIG_TPL
+#if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT)
gd->bd = malloc(sizeof(*gd->bd));
if (!gd->bd) {
printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
@@ -207,6 +209,19 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
+ if (!IS_ENABLED(CONFIG_SYS_COREBOOT)) {
+ /*
+ * Copy U-Boot from ROM
+ * TODO(sjg@chromium.org): Figure out a way to get the text base
+ * correctly here, and in the device-tree binman definition.
+ *
+ * Also consider using FIT so we get the correct image length
+ * and parameters.
+ */
+ memcpy((char *)spl_image->load_addr, (char *)0xfff00000,
+ 0x100000);
+ }
+
debug("Loading to %lx\n", spl_image->load_addr);
return 0;
generated by cgit (git 2.34.1) at 2025-01-13 08:52:57 +0000