summaryrefslogtreecommitdiff
path: root/arch/xtensa/include
diff options
context:
space:
mode:
Diffstat (limited to 'arch/xtensa/include')
-rw-r--r--arch/xtensa/include/asm/addrspace.h31
-rw-r--r--arch/xtensa/include/asm/asmmacro.h152
-rw-r--r--arch/xtensa/include/asm/atomic.h55
-rw-r--r--arch/xtensa/include/asm/bitops.h36
-rw-r--r--arch/xtensa/include/asm/bootparam.h54
-rw-r--r--arch/xtensa/include/asm/byteorder.h83
-rw-r--r--arch/xtensa/include/asm/cache.h25
-rw-r--r--arch/xtensa/include/asm/cacheasm.h211
-rw-r--r--arch/xtensa/include/asm/config.h24
-rw-r--r--arch/xtensa/include/asm/errno.h1
-rw-r--r--arch/xtensa/include/asm/global_data.h20
-rw-r--r--arch/xtensa/include/asm/io.h148
-rw-r--r--arch/xtensa/include/asm/ldscript.h222
-rw-r--r--arch/xtensa/include/asm/linkage.h4
-rw-r--r--arch/xtensa/include/asm/misc.h20
-rw-r--r--arch/xtensa/include/asm/posix_types.h74
-rw-r--r--arch/xtensa/include/asm/processor.h11
-rw-r--r--arch/xtensa/include/asm/ptrace.h133
-rw-r--r--arch/xtensa/include/asm/regs.h95
-rw-r--r--arch/xtensa/include/asm/relocate.h14
-rw-r--r--arch/xtensa/include/asm/sections.h12
-rw-r--r--arch/xtensa/include/asm/string.h10
-rw-r--r--arch/xtensa/include/asm/system.h27
-rw-r--r--arch/xtensa/include/asm/types.h60
-rw-r--r--arch/xtensa/include/asm/u-boot.h41
-rw-r--r--arch/xtensa/include/asm/unaligned.h6
26 files changed, 1569 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/addrspace.h b/arch/xtensa/include/asm/addrspace.h
new file mode 100644
index 0000000000..1d62259fd5
--- /dev/null
+++ b/arch/xtensa/include/asm/addrspace.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2008-2013 Tensilica Inc.
+ * Copyright (C) 2016 Cadence Design Systems Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_ADDRSPACE_H
+#define _XTENSA_ADDRSPACE_H
+
+#include <asm/arch/core.h>
+
+/*
+ * MMU Memory Map
+ *
+ * noMMU and v3 MMU have identity mapped address space on reset.
+ * V2 MMU:
+ * IO (uncached) f0000000..ffffffff -> f000000
+ * IO (cached) e0000000..efffffff -> f000000
+ * MEM (uncached) d8000000..dfffffff -> 0000000
+ * MEM (cached) d0000000..d7ffffff -> 0000000
+ *
+ * The actual location of memory and IO is the board property.
+ */
+
+#define IOADDR(x) (CONFIG_SYS_IO_BASE + (x))
+#define MEMADDR(x) (CONFIG_SYS_MEMORY_BASE + (x))
+#define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \
+ XCHAL_VECBASE_RESET_PADDR)
+
+#endif /* _XTENSA_ADDRSPACE_H */
diff --git a/arch/xtensa/include/asm/asmmacro.h b/arch/xtensa/include/asm/asmmacro.h
new file mode 100644
index 0000000000..b7adc7e198
--- /dev/null
+++ b/arch/xtensa/include/asm/asmmacro.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2005 - 2013 Tensilica Inc.
+ * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_ASMMACRO_H
+#define _XTENSA_ASMMACRO_H
+
+#include <asm/arch/core.h>
+
+/*
+ * Function entry and return macros for supported ABIs.
+ */
+
+#if defined(__XTENSA_WINDOWED_ABI__)
+#define abi_entry entry sp, 16
+#define abi_ret retw
+#elif defined(__XTENSA_CALL0_ABI__)
+#define abi_entry
+#define abi_ret ret
+#else
+#error Unsupported Xtensa ABI
+#endif
+
+/*
+ * Some little helpers for loops. Use zero-overhead-loops
+ * where applicable and if supported by the processor.
+ *
+ * __loopi ar, at, size, inc
+ * ar register initialized with the start address
+ * at scratch register used by macro
+ * size size immediate value
+ * inc increment
+ *
+ * __loops ar, as, at, inc_log2[, mask_log2][, cond][, ncond]
+ * ar register initialized with the start address
+ * as register initialized with the size
+ * at scratch register use by macro
+ * inc_log2 increment [in log2]
+ * mask_log2 mask [in log2]
+ * cond true condition (used in loop'cond')
+ * ncond false condition (used in b'ncond')
+ *
+ * __loop as
+ * restart loop. 'as' register must not have been modified!
+ *
+ * __endla ar, as, incr
+ * ar start address (modified)
+ * as scratch register used by __loops/__loopi macros or
+ * end address used by __loopt macro
+ * inc increment
+ */
+
+#if XCHAL_HAVE_LOOPS
+
+.macro __loopi ar, at, size, incr
+ movi \at, ((\size + \incr - 1) / (\incr))
+ loop \at, 99f
+.endm
+
+
+.macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
+ .ifgt \incr_log2 - 1
+ addi \at, \as, (1 << \incr_log2) - 1
+ .ifnc \mask_log2,
+ extui \at, \at, \incr_log2, \mask_log2
+ .else
+ srli \at, \at, \incr_log2
+ .endif
+ .endif
+ loop\cond \at, 99f
+.endm
+
+
+.macro __loopt ar, as, at, incr_log2
+ sub \at, \as, \ar
+ .ifgt \incr_log2 - 1
+ addi \at, \at, (1 << \incr_log2) - 1
+ srli \at, \at, \incr_log2
+ .endif
+ loop \at, 99f
+.endm
+
+
+.macro __loop as
+ loop \as, 99f
+.endm
+
+
+.macro __endl ar, as
+99:
+.endm
+
+
+#else
+
+.macro __loopi ar, at, size, incr
+ movi \at, ((\size + \incr - 1) / (\incr))
+ addi \at, \ar, \size
+98:
+.endm
+
+
+.macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
+ .ifnc \mask_log2,
+ extui \at, \as, \incr_log2, \mask_log2
+ .else
+ .ifnc \ncond,
+ srli \at, \as, \incr_log2
+ .endif
+ .endif
+ .ifnc \ncond,
+ b\ncond \at, 99f
+
+ .endif
+ .ifnc \mask_log2,
+ slli \at, \at, \incr_log2
+ add \at, \ar, \at
+ .else
+ add \at, \ar, \as
+ .endif
+98:
+.endm
+
+.macro __loopt ar, as, at, incr_log2
+98:
+.endm
+
+
+.macro __loop as
+98:
+.endm
+
+
+.macro __endl ar, as
+ bltu \ar, \as, 98b
+99:
+.endm
+
+
+#endif
+
+
+.macro __endla ar, as, incr
+ addi \ar, \ar, \incr
+ __endl \ar \as
+.endm
+
+
+#endif /* _XTENSA_ASMMACRO_H */
diff --git a/arch/xtensa/include/asm/atomic.h b/arch/xtensa/include/asm/atomic.h
new file mode 100644
index 0000000000..a75baa09e0
--- /dev/null
+++ b/arch/xtensa/include/asm/atomic.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2016 Cadence Design Systems Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_ATOMIC_H
+#define _XTENSA_ATOMIC_H
+
+#include <asm/system.h>
+
+typedef struct { volatile int counter; } atomic_t;
+
+#define ATOMIC_INIT(i) { (i) }
+
+#define atomic_read(v) ((v)->counter)
+#define atomic_set(v, i) ((v)->counter = (i))
+
+static inline void atomic_add(int i, atomic_t *v)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ v->counter += i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ v->counter -= i;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_inc(atomic_t *v)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ ++v->counter;
+ local_irq_restore(flags);
+}
+
+static inline void atomic_dec(atomic_t *v)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ --v->counter;
+ local_irq_restore(flags);
+}
+
+#endif
diff --git a/arch/xtensa/include/asm/bitops.h b/arch/xtensa/include/asm/bitops.h
new file mode 100644
index 0000000000..550d12f498
--- /dev/null
+++ b/arch/xtensa/include/asm/bitops.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2001 - 2012 Tensilica Inc.
+ * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_BITOPS_H
+#define _XTENSA_BITOPS_H
+
+#include <asm/system.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
+static inline int test_bit(int nr, const void *addr)
+{
+ return ((unsigned char *)addr)[nr >> 3] & (1u << (nr & 7));
+}
+
+static inline int test_and_set_bit(int nr, volatile void *addr)
+{
+ unsigned long flags;
+ unsigned char tmp;
+ unsigned char mask = 1u << (nr & 7);
+
+ local_irq_save(flags);
+ tmp = ((unsigned char *)addr)[nr >> 3];
+ ((unsigned char *)addr)[nr >> 3] |= mask;
+ local_irq_restore(flags);
+
+ return tmp & mask;
+}
+
+#endif /* _XTENSA_BITOPS_H */
diff --git a/arch/xtensa/include/asm/bootparam.h b/arch/xtensa/include/asm/bootparam.h
new file mode 100644
index 0000000000..a2a9013ebf
--- /dev/null
+++ b/arch/xtensa/include/asm/bootparam.h
@@ -0,0 +1,54 @@
+/*
+ * Definition of the Linux/Xtensa boot parameter structure
+ *
+ * Copyright (C) 2001 - 2009 Tensilica Inc.
+ *
+ * (Concept borrowed from the 68K port)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_BOOTPARAM_H
+#define _XTENSA_BOOTPARAM_H
+
+#define BP_VERSION 0x0001
+
+#define BP_TAG_COMMAND_LINE 0x1001 /* command line (0-terminated string)*/
+#define BP_TAG_INITRD 0x1002 /* ramdisk addr and size (bp_meminfo) */
+#define BP_TAG_MEMORY 0x1003 /* memory addr and size (bp_meminfo) */
+#define BP_TAG_SERIAL_BAUDRATE 0x1004 /* baud rate of current console */
+#define BP_TAG_SERIAL_PORT 0x1005 /* serial device of current console */
+#define BP_TAG_FDT 0x1006 /* flat device tree */
+
+#define BP_TAG_FIRST 0x7B0B /* first tag with a version number */
+#define BP_TAG_LAST 0x7E0B /* last tag */
+
+#ifndef __ASSEMBLY__
+
+/* All records are aligned to 4 bytes */
+
+struct bp_tag {
+ unsigned short id; /* tag id */
+ unsigned short size; /* size of this record excluding the structure*/
+ unsigned long data[0]; /* data */
+};
+
+#define bp_tag_next(tag) \
+ ((struct bp_tag *)((unsigned long)((tag) + 1) + (tag)->size))
+
+struct meminfo {
+ unsigned long type;
+ unsigned long start;
+ unsigned long end;
+};
+
+#define MEMORY_TYPE_CONVENTIONAL 0x1000
+#define MEMORY_TYPE_NONE 0x2000
+
+struct sysmem_info {
+ int nr_banks;
+ struct meminfo bank[0];
+};
+
+#endif
+#endif
diff --git a/arch/xtensa/include/asm/byteorder.h b/arch/xtensa/include/asm/byteorder.h
new file mode 100644
index 0000000000..278653ce48
--- /dev/null
+++ b/arch/xtensa/include/asm/byteorder.h
@@ -0,0 +1,83 @@
+/*
+ * Based on Linux/Xtensa kernel version
+ *
+ * Copyright (C) 2001 - 2007 Tensilica Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_BYTEORDER_H
+#define _XTENSA_BYTEORDER_H
+
+#include <asm/types.h>
+
+static inline __attribute__((const)) __u32 ___arch__swab32(__u32 x)
+{
+ __u32 res;
+
+ /* instruction sequence from Xtensa ISA release 2/2000 */
+ __asm__("ssai 8\n\t"
+ "srli %0, %1, 16\n\t"
+ "src %0, %0, %1\n\t"
+ "src %0, %0, %0\n\t"
+ "src %0, %1, %0\n"
+ : "=&a" (res)
+ : "a" (x)
+ );
+ return res;
+}
+
+static inline __attribute__((const)) __u16 ___arch__swab16(__u16 x)
+{
+ /*
+ * Given that 'short' values are signed (i.e., can be negative),
+ * we cannot assume that the upper 16-bits of the register are
+ * zero. We are careful to mask values after shifting.
+ */
+
+ /*
+ * There exists an anomaly between xt-gcc and xt-xcc. xt-gcc
+ * inserts an extui instruction after putting this function inline
+ * to ensure that it uses only the least-significant 16 bits of
+ * the result. xt-xcc doesn't use an extui, but assumes the
+ * __asm__ macro follows convention that the upper 16 bits of an
+ * 'unsigned short' result are still zero. This macro doesn't
+ * follow convention; indeed, it leaves garbage in the upport 16
+ * bits of the register.
+ *
+ * Declaring the temporary variables 'res' and 'tmp' to be 32-bit
+ * types while the return type of the function is a 16-bit type
+ * forces both compilers to insert exactly one extui instruction
+ * (or equivalent) to mask off the upper 16 bits.
+ */
+
+ __u32 res;
+ __u32 tmp;
+
+ __asm__("extui %1, %2, 8, 8\n\t"
+ "slli %0, %2, 8\n\t"
+ "or %0, %0, %1\n"
+ : "=&a" (res), "=&a" (tmp)
+ : "a" (x)
+ );
+
+ return res;
+}
+
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+# define __BYTEORDER_HAS_U64__
+# define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __XTENSA_EL__
+# include <linux/byteorder/little_endian.h>
+#elif defined(__XTENSA_EB__)
+# include <linux/byteorder/big_endian.h>
+#else
+# error processor byte order undefined!
+#endif
+
+#endif /* _XTENSA_BYTEORDER_H */
diff --git a/arch/xtensa/include/asm/cache.h b/arch/xtensa/include/asm/cache.h
new file mode 100644
index 0000000000..08c534ca01
--- /dev/null
+++ b/arch/xtensa/include/asm/cache.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2009 Tensilica Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _XTENSA_CACHE_H
+#define _XTENSA_CACHE_H
+
+#include <asm/arch/core.h>
+
+#define ARCH_DMA_MINALIGN XCHAL_DCACHE_LINESIZE
+
+#ifndef __ASSEMBLY__
+
+void __flush_dcache_all(void);
+void __flush_invalidate_dcache_range(unsigned long addr, unsigned long size);
+void __invalidate_dcache_all(void);
+void __invalidate_dcache_range(unsigned long addr, unsigned long size);
+
+void __invalidate_icache_all(void);
+void __invalidate_icache_range(unsigned long addr, unsigned long size);
+
+#endif
+
+#endif /* _XTENSA_CACHE_H */
diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h
new file mode 100644
index 0000000000..342a8177e4
--- /dev/null
+++ b/arch/xtensa/include/asm/cacheasm.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2006 Tensilica Inc.
+ * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_CACHEASM_H
+#define _XTENSA_CACHEASM_H
+
+#include <asm/cache.h>
+#include <asm/asmmacro.h>
+#include <linux/stringify.h>
+
+#define PAGE_SIZE 4096
+#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
+#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
+#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
+#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
+
+/*
+ * Define cache functions as macros here so that they can be used
+ * by the kernel and boot loader. We should consider moving them to a
+ * library that can be linked by both.
+ *
+ * Locking
+ *
+ * ___unlock_dcache_all
+ * ___unlock_icache_all
+ *
+ * Flush and invaldating
+ *
+ * ___flush_invalidate_dcache_{all|range|page}
+ * ___flush_dcache_{all|range|page}
+ * ___invalidate_dcache_{all|range|page}
+ * ___invalidate_icache_{all|range|page}
+ *
+ */
+
+ .macro __loop_cache_all ar at insn size line_width
+
+ movi \ar, 0
+
+ __loopi \ar, \at, \size, (4 << (\line_width))
+
+ \insn \ar, 0 << (\line_width)
+ \insn \ar, 1 << (\line_width)
+ \insn \ar, 2 << (\line_width)
+ \insn \ar, 3 << (\line_width)
+
+ __endla \ar, \at, 4 << (\line_width)
+
+ .endm
+
+
+ .macro __loop_cache_range ar as at insn line_width
+
+ extui \at, \ar, 0, \line_width
+ add \as, \as, \at
+
+ __loops \ar, \as, \at, \line_width
+ \insn \ar, 0
+ __endla \ar, \at, (1 << (\line_width))
+
+ .endm
+
+
+ .macro __loop_cache_page ar at insn line_width
+
+ __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width)
+
+ \insn \ar, 0 << (\line_width)
+ \insn \ar, 1 << (\line_width)
+ \insn \ar, 2 << (\line_width)
+ \insn \ar, 3 << (\line_width)
+
+ __endla \ar, \at, 4 << (\line_width)
+
+ .endm
+
+
+ .macro ___unlock_dcache_all ar at
+
+#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
+ __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
+#endif
+
+ .endm
+
+
+ .macro ___unlock_icache_all ar at
+
+#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
+ __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
+#endif
+
+ .endm
+
+
+ .macro ___flush_invalidate_dcache_all ar at
+
+#if XCHAL_DCACHE_SIZE
+ __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
+#endif
+
+ .endm
+
+
+ .macro ___flush_dcache_all ar at
+
+#if XCHAL_DCACHE_SIZE
+ __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
+#endif
+
+ .endm
+
+
+ .macro ___invalidate_dcache_all ar at
+
+#if XCHAL_DCACHE_SIZE
+ __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
+ XCHAL_DCACHE_LINEWIDTH
+#endif
+
+ .endm
+
+
+ .macro ___invalidate_icache_all ar at
+
+#if XCHAL_ICACHE_SIZE
+ __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
+ XCHAL_ICACHE_LINEWIDTH
+#endif
+
+ .endm
+
+
+
+ .macro ___flush_invalidate_dcache_range ar as at
+
+#if XCHAL_DCACHE_SIZE
+ __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
+#endif
+
+ .endm
+
+
+ .macro ___flush_dcache_range ar as at
+
+#if XCHAL_DCACHE_SIZE
+ __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
+#endif
+
+ .endm
+
+
+ .macro ___invalidate_dcache_range ar as at
+
+#if XCHAL_DCACHE_SIZE
+ __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
+#endif
+
+ .endm
+
+
+ .macro ___invalidate_icache_range ar as at
+
+#if XCHAL_ICACHE_SIZE
+ __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
+#endif
+
+ .endm
+
+
+
+ .macro ___flush_invalidate_dcache_page ar as
+
+#if XCHAL_DCACHE_SIZE
+ __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
+#endif
+
+ .endm
+
+
+ .macro ___flush_dcache_page ar as
+
+#if XCHAL_DCACHE_SIZE
+ __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
+#endif
+
+ .endm
+
+
+ .macro ___invalidate_dcache_page ar as
+
+#if XCHAL_DCACHE_SIZE
+ __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
+#endif
+
+ .endm
+
+
+ .macro ___invalidate_icache_page ar as
+
+#if XCHAL_ICACHE_SIZE
+ __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
+#endif
+
+ .endm
+
+#endif /* _XTENSA_CACHEASM_H */
diff --git a/arch/xtensa/include/asm/config.h b/arch/xtensa/include/asm/config.h
new file mode 100644
index 0000000000..db1ea87c30
--- /dev/null
+++ b/arch/xtensa/include/asm/config.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2009 Tensilica Inc.
+ * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#include <asm/arch/core.h>
+
+#define CONFIG_LMB
+
+/*
+ * Make boot parameters available in the MMUv2 virtual memory layout by
+ * restricting used physical memory to the first 128MB.
+ */
+#if XCHAL_HAVE_PTP_MMU
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED (128 << 20)
+#endif
+
+#endif
diff --git a/arch/xtensa/include/asm/errno.h b/arch/xtensa/include/asm/errno.h
new file mode 100644
index 0000000000..4c82b503d9
--- /dev/null
+++ b/arch/xtensa/include/asm/errno.h
@@ -0,0 +1 @@
+#include <asm-generic/errno.h>
diff --git a/arch/xtensa/include/asm/global_data.h b/arch/xtensa/include/asm/global_data.h
new file mode 100644
index 0000000000..45693457ad
--- /dev/null
+++ b/arch/xtensa/include/asm/global_data.h
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2007, Tensilica Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_GBL_DATA_H
+#define _XTENSA_GBL_DATA_H
+
+/* Architecture-specific global data */
+
+struct arch_global_data {
+ unsigned long cpu_clk;
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR extern gd_t *gd
+
+#endif /* _XTENSA_GBL_DATA_H */
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
new file mode 100644
index 0000000000..e34d6e1d7f
--- /dev/null
+++ b/arch/xtensa/include/asm/io.h
@@ -0,0 +1,148 @@
+/*
+ * IO header file
+ *
+ * Copyright (C) 2001-2007 Tensilica Inc.
+ * Based on the Linux/Xtensa version of this header.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_IO_H
+#define _XTENSA_IO_H
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+/*
+ * swap functions to change byte order from little-endian to big-endian and
+ * vice versa.
+ */
+
+static inline unsigned short _swapw(unsigned short v)
+{
+ return (v << 8) | (v >> 8);
+}
+
+static inline unsigned int _swapl(unsigned int v)
+{
+ return (v << 24) | ((v & 0xff00) << 8) |
+ ((v >> 8) & 0xff00) | (v >> 24);
+}
+
+/*
+ * Generic I/O
+ */
+
+#define readb(addr) \
+ ({ unsigned char __v = (*(volatile unsigned char *)(addr)); __v; })
+#define readw(addr) \
+ ({ unsigned short __v = (*(volatile unsigned short *)(addr)); __v; })
+#define readl(addr) \
+ ({ unsigned int __v = (*(volatile unsigned int *)(addr)); __v; })
+#define writeb(b, addr) (void)((*(volatile unsigned char *)(addr)) = (b))
+#define writew(b, addr) (void)((*(volatile unsigned short *)(addr)) = (b))
+#define writel(b, addr) (void)((*(volatile unsigned int *)(addr)) = (b))
+
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+
+/* These are the definitions for the x86 IO instructions
+ * inb/inw/inl/outb/outw/outl, the "string" versions
+ * insb/insw/insl/outsb/outsw/outsl, and the "pausing" versions
+ * inb_p/inw_p/...
+ * The macros don't do byte-swapping.
+ */
+
+#define inb(port) readb((u8 *)((port)))
+#define outb(val, port) writeb((val), (u8 *)((unsigned long)(port)))
+#define inw(port) readw((u16 *)((port)))
+#define outw(val, port) writew((val), (u16 *)((unsigned long)(port)))
+#define inl(port) readl((u32 *)((port)))
+#define outl(val, port) writel((val), (u32 *)((unsigned long)(port)))
+
+#define inb_p(port) inb((port))
+#define outb_p(val, port) outb((val), (port))
+#define inw_p(port) inw((port))
+#define outw_p(val, port) outw((val), (port))
+#define inl_p(port) inl((port))
+#define outl_p(val, port) outl((val), (port))
+
+void insb(unsigned long port, void *dst, unsigned long count);
+void insw(unsigned long port, void *dst, unsigned long count);
+void insl(unsigned long port, void *dst, unsigned long count);
+void outsb(unsigned long port, const void *src, unsigned long count);
+void outsw(unsigned long port, const void *src, unsigned long count);
+void outsl(unsigned long port, const void *src, unsigned long count);
+
+#define IO_SPACE_LIMIT ~0
+
+#define memset_io(a, b, c) memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
+
+/* At this point the Xtensa doesn't provide byte swap instructions */
+
+#ifdef __XTENSA_EB__
+# define in_8(addr) (*(u8 *)(addr))
+# define in_le16(addr) _swapw(*(u16 *)(addr))
+# define in_le32(addr) _swapl(*(u32 *)(addr))
+# define out_8(b, addr) *(u8 *)(addr) = (b)
+# define out_le16(b, addr) *(u16 *)(addr) = _swapw(b)
+# define out_le32(b, addr) *(u32 *)(addr) = _swapl(b)
+#elif defined(__XTENSA_EL__)
+# define in_8(addr) (*(u8 *)(addr))
+# define in_le16(addr) (*(u16 *)(addr))
+# define in_le32(addr) (*(u32 *)(addr))
+# define out_8(b, addr) *(u8 *)(addr) = (b)
+# define out_le16(b, addr) *(u16 *)(addr) = (b)
+# define out_le32(b, addr) *(u32 *)(addr) = (b)
+#else
+# error processor byte order undefined!
+#endif
+
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem access
+ */
+#define xlate_dev_mem_ptr(p) __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p) p
+
+#define MAP_NOCACHE (0)
+#define MAP_WRCOMBINE (0)
+#define MAP_WRBACK (0)
+#define MAP_WRTHROUGH (0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+ return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+}
+
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+ return (phys_addr_t)((unsigned long)vaddr);
+}
+
+/*
+ * Dummy function to keep U-Boot's cfi_flash.c driver happy.
+ */
+static inline void sync(void)
+{
+}
+
+#endif /* _XTENSA_IO_H */
diff --git a/arch/xtensa/include/asm/ldscript.h b/arch/xtensa/include/asm/ldscript.h
new file mode 100644
index 0000000000..62a1c05268
--- /dev/null
+++ b/arch/xtensa/include/asm/ldscript.h
@@ -0,0 +1,222 @@
+/*
+ * (C) Copyright 2007 Tensilica, Inc.
+ * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_LDSCRIPT_H
+#define _XTENSA_LDSCRIPT_H
+
+/*
+ * This linker script is pre-processed with CPP to avoid hard-coding
+ * addresses that depend on the Xtensa core configuration, because
+ * this FPGA board can be used with a huge variety of Xtensa cores.
+ */
+
+#include <asm/arch/core.h>
+#include <asm/addrspace.h>
+
+#define ALIGN_LMA 4
+#define LMA_EQ_VMA
+#define FORCE_OUTPUT . = .
+#define FOLLOWING(sec) \
+ AT(((LOADADDR(sec) + SIZEOF(sec) + ALIGN_LMA-1)) & ~(ALIGN_LMA-1))
+
+/*
+ * Specify an output section that will be added to the ROM store table
+ * (PACKED_SECTION) or one that will be resident in ROM (RESIDENT_SECTION).
+ * 'symname' is a base name for section boundary symbols *_start & *_end.
+ * 'lma' is the load address at which a section will be packed in ROM.
+ * 'region' is the basename identifying a memory region and program header.
+ * 'keep' prevents removal of empty sections (must be 'KEEP' or 'NOKEEP').
+ */
+
+#define RELOCATE1(_sec_) \
+ LONG(_##_sec_##_start); \
+ LONG(_##_sec_##_end); \
+ LONG(LOADADDR(.##_sec_));
+
+#define RELOCATE2(_sym_, _sec_) \
+ LONG(_##_sym_##_##_sec_##_start); \
+ LONG(_##_sym_##_##_sec_##_end); \
+ LONG(LOADADDR(.##_sym_##.##_sec_));
+
+#define SECTION_VECTOR(_sym_, _sec_, _vma_, _lma_) \
+.##_sym_##.##_sec_ _vma_ : _lma_ \
+{ \
+ . = ALIGN(4); \
+ _##_sym_##_##_sec_##_start = ABSOLUTE(.); \
+ KEEP(*(.##_sym_##.##_sec_)) \
+ _##_sym_##_##_sec_##_end = ABSOLUTE(.); \
+}
+
+/* In MMU configs there are two aliases of SYSROM, cached and uncached.
+ * For various reasons it is simpler to use the uncached mapping for load
+ * addresses, so ROM sections end up contiguous with the reset vector and
+ * we get a compact binary image. However we can gain performance by doing
+ * the unpacking from the cached ROM mapping. So we adjust all the load
+ * addresses in the ROM store table with an offset to the cached mapping,
+ * including the symbols referring to the ROM store table itself.
+ */
+
+#define SECTION_ResetVector(_vma_, _lma_) \
+ .ResetVector.text _vma_ : _lma_ \
+ { \
+ FORCE_OUTPUT; \
+ KEEP(*(.ResetVector.text)); \
+ KEEP(*(.reset.literal .reset.text)) \
+ }
+
+#define SECTION_text(_vma_, _lma_) \
+ .text _vma_ : _lma_ \
+ { \
+ _text_start = ABSOLUTE(.); \
+ *(.literal .text) \
+ *(.literal.* .text.* .stub) \
+ *(.gnu.warning .gnu.linkonce.literal.*) \
+ *(.gnu.linkonce.t.*.literal .gnu.linkonce.t.*) \
+ *(.fini.literal) \
+ *(.fini) \
+ *(.gnu.version) \
+ _text_end = ABSOLUTE(.); \
+ }
+
+#define SECTION_rodata(_vma_, _lma_) \
+ .rodata _vma_ : _lma_ \
+ { \
+ _rodata_start = ABSOLUTE(.); \
+ *(.rodata) \
+ *(.rodata.*) \
+ *(.dtb.init.rodata) \
+ *(.gnu.linkonce.r.*) \
+ *(.rodata1) \
+ __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); \
+ *(.xt_except_table) \
+ *(.gcc_except_table) \
+ *(.gnu.linkonce.e.*) \
+ *(.gnu.version_r) \
+ . = ALIGN(16); \
+ _rodata_end = ABSOLUTE(.); \
+ }
+
+#define SECTION_u_boot_list(_vma_, _lma_) \
+ .u_boot_list _vma_ : _lma_ \
+ { \
+ _u_boot_list_start = ABSOLUTE(.); \
+ KEEP(*(SORT(.u_boot_list*))); \
+ _u_boot_list_end = ABSOLUTE(.); \
+ }
+
+#define SECTION_data(_vma_, _lma_) \
+ .data _vma_ : _lma_ \
+ { \
+ _data_start = ABSOLUTE(.); \
+ *(.data) \
+ *(.data.*) \
+ *(.gnu.linkonce.d.*) \
+ *(.data1) \
+ *(.sdata) \
+ *(.sdata.*) \
+ *(.gnu.linkonce.s.*) \
+ *(.sdata2) \
+ *(.sdata2.*) \
+ *(.gnu.linkonce.s2.*) \
+ *(.jcr) \
+ *(.eh_frame) \
+ *(.dynamic) \
+ *(.gnu.version_d) \
+ _data_end = ABSOLUTE(.); \
+ }
+
+#define SECTION_lit4(_vma_, _lma_) \
+ .lit4 _vma_ : _lma_ \
+ { \
+ _lit4_start = ABSOLUTE(.); \
+ *(*.lit4) \
+ *(.gnu.linkonce.lit4.*) \
+ _lit4_end = ABSOLUTE(.); \
+ }
+
+#define SECTION_bss(_vma_, _lma_) \
+ .bss _vma_ : _lma_ \
+ { \
+ . = ALIGN(8); \
+ _bss_start = ABSOLUTE(.); \
+ __bss_start = ABSOLUTE(.); \
+ *(.dynsbss) \
+ *(.sbss) \
+ *(.sbss.*) \
+ *(.gnu.linkonce.sb.*) \
+ *(.scommon) \
+ *(.sbss2) \
+ *(.sbss2.*) \
+ *(.gnu.linkonce.sb2.*) \
+ *(.dynbss) \
+ *(.bss) \
+ *(.bss.*) \
+ *(.gnu.linkonce.b.*) \
+ *(COMMON) \
+ *(.sram.bss) \
+ . = ALIGN(8); \
+ _bss_end = ABSOLUTE(.); \
+ __bss_end = ABSOLUTE(.); \
+ _end = ALIGN(0x8); \
+ PROVIDE(end = ALIGN(0x8)); \
+ _stack_sentry = ALIGN(0x8); \
+ }
+
+#define SECTION_debug \
+ .debug 0 : { *(.debug) } \
+ .line 0 : { *(.line) } \
+ .debug_srcinfo 0 : { *(.debug_srcinfo) } \
+ .debug_sfnames 0 : { *(.debug_sfnames) } \
+ .debug_aranges 0 : { *(.debug_aranges) } \
+ .debug_pubnames 0 : { *(.debug_pubnames) } \
+ .debug_info 0 : { *(.debug_info) } \
+ .debug_abbrev 0 : { *(.debug_abbrev) } \
+ .debug_line 0 : { *(.debug_line) } \
+ .debug_frame 0 : { *(.debug_frame) } \
+ .debug_str 0 : { *(.debug_str) } \
+ .debug_loc 0 : { *(.debug_loc) } \
+ .debug_macinfo 0 : { *(.debug_macinfo) } \
+ .debug_weaknames 0 : { *(.debug_weaknames) } \
+ .debug_funcnames 0 : { *(.debug_funcnames) } \
+ .debug_typenames 0 : { *(.debug_typenames) } \
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+#define SECTION_xtensa \
+ .xt.insn 0 : \
+ { \
+ KEEP (*(.xt.insn)) \
+ KEEP (*(.gnu.linkonce.x.*)) \
+ } \
+ .xt.prop 0 : \
+ { \
+ KEEP (*(.xt.prop)) \
+ KEEP (*(.xt.prop.*)) \
+ KEEP (*(.gnu.linkonce.prop.*)) \
+ } \
+ .xt.lit 0 : \
+ { \
+ KEEP (*(.xt.lit)) \
+ KEEP (*(.xt.lit.*)) \
+ KEEP (*(.gnu.linkonce.p.*)) \
+ } \
+ .xt.profile_range 0 : \
+ { \
+ KEEP (*(.xt.profile_range)) \
+ KEEP (*(.gnu.linkonce.profile_range.*)) \
+ } \
+ .xt.profile_ranges 0 : \
+ { \
+ KEEP (*(.xt.profile_ranges)) \
+ KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) \
+ } \
+ .xt.profile_files 0 : \
+ { \
+ KEEP (*(.xt.profile_files)) \
+ KEEP (*(.gnu.linkonce.xt.profile_files.*)) \
+ }
+
+#endif /* _XTENSA_LDSCRIPT_H */
diff --git a/arch/xtensa/include/asm/linkage.h b/arch/xtensa/include/asm/linkage.h
new file mode 100644
index 0000000000..3f46161a9f
--- /dev/null
+++ b/arch/xtensa/include/asm/linkage.h
@@ -0,0 +1,4 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#endif
diff --git a/arch/xtensa/include/asm/misc.h b/arch/xtensa/include/asm/misc.h
new file mode 100644
index 0000000000..5a2708fbef
--- /dev/null
+++ b/arch/xtensa/include/asm/misc.h
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2008, Tensilica Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _XTENSA_MISC_H
+#define _XTENSA_MISC_H
+
+/* Used in cpu/xtensa/cpu.c */
+void board_reset(void);
+
+#endif /* _XTENSA_MISC_H */
diff --git a/arch/xtensa/include/asm/posix_types.h b/arch/xtensa/include/asm/posix_types.h
new file mode 100644
index 0000000000..821115c006
--- /dev/null
+++ b/arch/xtensa/include/asm/posix_types.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2007, Tensilica Inc.
+ *
+ * Based on the ARM version: Copyright (C) 1996-1998 Russell King.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _XTENSA_POSIX_TYPES_H
+#define _XTENSA_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc. Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short __kernel_dev_t;
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned short __kernel_ipc_pid_t;
+typedef unsigned short __kernel_uid_t;
+typedef unsigned short __kernel_gid_t;
+typedef unsigned int __kernel_size_t;
+typedef int __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_daddr_t;
+typedef char * __kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+ int val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+ int __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef __FD_SET
+#define __FD_SET(fd, fdsetp) \
+ (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef __FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+ (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef __FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+ ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef __FD_ZERO
+#define __FD_ZERO(fdsetp) \
+ (memset(fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif
+
+#endif /* _XTENSA_POSIX_TYPES_H */
diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h
new file mode 100644
index 0000000000..8822f80f8d
--- /dev/null
+++ b/arch/xtensa/include/asm/processor.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 1997 Tensilica Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_PROCESSOR_H
+#define _XTENSA_PROCESSOR_H
+
+
+#endif /* _XTENSA_PROCESSOR_H */
diff --git a/arch/xtensa/include/asm/ptrace.h b/arch/xtensa/include/asm/ptrace.h
new file mode 100644
index 0000000000..d187dbf4c9
--- /dev/null
+++ b/arch/xtensa/include/asm/ptrace.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2001 - 2007 Tensilica Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_PTRACE_H
+#define _XTENSA_PTRACE_H
+
+#include <compiler.h>
+
+/*
+ * Kernel stack
+ *
+ * +-----------------------+ -------- STACK_SIZE
+ * | register file | |
+ * +-----------------------+ |
+ * | struct pt_regs | |
+ * +-----------------------+ | ------ PT_REGS_OFFSET
+ * double : 16 bytes spill area : | ^
+ * exception :- - - - - - - - - - - -: | |
+ * frame : struct pt_regs : | |
+ * :- - - - - - - - - - - -: | |
+ * | | | |
+ * | memory stack | | |
+ * | | | |
+ * ~ ~ ~ ~
+ * ~ ~ ~ ~
+ * | | | |
+ * | | | |
+ * +-----------------------+ | | --- STACK_BIAS
+ * | struct task_struct | | | ^
+ * current --> +-----------------------+ | | |
+ * | struct thread_info | | | |
+ * +-----------------------+ --------
+ */
+
+#define KERNEL_STACK_SIZE (2 * PAGE_SIZE)
+
+/* Offsets for exception_handlers[] (3 x 64-entries x 4-byte tables) */
+
+#define EXC_TABLE_KSTK 0x004 /* Kernel Stack */
+#define EXC_TABLE_DOUBLE_SAVE 0x008 /* Double exception save area for a0 */
+#define EXC_TABLE_FIXUP 0x00c /* Fixup handler */
+#define EXC_TABLE_PARAM 0x010 /* For passing a parameter to fixup */
+#define EXC_TABLE_SYSCALL_SAVE 0x014 /* For fast syscall handler */
+#define EXC_TABLE_FAST_USER 0x100 /* Fast user exception handler */
+#define EXC_TABLE_FAST_KERNEL 0x200 /* Fast kernel exception handler */
+#define EXC_TABLE_DEFAULT 0x300 /* Default C-Handler */
+#define EXC_TABLE_SIZE 0x400
+
+/* Registers used by strace */
+
+#define REG_A_BASE 0xfc000000
+#define REG_AR_BASE 0x04000000
+#define REG_PC 0x14000000
+#define REG_PS 0x080000e6
+#define REG_WB 0x08000048
+#define REG_WS 0x08000049
+#define REG_LBEG 0x08000000
+#define REG_LEND 0x08000001
+#define REG_LCOUNT 0x08000002
+#define REG_SAR 0x08000003
+#define REG_DEPC 0x080000c0
+#define REG_EXCCAUSE 0x080000e8
+#define REG_EXCVADDR 0x080000ee
+#define SYSCALL_NR 0x1
+
+#define AR_REGNO_TO_A_REGNO(ar, wb) (ar - wb*4) & ~(XCHAL_NUM_AREGS - 1)
+
+/* Other PTRACE_ values defined in <linux/ptrace.h> using values 0-9,16,17,24 */
+
+#define PTRACE_GETREGS 12
+#define PTRACE_SETREGS 13
+#define PTRACE_GETFPREGS 14
+#define PTRACE_SETFPREGS 15
+#define PTRACE_GETFPREGSIZE 18
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_regs {
+ unsigned long pc; /* 4 */
+ unsigned long ps; /* 8 */
+ unsigned long depc; /* 12 */
+ unsigned long exccause; /* 16 */
+ unsigned long excvaddr; /* 20 */
+ unsigned long debugcause; /* 24 */
+ unsigned long wmask; /* 28 */
+ unsigned long lbeg; /* 32 */
+ unsigned long lend; /* 36 */
+ unsigned long lcount; /* 40 */
+ unsigned long sar; /* 44 */
+ unsigned long windowbase; /* 48 */
+ unsigned long windowstart; /* 52 */
+ unsigned long syscall; /* 56 */
+ unsigned long icountlevel; /* 60 */
+ int reserved[1]; /* 64 */
+
+ /* Make sure the areg field is 16 bytes aligned */
+ int align[0] __aligned(16);
+
+ /* current register frame.
+ * Note: The ESF for kernel exceptions ends after 16 registers!
+ */
+ unsigned long areg[16]; /* 128 (64) */
+};
+
+#ifdef __KERNEL__
+
+# define task_pt_regs(tsk) ((struct pt_regs *) \
+ (task_stack_page(tsk) + KERNEL_STACK_SIZE - (XCHAL_NUM_AREGS-16)*4) - 1)
+# define user_mode(regs) (((regs)->ps & 0x00000020) != 0)
+# define instruction_pointer(regs) ((regs)->pc)
+void show_regs(struct pt_regs *);
+
+# ifndef CONFIG_SMP
+# define profile_pc(regs) instruction_pointer(regs)
+# endif
+#endif /* __KERNEL__ */
+
+#else /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+# include <asm/asm-offsets.h>
+#define PT_REGS_OFFSET (KERNEL_STACK_SIZE - PT_USER_SIZE)
+#endif
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _XTENSA_PTRACE_H */
diff --git a/arch/xtensa/include/asm/regs.h b/arch/xtensa/include/asm/regs.h
new file mode 100644
index 0000000000..0a82a221dd
--- /dev/null
+++ b/arch/xtensa/include/asm/regs.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2006 Tensilica, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_REGS_H
+#define _XTENSA_REGS_H
+
+/* Special registers */
+
+#define IBREAKA 128
+#define DBREAKA 144
+#define DBREAKC 160
+
+/* Special names for read-only and write-only interrupt registers */
+
+#define INTREAD 226
+#define INTSET 226
+#define INTCLEAR 227
+
+/* EXCCAUSE register fields */
+
+#define EXCCAUSE_EXCCAUSE_SHIFT 0
+#define EXCCAUSE_EXCCAUSE_MASK 0x3F
+
+#define EXCCAUSE_ILLEGAL_INSTRUCTION 0
+#define EXCCAUSE_SYSTEM_CALL 1
+#define EXCCAUSE_INSTRUCTION_FETCH_ERROR 2
+#define EXCCAUSE_LOAD_STORE_ERROR 3
+#define EXCCAUSE_LEVEL1_INTERRUPT 4
+#define EXCCAUSE_ALLOCA 5
+#define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6
+#define EXCCAUSE_SPECULATION 7
+#define EXCCAUSE_PRIVILEGED 8
+#define EXCCAUSE_UNALIGNED 9
+#define EXCCAUSE_INSTR_DATA_ERROR 12
+#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13
+#define EXCCAUSE_INSTR_ADDR_ERROR 14
+#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15
+#define EXCCAUSE_ITLB_MISS 16
+#define EXCCAUSE_ITLB_MULTIHIT 17
+#define EXCCAUSE_ITLB_PRIVILEGE 18
+#define EXCCAUSE_ITLB_SIZE_RESTRICTION 19
+#define EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20
+#define EXCCAUSE_DTLB_MISS 24
+#define EXCCAUSE_DTLB_MULTIHIT 25
+#define EXCCAUSE_DTLB_PRIVILEGE 26
+#define EXCCAUSE_DTLB_SIZE_RESTRICTION 27
+#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28
+#define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29
+#define EXCCAUSE_COPROCESSOR0_DISABLED 32
+#define EXCCAUSE_COPROCESSOR1_DISABLED 33
+#define EXCCAUSE_COPROCESSOR2_DISABLED 34
+#define EXCCAUSE_COPROCESSOR3_DISABLED 35
+#define EXCCAUSE_COPROCESSOR4_DISABLED 36
+#define EXCCAUSE_COPROCESSOR5_DISABLED 37
+#define EXCCAUSE_COPROCESSOR6_DISABLED 38
+#define EXCCAUSE_COPROCESSOR7_DISABLED 39
+#define EXCCAUSE_LAST 63
+
+/* PS register fields */
+
+#define PS_WOE_BIT 18
+#define PS_CALLINC_SHIFT 16
+#define PS_CALLINC_MASK 0x00030000
+#define PS_OWB_SHIFT 8
+#define PS_OWB_MASK 0x00000F00
+#define PS_RING_SHIFT 6
+#define PS_RING_MASK 0x000000C0
+#define PS_UM_BIT 5
+#define PS_EXCM_BIT 4
+#define PS_INTLEVEL_SHIFT 0
+#define PS_INTLEVEL_MASK 0x0000000F
+
+/* DBREAKCn register fields */
+
+#define DBREAKC_MASK_BIT 0
+#define DBREAKC_MASK_MASK 0x0000003F
+#define DBREAKC_LOAD_BIT 30
+#define DBREAKC_LOAD_MASK 0x40000000
+#define DBREAKC_STOR_BIT 31
+#define DBREAKC_STOR_MASK 0x80000000
+
+/* DEBUGCAUSE register fields */
+
+#define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */
+#define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */
+#define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */
+#define DEBUGCAUSE_DBREAK_BIT 2 /* DBREAK match */
+#define DEBUGCAUSE_IBREAK_BIT 1 /* IBREAK match */
+#define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */
+
+#endif /* _XTENSA_SPECREG_H */
+
diff --git a/arch/xtensa/include/asm/relocate.h b/arch/xtensa/include/asm/relocate.h
new file mode 100644
index 0000000000..9c4ce23988
--- /dev/null
+++ b/arch/xtensa/include/asm/relocate.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Cadence Design Systems Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_XTENSA_RELOCATE_H
+#define _ASM_XTENSA_RELOCATE_H
+
+#include <common.h>
+
+int clear_bss(void);
+
+#endif /* _ASM_XTENSA_RELOCATE_H */
diff --git a/arch/xtensa/include/asm/sections.h b/arch/xtensa/include/asm/sections.h
new file mode 100644
index 0000000000..2309b14638
--- /dev/null
+++ b/arch/xtensa/include/asm/sections.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_XTENSA_SECTIONS_H
+#define __ASM_XTENSA_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/arch/xtensa/include/asm/string.h b/arch/xtensa/include/asm/string.h
new file mode 100644
index 0000000000..65a3601674
--- /dev/null
+++ b/arch/xtensa/include/asm/string.h
@@ -0,0 +1,10 @@
+#ifndef _XTENSA_STRING_H
+#define _XTENSA_STRING_H
+
+/*
+ * Use the generic string functions in U-Boot's lib_generic.
+ * In the boot loader we care about compactness more than performance.
+ * Prototypes will be taken from <linux/string.h>
+ */
+
+#endif /* _XTENSA_STRING_H */
diff --git a/arch/xtensa/include/asm/system.h b/arch/xtensa/include/asm/system.h
new file mode 100644
index 0000000000..5b710089c1
--- /dev/null
+++ b/arch/xtensa/include/asm/system.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2016 Cadence Design Systems Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_SYSTEM_H
+#define _XTENSA_SYSTEM_H
+
+#include <asm/arch/core.h>
+
+#if XCHAL_HAVE_INTERRUPTS
+#define local_irq_save(flags) \
+ __asm__ __volatile__ ("rsil %0, %1" \
+ : "=a"(flags) \
+ : "I"(XCHAL_EXCM_LEVEL) \
+ : "memory")
+#define local_irq_restore(flags) \
+ __asm__ __volatile__ ("wsr %0, ps\n\t" \
+ "rsync" \
+ :: "a"(flags) : "memory")
+#else
+#define local_irq_save(flags) ((void)(flags))
+#define local_irq_restore(flags) ((void)(flags))
+#endif
+
+#endif
diff --git a/arch/xtensa/include/asm/types.h b/arch/xtensa/include/asm/types.h
new file mode 100644
index 0000000000..f7eda9dc59
--- /dev/null
+++ b/arch/xtensa/include/asm/types.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 1997 Tensilica Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _XTENSA_TYPES_H
+#define _XTENSA_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+
+#endif /* __KERNEL__ */
+
+#endif /* _XTENSA_TYPES_H */
diff --git a/arch/xtensa/include/asm/u-boot.h b/arch/xtensa/include/asm/u-boot.h
new file mode 100644
index 0000000000..cfdc0367b3
--- /dev/null
+++ b/arch/xtensa/include/asm/u-boot.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2007, Tensilica Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _XTENSA_U_BOOT_H
+#define _XTENSA_U_BOOT_H
+
+#ifdef CONFIG_SYS_GENERIC_BOARD
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#else
+
+#ifndef __ASSEMBLY__
+typedef struct bd_info {
+ int bi_baudrate; /* serial console baudrate */
+ unsigned long bi_ip_addr; /* IP Address */
+ unsigned char bi_enetaddr[6]; /* Ethernet adress */
+ unsigned long bi_boot_params; /* where this board expects params */
+ unsigned long bi_memstart; /* start of DRAM memory VA */
+ unsigned long bi_memsize; /* size of DRAM memory in bytes */
+ unsigned long bi_flashstart; /* start of FLASH memory */
+ unsigned long bi_flashsize; /* size of FLASH memory */
+ unsigned long bi_flashoffset; /* offset to skip UBoot image */
+} bd_t;
+#endif /* __ ASSEMBLY__ */
+
+#endif /* CONFIG_SYS_GENERIC_BOARD */
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_XTENSA
+
+#endif /* _XTENSA_U_BOOT_H */
diff --git a/arch/xtensa/include/asm/unaligned.h b/arch/xtensa/include/asm/unaligned.h
new file mode 100644
index 0000000000..536f3642e3
--- /dev/null
+++ b/arch/xtensa/include/asm/unaligned.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_XTENSA_UNALIGNED_H
+#define _ASM_XTENSA_UNALIGNED_H
+
+#include <asm-generic/unaligned.h>
+
+#endif /* _ASM_XTENSA_UNALIGNED_H */