diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/i386/cpu/cpu.c | 13 | ||||
| -rw-r--r-- | arch/i386/cpu/interrupts.c | 3 | ||||
| -rw-r--r-- | arch/i386/cpu/sc520/sc520.c | 7 | ||||
| -rw-r--r-- | arch/i386/cpu/start.S | 3 | ||||
| -rw-r--r-- | arch/i386/cpu/start16.S | 5 | ||||
| -rw-r--r-- | arch/i386/include/asm/processor-flags.h | 100 |
6 files changed, 121 insertions, 10 deletions
diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c index 1dcbb983f5..e96380aa92 100644 --- a/arch/i386/cpu/cpu.c +++ b/arch/i386/cpu/cpu.c @@ -36,6 +36,7 @@ #include <common.h> #include <command.h> #include <asm/processor.h> +#include <asm/processor-flags.h> #include <asm/interrupt.h> /* Constructor for a conventional segment GDT (or LDT) entry */ @@ -88,12 +89,16 @@ static void reload_gdt(void) int cpu_init_f(void) { + const u32 em_rst = ~X86_CR0_EM; + const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; + /* initialize FPU, reset EM, set MP and NE */ asm ("fninit\n" \ - "movl %cr0, %eax\n" \ - "andl $~0x4, %eax\n" \ - "orl $0x22, %eax\n" \ - "movl %eax, %cr0\n" ); + "movl %%cr0, %%eax\n" \ + "andl %0, %%eax\n" \ + "orl %1, %%eax\n" \ + "movl %%eax, %%cr0\n" \ + : : "i" (em_rst), "i" (mp_ne_set) : "eax"); return 0; } diff --git a/arch/i386/cpu/interrupts.c b/arch/i386/cpu/interrupts.c index cdff3d934d..1cefe02c86 100644 --- a/arch/i386/cpu/interrupts.c +++ b/arch/i386/cpu/interrupts.c @@ -30,6 +30,7 @@ #include <common.h> #include <asm/interrupt.h> #include <asm/io.h> +#include <asm/processor-flags.h> #define DECLARE_INTERRUPT(x) \ ".globl irq_"#x"\n" \ @@ -237,7 +238,7 @@ int disable_interrupts(void) asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : ); - return (flags&0x200); /* IE flags is bit 9 */ + return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */ } /* IRQ Low-Level Service Routine */ diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 7acd471d96..21037d29d7 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -26,6 +26,7 @@ #include <common.h> #include <asm/io.h> +#include <asm/processor-flags.h> #include <asm/ic/sc520.h> DECLARE_GLOBAL_DATA_PTR; @@ -41,6 +42,8 @@ volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000; void init_sc520(void) { + const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD); + /* * Set the UARTxCTL register at it's slower, * baud clock giving us a 1.8432 MHz reference @@ -84,8 +87,8 @@ void init_sc520(void) /* turn on the cache and disable write through */ asm("movl %%cr0, %%eax\n" - "andl $0x9fffffff, %%eax\n" - "movl %%eax, %%cr0\n" : : : "eax"); + "andl %0, %%eax\n" + "movl %%eax, %%cr0\n" : : "i" (nw_cd_rst) : "eax"); } unsigned long init_sc520_dram(void) diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index ab9338a00a..460c21bef8 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -26,6 +26,7 @@ #include <config.h> #include <version.h> #include <asm/global_data.h> +#include <asm/processor-flags.h> .section .text @@ -46,7 +47,7 @@ _i386boot_start: /* Turn of cache (this might require a 486-class CPU) */ movl %cr0, %eax - orl $0x60000000, %eax + orl $(X86_CR0_NW | X86_CR0_CD), %eax movl %eax, %cr0 wbinvd diff --git a/arch/i386/cpu/start16.S b/arch/i386/cpu/start16.S index 0a5823d3c2..7dc5358366 100644 --- a/arch/i386/cpu/start16.S +++ b/arch/i386/cpu/start16.S @@ -23,6 +23,7 @@ */ #include <asm/global_data.h> +#include <asm/processor-flags.h> #define BOOT_SEG 0xffff0000 /* linear segment of boot code */ #define a32 .byte 0x67; @@ -45,7 +46,7 @@ board_init16_ret: /* Turn of cache (this might require a 486-class CPU) */ movl %cr0, %eax - orl $0x60000000, %eax + orl $(X86_CR0_NW & X86_CR0_CD), %eax movl %eax, %cr0 wbinvd @@ -55,7 +56,7 @@ o32 cs lgdt gdt_ptr /* Now, we enter protected mode */ movl %cr0, %eax - orl $1, %eax + orl $X86_CR0_PE, %eax movl %eax, %cr0 /* Flush the prefetch queue */ diff --git a/arch/i386/include/asm/processor-flags.h b/arch/i386/include/asm/processor-flags.h new file mode 100644 index 0000000000..7a3e836eb2 --- /dev/null +++ b/arch/i386/include/asm/processor-flags.h @@ -0,0 +1,100 @@ +#ifndef _ASM_X86_PROCESSOR_FLAGS_H +#define _ASM_X86_PROCESSOR_FLAGS_H +/* Various flags defined: can be included from assembler. */ + +/* + * EFLAGS bits + */ +#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ +#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ +#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ +#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ +#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ +#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ +#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ +#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ +#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ +#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ +#define X86_EFLAGS_NT 0x00004000 /* Nested Task */ +#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ +#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ +#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ +#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ +#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ +#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ + +/* + * Basic CPU control in CR0 + */ +#define X86_CR0_PE 0x00000001 /* Protection Enable */ +#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */ +#define X86_CR0_EM 0x00000004 /* Emulation */ +#define X86_CR0_TS 0x00000008 /* Task Switched */ +#define X86_CR0_ET 0x00000010 /* Extension Type */ +#define X86_CR0_NE 0x00000020 /* Numeric Error */ +#define X86_CR0_WP 0x00010000 /* Write Protect */ +#define X86_CR0_AM 0x00040000 /* Alignment Mask */ +#define X86_CR0_NW 0x20000000 /* Not Write-through */ +#define X86_CR0_CD 0x40000000 /* Cache Disable */ +#define X86_CR0_PG 0x80000000 /* Paging */ + +/* + * Paging options in CR3 + */ +#define X86_CR3_PWT 0x00000008 /* Page Write Through */ +#define X86_CR3_PCD 0x00000010 /* Page Cache Disable */ + +/* + * Intel CPU features in CR4 + */ +#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ +#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ +#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ +#define X86_CR4_DE 0x00000008 /* enable debugging extensions */ +#define X86_CR4_PSE 0x00000010 /* enable page size extensions */ +#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ +#define X86_CR4_MCE 0x00000040 /* Machine check enable */ +#define X86_CR4_PGE 0x00000080 /* enable global pages */ +#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ +#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ +#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ +#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */ +#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ + +/* + * x86-64 Task Priority Register, CR8 + */ +#define X86_CR8_TPR 0x0000000F /* task priority register */ + +/* + * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h> + */ + +/* + * NSC/Cyrix CPU configuration register indexes + */ +#define CX86_PCR0 0x20 +#define CX86_GCR 0xb8 +#define CX86_CCR0 0xc0 +#define CX86_CCR1 0xc1 +#define CX86_CCR2 0xc2 +#define CX86_CCR3 0xc3 +#define CX86_CCR4 0xe8 +#define CX86_CCR5 0xe9 +#define CX86_CCR6 0xea +#define CX86_CCR7 0xeb +#define CX86_PCR1 0xf0 +#define CX86_DIR0 0xfe +#define CX86_DIR1 0xff +#define CX86_ARR_BASE 0xc4 +#define CX86_RCR_BASE 0xdc + +#ifdef __KERNEL__ +#ifdef CONFIG_VM86 +#define X86_VM_MASK X86_EFLAGS_VM +#else +#define X86_VM_MASK 0 /* No VM86 support */ +#endif +#endif + +#endif /* _ASM_X86_PROCESSOR_FLAGS_H */ |