diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/cpu/quark/dram.c | 99 | ||||
| -rw-r--r-- | arch/x86/dts/galileo.dts | 25 |
2 files changed, 122 insertions, 2 deletions
diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index fbdc3cde05..9cac846c69 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -5,15 +5,110 @@ */ #include <common.h> +#include <errno.h> +#include <fdtdec.h> #include <asm/post.h> +#include <asm/arch/mrc.h> #include <asm/arch/quark.h> DECLARE_GLOBAL_DATA_PTR; +static int mrc_configure_params(struct mrc_params *mrc_params) +{ + const void *blob = gd->fdt_blob; + int node; + int mrc_flags; + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_QRK_MRC); + if (node < 0) { + debug("%s: Cannot find MRC node\n", __func__); + return -EINVAL; + } + + /* + * TODO: + * + * We need support fast boot (MRC cache) in the future. + * + * Set boot mode to cold boot for now + */ + mrc_params->boot_mode = BM_COLD; + + /* + * TODO: + * + * We need determine ECC by pin strap state + * + * Disable ECC by default for now + */ + mrc_params->ecc_enables = 0; + + mrc_flags = fdtdec_get_int(blob, node, "flags", 0); + if (mrc_flags & MRC_FLAG_SCRAMBLE_EN) + mrc_params->scrambling_enables = 1; + else + mrc_params->scrambling_enables = 0; + + mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0); + mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0); + mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0); + + mrc_params->rank_enables = fdtdec_get_int(blob, node, "rank-mask", 0); + mrc_params->channel_enables = fdtdec_get_int(blob, node, + "chan-mask", 0); + mrc_params->channel_width = fdtdec_get_int(blob, node, + "chan-width", 0); + mrc_params->address_mode = fdtdec_get_int(blob, node, "addr-mode", 0); + + mrc_params->refresh_rate = fdtdec_get_int(blob, node, + "refresh-rate", 0); + mrc_params->sr_temp_range = fdtdec_get_int(blob, node, + "sr-temp-range", 0); + mrc_params->ron_value = fdtdec_get_int(blob, node, + "ron-value", 0); + mrc_params->rtt_nom_value = fdtdec_get_int(blob, node, + "rtt-nom-value", 0); + mrc_params->rd_odt_value = fdtdec_get_int(blob, node, + "rd-odt-value", 0); + + mrc_params->params.density = fdtdec_get_int(blob, node, + "dram-density", 0); + mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0); + mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0); + mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0); + mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0); + mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0); + + debug("MRC dram_width %d\n", mrc_params->dram_width); + debug("MRC rank_enables %d\n", mrc_params->rank_enables); + debug("MRC ddr_speed %d\n", mrc_params->ddr_speed); + debug("MRC flags: %s\n", + (mrc_params->scrambling_enables) ? "SCRAMBLE_EN" : ""); + + debug("MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n", + mrc_params->params.density, mrc_params->params.cl, + mrc_params->params.ras, mrc_params->params.wtr, + mrc_params->params.rrd, mrc_params->params.faw); + + return 0; +} + int dram_init(void) { - /* hardcode the DRAM size for now */ - gd->ram_size = DRAM_MAX_SIZE; + struct mrc_params mrc_params; + int ret; + + memset(&mrc_params, 0, sizeof(struct mrc_params)); + ret = mrc_configure_params(&mrc_params); + if (ret) + return ret; + + /* Set up the DRAM by calling the memory reference code */ + mrc_init(&mrc_params); + if (mrc_params.status) + return -EIO; + + gd->ram_size = mrc_params.mem_size; post_code(POST_DRAM); return 0; diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index 14a19c3ec3..d462221a9d 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -6,6 +6,8 @@ /dts-v1/; +#include <dt-bindings/mrc/quark.h> + /include/ "skeleton.dtsi" / { @@ -20,6 +22,29 @@ stdout-path = &pciuart0; }; + mrc { + compatible = "intel,quark-mrc"; + flags = <MRC_FLAG_SCRAMBLE_EN>; + dram-width = <DRAM_WIDTH_X8>; + dram-speed = <DRAM_FREQ_800>; + dram-type = <DRAM_TYPE_DDR3>; + rank-mask = <DRAM_RANK(0)>; + chan-mask = <DRAM_CHANNEL(0)>; + chan-width = <DRAM_CHANNEL_WIDTH_X16>; + addr-mode = <DRAM_ADDR_MODE0>; + refresh-rate = <DRAM_REFRESH_RATE_785US>; + sr-temp-range = <DRAM_SRT_RANGE_NORMAL>; + ron-value = <DRAM_RON_34OHM>; + rtt-nom-value = <DRAM_RTT_NOM_120OHM>; + rd-odt-value = <DRAM_RD_ODT_OFF>; + dram-density = <DRAM_DENSITY_1G>; + dram-cl = <6>; + dram-ras = <0x0000927c>; + dram-wtr = <0x00002710>; + dram-rrd = <0x00002710>; + dram-faw = <0x00009c40>; + }; + pci { #address-cells = <3>; #size-cells = <2>; |