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-rw-r--r--arch/powerpc/dts/mpc8548-post.dtsi9
-rw-r--r--arch/powerpc/dts/mpc8548cds.dts6
-rw-r--r--arch/powerpc/dts/mpc8548cds_36b.dts6
-rw-r--r--arch/powerpc/dts/p1020-post.dtsi20
-rw-r--r--arch/powerpc/dts/p1020rdb-pc.dts12
-rw-r--r--arch/powerpc/dts/p1020rdb-pc_36b.dts12
-rw-r--r--arch/powerpc/dts/p1020rdb-pd.dts12
-rw-r--r--arch/powerpc/dts/p2020-post.dtsi30
-rw-r--r--arch/powerpc/dts/p2020rdb-pc.dts17
-rw-r--r--arch/powerpc/dts/p2020rdb-pc_36b.dts17
-rw-r--r--arch/powerpc/dts/p2041.dtsi36
-rw-r--r--arch/powerpc/dts/p3041.dtsi48
-rw-r--r--arch/powerpc/dts/p4080.dtsi36
-rw-r--r--arch/powerpc/dts/p5040.dtsi36
-rw-r--r--arch/powerpc/dts/t102x.dtsi36
-rw-r--r--arch/powerpc/dts/t104x.dtsi48
-rw-r--r--arch/powerpc/dts/t4240.dtsi48
17 files changed, 429 insertions, 0 deletions
diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-post.dtsi
index 5533a4b598..2206f2da9f 100644
--- a/arch/powerpc/dts/mpc8548-post.dtsi
+++ b/arch/powerpc/dts/mpc8548-post.dtsi
@@ -25,3 +25,12 @@
last-interrupt-source = <255>;
};
};
+
+&pcie {
+ compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/mpc8548cds.dts b/arch/powerpc/dts/mpc8548cds.dts
index cceea345c8..3b927bd265 100644
--- a/arch/powerpc/dts/mpc8548cds.dts
+++ b/arch/powerpc/dts/mpc8548cds.dts
@@ -18,6 +18,12 @@
soc: soc8548@e0000000 {
ranges = <0x0 0x0 0xe0000000 0x100000>;
};
+
+ pcie: pcie@e000a000 {
+ reg = <0x0 0xe000a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000 /* downstream I/O */
+ 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
};
/include/ "mpc8548-post.dtsi"
diff --git a/arch/powerpc/dts/mpc8548cds_36b.dts b/arch/powerpc/dts/mpc8548cds_36b.dts
index faff35cc36..98d7c2410b 100644
--- a/arch/powerpc/dts/mpc8548cds_36b.dts
+++ b/arch/powerpc/dts/mpc8548cds_36b.dts
@@ -18,6 +18,12 @@
soc: soc8548@fe0000000 {
ranges = <0x0 0xf 0xe0000000 0x100000>;
};
+
+ pcie: pcie@fe000a000 {
+ reg = <0xf 0xe000a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x00100000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
};
/include/ "mpc8548-post.dtsi"
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index e1a4f500a6..1e5e67804b 100644
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -25,3 +25,23 @@
last-interrupt-source = <255>;
};
};
+
+/* PCIe controller base address 0x9000 */
+&pci1 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+&pci0 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
index fd68b8b440..7ebaa619df 100644
--- a/arch/powerpc/dts/p1020rdb-pc.dts
+++ b/arch/powerpc/dts/p1020rdb-pc.dts
@@ -18,6 +18,18 @@
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
+
+ pci1: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@ffe0a000 {
+ reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
};
/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts
index a23d031eee..c0e5ef4cf4 100644
--- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -18,6 +18,18 @@
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
+
+ pci1: pcie@fffe09000 {
+ reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@fffe0a000 {
+ reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
};
/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
index 81f25a3866..21174a09be 100644
--- a/arch/powerpc/dts/p1020rdb-pd.dts
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -18,6 +18,18 @@
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
+
+ pci1: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@ffe0a000 {
+ reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
};
/include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index f20d1fa20d..f696f35960 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -25,3 +25,33 @@
last-interrupt-source = <255>;
};
};
+
+/* PCIe controller base address 0x8000 */
+&pci2 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0x9000 */
+&pci1 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+&pci0 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 4800b76c1c..08befd4c59 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -18,6 +18,23 @@
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
+
+ pci2: pcie@ffe08000 {
+ reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */
+ status = "disabled";
+ };
+
+ pci1: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@ffe0a000 {
+ reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
};
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 8323b90e6d..04b2519e1a 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -18,6 +18,23 @@
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
+
+ pci2: pcie@fffe08000 {
+ reg = <0xf 0xffe08000 0x0 0x1000>; /* registers */
+ status = "disabled";
+ };
+
+ pci1: pcie@fffe09000 {
+ reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@fffe0a000 {
+ reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
};
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi
index 9aa0422821..55f7adc50e 100644
--- a/arch/powerpc/dts/p2041.dtsi
+++ b/arch/powerpc/dts/p2041.dtsi
@@ -60,4 +60,40 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe200000 {
+ compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe201000 {
+ compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe202000 {
+ compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
};
diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi
index 7d5c7134aa..197896d35a 100644
--- a/arch/powerpc/dts/p3041.dtsi
+++ b/arch/powerpc/dts/p3041.dtsi
@@ -60,4 +60,52 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe200000 {
+ compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe201000 {
+ compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe202000 {
+ compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe203000 {
+ compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe203000 0x0 0x1000>; /* registers */
+ law_trgt_if = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
};
diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi
index 7c8dbae442..ab766803a3 100644
--- a/arch/powerpc/dts/p4080.dtsi
+++ b/arch/powerpc/dts/p4080.dtsi
@@ -80,4 +80,40 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe200000 {
+ compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe201000 {
+ compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe202000 {
+ compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
};
diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi
index b6f6c5dd58..8ab123dca4 100644
--- a/arch/powerpc/dts/p5040.dtsi
+++ b/arch/powerpc/dts/p5040.dtsi
@@ -59,4 +59,40 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe200000 {
+ compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe201000 {
+ compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe202000 {
+ compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
};
diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi
index 2393e316f8..c49fd21088 100644
--- a/arch/powerpc/dts/t102x.dtsi
+++ b/arch/powerpc/dts/t102x.dtsi
@@ -49,4 +49,40 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe240000 {
+ compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe250000 {
+ compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe260000 {
+ compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
};
diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi
index ff0da9397e..59989677a2 100644
--- a/arch/powerpc/dts/t104x.dtsi
+++ b/arch/powerpc/dts/t104x.dtsi
@@ -59,4 +59,52 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe240000 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe250000 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe260000 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe270000 {
+ compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */
+ law_trgt_if = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
+ };
};
diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi
index 4d8fc7192e..fc34974c7f 100644
--- a/arch/powerpc/dts/t4240.dtsi
+++ b/arch/powerpc/dts/t4240.dtsi
@@ -99,4 +99,52 @@
clock-frequency = <0x0>;
};
};
+
+ pcie@ffe240000 {
+ compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe250000 {
+ compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe250000 0x0 0x4000>; /* registers */
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe260000 {
+ compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe260000 0x0 0x4000>; /* registers */
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
+
+ pcie@ffe270000 {
+ compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
+ reg = <0xf 0xfe270000 0x0 0x4000>; /* registers */
+ law_trgt_if = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
+ };
};
generated by cgit (git 2.34.1) at 2025-01-06 12:39:27 +0000