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-rw-r--r--arch/arm/cpu/arm720t/tegra20/cpu.c8
-rw-r--r--arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c2
-rw-r--r--arch/arm/cpu/tegra20-common/Makefile2
-rw-r--r--arch/arm/cpu/tegra20-common/ap20.c6
-rw-r--r--arch/arm/cpu/tegra20-common/board.c14
-rw-r--r--arch/arm/cpu/tegra20-common/warmboot.c14
-rw-r--r--arch/arm/cpu/tegra20-common/warmboot_avp.c2
-rw-r--r--arch/arm/include/asm/arch-tegra20/ap20.h3
-rw-r--r--arch/arm/include/asm/arch-tegra20/mmc.h8
-rw-r--r--arch/arm/include/asm/arch-tegra20/sys_proto.h4
-rw-r--r--arch/arm/include/asm/arch-tegra20/tegra20.h14
-rw-r--r--arch/arm/include/asm/arch-tegra20/tegra_mmc.h131
-rw-r--r--arch/arm/include/asm/arch-tegra20/tegra_spi.h2
-rw-r--r--arch/arm/include/asm/arch-tegra20/timer.h4
14 files changed, 171 insertions, 43 deletions
diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c b/arch/arm/cpu/arm720t/tegra20/cpu.c
index 6d4d66bced..ddf8d979f4 100644
--- a/arch/arm/cpu/arm720t/tegra20/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra20/cpu.c
@@ -105,14 +105,14 @@ static void enable_cpu_clock(int enable)
static int is_cpu_powered(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
}
static void remove_cpu_io_clamps(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
/* Remove the clamps on the CPU I/O signals */
@@ -126,7 +126,7 @@ static void remove_cpu_io_clamps(void)
static void powerup_cpu(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
int timeout = IO_STABILIZATION_DELAY;
@@ -157,7 +157,7 @@ static void powerup_cpu(void)
static void enable_cpu_power_rail(void)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
reg = readl(&pmc->pmc_cntrl);
diff --git a/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c b/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c
index 75cadb03ec..925f8414c4 100644
--- a/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c
+++ b/arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c
@@ -46,7 +46,7 @@
static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
puts("Entering RCM...\n");
udelay(50000);
diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile
index 43c96c6864..9e91e5cb8c 100644
--- a/arch/arm/cpu/tegra20-common/Makefile
+++ b/arch/arm/cpu/tegra20-common/Makefile
@@ -33,7 +33,7 @@ LIB = $(obj)lib$(SOC)-common.o
SOBJS += lowlevel_init.o
COBJS-y += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
-COBJS-$(CONFIG_TEGRA20_LP0) += warmboot.o crypto.o warmboot_avp.o
+COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
diff --git a/arch/arm/cpu/tegra20-common/ap20.c b/arch/arm/cpu/tegra20-common/ap20.c
index 00588dae52..c0ca6eb379 100644
--- a/arch/arm/cpu/tegra20-common/ap20.c
+++ b/arch/arm/cpu/tegra20-common/ap20.c
@@ -32,7 +32,7 @@
int tegra_get_chip_type(void)
{
struct apb_misc_gp_ctlr *gp;
- struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+ struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
uint tegra_sku_id, rev;
/*
@@ -40,7 +40,7 @@ int tegra_get_chip_type(void)
* APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
* Tegra30
*/
- gp = (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+ gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
tegra_sku_id = readl(&fuse->sku_info) & 0xff;
@@ -101,7 +101,7 @@ static u32 get_odmdata(void)
static void init_pmc_scratch(void)
{
- struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 odmdata;
int i;
diff --git a/arch/arm/cpu/tegra20-common/board.c b/arch/arm/cpu/tegra20-common/board.c
index 598023aba9..8a8d3384ac 100644
--- a/arch/arm/cpu/tegra20-common/board.c
+++ b/arch/arm/cpu/tegra20-common/board.c
@@ -47,7 +47,7 @@ enum {
unsigned int query_sdram_size(void)
{
- struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
reg = readl(&pmc->pmc_scratch20);
@@ -81,11 +81,11 @@ int checkboard(void)
#endif /* CONFIG_DISPLAY_BOARDINFO */
static int uart_configs[] = {
-#if defined(CONFIG_TEGRA20_UARTA_UAA_UAB)
+#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
FUNCMUX_UART1_UAA_UAB,
-#elif defined(CONFIG_TEGRA20_UARTA_GPU)
+#elif defined(CONFIG_TEGRA_UARTA_GPU)
FUNCMUX_UART1_GPU,
-#elif defined(CONFIG_TEGRA20_UARTA_SDIO1)
+#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
FUNCMUX_UART1_SDIO1,
#else
FUNCMUX_UART1_IRRX_IRTX,
@@ -125,13 +125,13 @@ void board_init_uart_f(void)
{
int uart_ids = 0; /* bit mask of which UART ids to enable */
-#ifdef CONFIG_TEGRA20_ENABLE_UARTA
+#ifdef CONFIG_TEGRA_ENABLE_UARTA
uart_ids |= UARTA;
#endif
-#ifdef CONFIG_TEGRA20_ENABLE_UARTB
+#ifdef CONFIG_TEGRA_ENABLE_UARTB
uart_ids |= UARTB;
#endif
-#ifdef CONFIG_TEGRA20_ENABLE_UARTD
+#ifdef CONFIG_TEGRA_ENABLE_UARTD
uart_ids |= UARTD;
#endif
setup_uarts(uart_ids);
diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c
index 809ea0133e..6ce995ef02 100644
--- a/arch/arm/cpu/tegra20-common/warmboot.c
+++ b/arch/arm/cpu/tegra20-common/warmboot.c
@@ -39,7 +39,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_TEGRA_CLOCK_SCALING
-#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA20_LP0"
+#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
#endif
/*
@@ -139,9 +139,9 @@ int warmboot_save_sdram_params(void)
u32 ram_code;
struct sdram_params sdram;
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+ (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
union scratch2_reg scratch2;
union scratch4_reg scratch4;
@@ -205,7 +205,7 @@ static u32 get_major_version(void)
{
u32 major_id;
struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+ (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
HIDREV_MAJORPREV_SHIFT;
@@ -229,7 +229,7 @@ static int is_failure_analysis_mode(struct fuse_regs *fuse)
static int ap20_is_odm_production_mode(void)
{
- struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+ struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
if (!is_failure_analysis_mode(fuse) &&
is_odm_production_mode_fuse_set(fuse))
@@ -240,7 +240,7 @@ static int ap20_is_odm_production_mode(void)
static int ap20_is_production_mode(void)
{
- struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+ struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
if (get_major_version() == 0)
return 1;
@@ -257,7 +257,7 @@ static enum fuse_operating_mode fuse_get_operation_mode(void)
{
u32 chip_id;
struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+ (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
HIDREV_CHIPID_SHIFT;
diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c
index cd01908a46..80a5a15dec 100644
--- a/arch/arm/cpu/tegra20-common/warmboot_avp.c
+++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c
@@ -38,7 +38,7 @@
void wb_start(void)
{
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
diff --git a/arch/arm/include/asm/arch-tegra20/ap20.h b/arch/arm/include/asm/arch-tegra20/ap20.h
index c84d22f97b..70d94c5041 100644
--- a/arch/arm/include/asm/arch-tegra20/ap20.h
+++ b/arch/arm/include/asm/arch-tegra20/ap20.h
@@ -95,9 +95,6 @@
#define HALT_COP_EVENT_IRQ_1 (1 << 11)
#define HALT_COP_EVENT_FIQ_1 (1 << 9)
-/* Start up the tegra20 SOC */
-void tegra20_start(void);
-
/* This is the main entry into U-Boot, used by the Cortex-A9 */
extern void _start(void);
diff --git a/arch/arm/include/asm/arch-tegra20/mmc.h b/arch/arm/include/asm/arch-tegra20/mmc.h
index 916a353a97..5c95047998 100644
--- a/arch/arm/include/asm/arch-tegra20/mmc.h
+++ b/arch/arm/include/asm/arch-tegra20/mmc.h
@@ -19,9 +19,9 @@
* MA 02111-1307 USA
*/
-#ifndef _TEGRA20_MMC_H_
-#define _TEGRA20_MMC_H_
+#ifndef _TEGRA_MMC_H_
+#define _TEGRA_MMC_H_
-int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
+int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
-#endif /* TEGRA20_MMC_H_ */
+#endif /* _TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/sys_proto.h b/arch/arm/include/asm/arch-tegra20/sys_proto.h
index 643d5424b8..919aec7f74 100644
--- a/arch/arm/include/asm/arch-tegra20/sys_proto.h
+++ b/arch/arm/include/asm/arch-tegra20/sys_proto.h
@@ -24,12 +24,12 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
-struct tegra20_sysinfo {
+struct tegra_sysinfo {
char *board_string;
};
void invalidate_dcache(void);
-extern const struct tegra20_sysinfo sysinfo;
+extern const struct tegra_sysinfo sysinfo;
#endif
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20.h b/arch/arm/include/asm/arch-tegra20/tegra20.h
index b2fb50e33e..c9485a1c84 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra20.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra20.h
@@ -33,22 +33,22 @@
#define NV_PA_GPIO_BASE 0x6000D000
#define NV_PA_EVP_BASE 0x6000F000
#define NV_PA_APB_MISC_BASE 0x70000000
-#define TEGRA20_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
+#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
-#define TEGRA20_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
-#define TEGRA20_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
-#define TEGRA20_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
-#define TEGRA20_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
+#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
+#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
+#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
+#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
#define NV_PA_CSITE_BASE 0x70040000
#define TEGRA_USB1_BASE 0xC5000000
#define TEGRA_USB3_BASE 0xC5008000
#define TEGRA_USB_ADDR_MASK 0xFFFFC000
-#define TEGRA20_SDRC_CS0 NV_PA_SDRAM_BASE
+#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
#define LOW_LEVEL_SRAM_STACK 0x4000FFFC
#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000)
#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096)
@@ -86,7 +86,7 @@ enum {
};
#else /* __ASSEMBLY__ */
-#define PRM_RSTCTRL TEGRA20_PMC_BASE
+#define PRM_RSTCTRL NV_PA_PMC_BASE
#endif
#endif /* TEGRA20_H */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra_mmc.h b/arch/arm/include/asm/arch-tegra20/tegra_mmc.h
new file mode 100644
index 0000000000..dd746cae0d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/tegra_mmc.h
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Portions Copyright (C) 2011-2012 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __TEGRA_MMC_H_
+#define __TEGRA_MMC_H_
+
+#define TEGRA_SDMMC1_BASE 0xC8000000
+#define TEGRA_SDMMC2_BASE 0xC8000200
+#define TEGRA_SDMMC3_BASE 0xC8000400
+#define TEGRA_SDMMC4_BASE 0xC8000600
+
+#ifndef __ASSEMBLY__
+struct tegra_mmc {
+ unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
+ unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
+ unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
+ unsigned int argument; /* _ARGUMENT_0 */
+ unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */
+ unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */
+ unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
+ unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
+ unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
+ unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
+ unsigned int bdata; /* _BUFFER_DATA_PORT_0 */
+ unsigned int prnsts; /* _PRESENT_STATE_0 */
+ unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */
+ unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */
+ unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */
+ unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */
+ unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */
+ unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */
+ unsigned char swrst; /* _SW_RESET_ 31:24 */
+ unsigned int norintsts; /* _INTERRUPT_STATUS_0 */
+ unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */
+ unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */
+ unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
+ unsigned char res1[2]; /* _RESERVED 31:16 */
+ unsigned int capareg; /* _CAPABILITIES_0 */
+ unsigned char res2[4]; /* RESERVED, offset 44h-47h */
+ unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */
+ unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */
+ unsigned short setacmd12err; /* offset 50h */
+ unsigned short setinterr; /* offset 52h */
+ unsigned char admaerr; /* offset 54h */
+ unsigned char res4[3]; /* RESERVED, offset 55h-57h */
+ unsigned long admaaddr; /* offset 58h-5Fh */
+ unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
+ unsigned short slotintstatus; /* offset FCh */
+ unsigned short hcver; /* HOST Version */
+ unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */
+};
+
+#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3)
+
+#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0)
+#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4)
+#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5)
+
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0)
+
+#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3)
+#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5)
+
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0)
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1)
+
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0)
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1)
+#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2)
+
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8)
+
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2)
+
+#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0)
+#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1)
+#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3)
+#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15)
+#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16)
+
+#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0)
+#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1)
+#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5)
+
+#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
+
+struct mmc_host {
+ struct tegra_mmc *reg;
+ unsigned int version; /* SDHCI spec. version */
+ unsigned int clock; /* Current clock (MHz) */
+ unsigned int base; /* Base address, SDMMC1/2/3/4 */
+ enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
+ int pwr_gpio; /* Power GPIO */
+ int cd_gpio; /* Change Detect GPIO */
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* __TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/tegra_spi.h b/arch/arm/include/asm/arch-tegra20/tegra_spi.h
index 8978beacc5..d53a93ff53 100644
--- a/arch/arm/include/asm/arch-tegra20/tegra_spi.h
+++ b/arch/arm/include/asm/arch-tegra20/tegra_spi.h
@@ -70,6 +70,6 @@ struct spi_tegra {
#define SPI_STAT_CUR_BLKCNT (1 << 15)
#define SPI_TIMEOUT 1000
-#define TEGRA20_SPI_MAX_FREQ 52000000
+#define TEGRA_SPI_MAX_FREQ 52000000
#endif /* _TEGRA_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/timer.h b/arch/arm/include/asm/arch-tegra20/timer.h
index 43f7ab4efa..fdb99a73ee 100644
--- a/arch/arm/include/asm/arch-tegra20/timer.h
+++ b/arch/arm/include/asm/arch-tegra20/timer.h
@@ -21,8 +21,8 @@
/* Tegra20 timer functions */
-#ifndef _TEGRA20_TIMER_H
-#define _TEGRA20_TIMER_H
+#ifndef _TEGRA_TIMER_H
+#define _TEGRA_TIMER_H
/* returns the current monotonic timer value in microseconds */
unsigned long timer_get_us(void);
generated by cgit (git 2.34.1) at 2024-12-26 22:19:13 +0000