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-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h111
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl489
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl48
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/irqroute.h27
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/lpc.asl121
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/platform.asl33
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl13
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl211
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/usb.asl34
-rw-r--r--arch/x86/include/asm/arch-baytrail/acpi/xhci.asl31
-rw-r--r--arch/x86/include/asm/arch-baytrail/device.h74
-rw-r--r--arch/x86/include/asm/arch-baytrail/iomap.h70
-rw-r--r--arch/x86/include/asm/arch-baytrail/irq.h86
13 files changed, 1348 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h b/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
new file mode 100644
index 0000000000..2c3585ac7f
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronics Engineering, LLC.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This file intentionally gets included multiple times, to set pic and apic
+ * modes, so should not have guard statements added.
+ */
+
+/*
+ * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ
+ * routing for the platform being compiled.
+ *
+ * This method uses #defines in irqroute.h along with the macros contained
+ * in this file to generate an IRQ routing for each PCI device in the system.
+ */
+
+#undef PCI_DEV_PIRQ_ROUTES
+#undef PCI_DEV_PIRQ_ROUTE
+#undef ACPI_DEV_IRQ
+#undef PCIE_BRIDGE_DEV
+#undef RP_IRQ_ROUTES
+#undef ROOTPORT_METHODS
+#undef ROOTPORT_IRQ_ROUTES
+#undef RP_METHOD
+
+#if defined(PIC_MODE)
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+ Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## P, Package() \
+{ \
+ ACPI_DEV_IRQ(0x0000, 0, a_), \
+ ACPI_DEV_IRQ(0x0000, 1, b_), \
+ ACPI_DEV_IRQ(0x0000, 2, c_), \
+ ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+/* define as blank so ROOTPORT_METHODS only gets inserted once */
+#define ROOTPORT_METHODS(prefix_, dev_)
+
+#else /* defined(PIC_MODE) */
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+ Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## A, Package() \
+{ \
+ ACPI_DEV_IRQ(0x0000, 0, a_), \
+ ACPI_DEV_IRQ(0x0000, 1, b_), \
+ ACPI_DEV_IRQ(0x0000, 2, c_), \
+ ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+#define ROOTPORT_METHODS(prefix_, dev_) \
+ RP_METHOD(prefix_, dev_, 0) \
+ RP_METHOD(prefix_, dev_, 1) \
+ RP_METHOD(prefix_, dev_, 2) \
+ RP_METHOD(prefix_, dev_, 3) \
+ RP_METHOD(prefix_, dev_, 4) \
+ RP_METHOD(prefix_, dev_, 5) \
+ RP_METHOD(prefix_, dev_, 6) \
+ RP_METHOD(prefix_, dev_, 7)
+
+#endif /* defined(PIC_MODE) */
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+ ACPI_DEV_IRQ(dev_, 0, a_), \
+ ACPI_DEV_IRQ(dev_, 1, b_), \
+ ACPI_DEV_IRQ(dev_, 2, c_), \
+ ACPI_DEV_IRQ(dev_, 3, d_)
+
+#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
+ ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+ ROOTPORT_METHODS(prefix_, dev_)
+
+#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+ RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
+ RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
+ RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
+ RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
+ RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
+ RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
+ RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
+ RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
+
+#define RP_METHOD(prefix_, dev_, func_)\
+Device (prefix_ ## 0 ## func_) \
+{ \
+ Name(_ADR, dev_ ## 000 ## func_) \
+ Name(_PRW, Package() { 0, 0 }) \
+ Method(_PRT) { \
+ If (PICM) { \
+ Return (prefix_ ## func_ ## A) \
+ } Else { \
+ Return (prefix_ ## func_ ## P) \
+ } \
+ } \
+}
+
+/* SoC specific PIRQ route configuration */
+#include "irqroute.h"
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
new file mode 100644
index 0000000000..aa7208529c
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl
@@ -0,0 +1,489 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Scope (\)
+{
+ /* Intel Legacy Block */
+ OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+ Field(ILBS, AnyAcc, NoLock, Preserve) {
+ Offset (0x8),
+ PRTA, 8,
+ PRTB, 8,
+ PRTC, 8,
+ PRTD, 8,
+ PRTE, 8,
+ PRTF, 8,
+ PRTG, 8,
+ PRTH, 8,
+ }
+}
+
+Device (LNKA)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTA)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLA, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLA, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTA */
+ ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+ Return (RTLA)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTA)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTA, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKB)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTB)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLB, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLB, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTB */
+ ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+ Return (RTLB)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTB)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTB, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKC)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTC)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLC, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLC, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTC */
+ ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+ Return (RTLC)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTC)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTC, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKD)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTD)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLD, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLD, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTD */
+ ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+ Return (RTLD)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTD)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTD, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKE)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTE)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLE, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLE, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTE */
+ ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
+
+ Return (RTLE)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTE)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTE, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKF)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTF)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLF, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLF, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTF */
+ ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
+
+ Return (RTLF)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTF)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTF, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKG)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTG)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLG, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLG, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTG */
+ ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
+
+ Return (RTLG)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTG)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTG, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
+
+Device (LNKH)
+{
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ /* Disable method */
+ Method(_DIS, 0, Serialized)
+ {
+ Store(0x80, PRTH)
+ }
+
+ /* Possible Resource Settings for this Link */
+ Name(_PRS, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+ })
+
+ /* Current Resource Settings for this link */
+ Method(_CRS, 0, Serialized)
+ {
+ Name(RTLH, ResourceTemplate()
+ {
+ IRQ(Level, ActiveLow, Shared) {}
+ })
+ CreateWordField(RTLH, 1, IRQ0)
+
+ /* Clear the WordField */
+ Store(Zero, IRQ0)
+
+ /* Set the bit from PRTH */
+ ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
+
+ Return (RTLH)
+ }
+
+ /* Set Resource Setting for this IRQ link */
+ Method(_SRS, 1, Serialized)
+ {
+ CreateWordField(Arg0, 1, IRQ0)
+
+ /* Which bit is set? */
+ FindSetRightBit(IRQ0, Local0)
+
+ Decrement(Local0)
+ Store(Local0, PRTH)
+ }
+
+ /* Status */
+ Method(_STA, 0, Serialized)
+ {
+ If (And(PRTH, 0x80)) {
+ Return (STA_DISABLED)
+ } Else {
+ Return (STA_INVISIBLE)
+ }
+ }
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
new file mode 100644
index 0000000000..64d38207d9
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Name(\PICM, 0)
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local APIC/IOAPIC configuration.
+ */
+Method(\_PIC, 1)
+{
+ /* Remember the OS' IRQ routing choice */
+ Store(Arg0, PICM)
+}
+
+/* PCI interrupt routing */
+Method(_PRT) {
+ If (PICM) {
+ Return (Package() {
+ #undef PIC_MODE
+ #include "irq_helper.h"
+ PCI_DEV_PIRQ_ROUTES
+ })
+ } Else {
+ Return (Package() {
+ #define PIC_MODE
+ #include "irq_helper.h"
+ PCI_DEV_PIRQ_ROUTES
+ })
+ }
+
+}
+
+/* PCIe downstream ports interrupt routing */
+PCIE_BRIDGE_IRQ_ROUTES
+#undef PIC_MODE
+#include "irq_helper.h"
+PCIE_BRIDGE_IRQ_ROUTES
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
new file mode 100644
index 0000000000..d7463140f1
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(EMMC_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SD_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(MMC45_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, A, A, A), \
+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+ PCIE_BRIDGE_DEV(RP, PCIE_DEV, A, B, C, D)
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
new file mode 100644
index 0000000000..1dca9770c5
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+ Name(_ADR, 0x001f0000)
+
+ #include "irqlinks.asl"
+
+ /* Firmware Hub */
+ Device (FWH)
+ {
+ Name(_HID, EISAID("INT0800"))
+ Name(_CRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+ })
+ }
+
+ /* 8259 Interrupt Controller */
+ Device (PIC)
+ {
+ Name(_HID, EISAID("PNP0000"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+ IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+ IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+ IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+ IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+ IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+ IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+ IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+ IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+ IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+ IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+ IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+ IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+ IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+ IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+ IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+ IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+ IRQNoFlags () { 2 }
+ })
+ }
+
+ /* 8254 timer */
+ Device (TIMR)
+ {
+ Name(_HID, EISAID("PNP0100"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+ IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+ IRQNoFlags() { 0 }
+ })
+ }
+
+ /* HPET */
+ Device (HPET)
+ {
+ Name(_HID, EISAID("PNP0103"))
+ Name(_CID, 0x010CD041)
+ Name(_CRS, ResourceTemplate()
+ {
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+ })
+
+ Method(_STA)
+ {
+ Return (STA_VISIBLE)
+ }
+ }
+
+ /* Real Time Clock */
+ Device (RTC)
+ {
+ Name(_HID, EISAID("PNP0B00"))
+ Name(_CRS, ResourceTemplate()
+ {
+ IO(Decode16, 0x70, 0x70, 1, 8)
+ /*
+ * Disable as Windows doesn't like it, and systems
+ * don't seem to use it
+ */
+ /* IRQNoFlags() { 8 } */
+ })
+ }
+
+ /* LPC device: Resource consumption */
+ Device (LDRC)
+ {
+ Name(_HID, EISAID("PNP0C02"))
+ Name(_UID, 2)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+ IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+ IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+ IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+ })
+
+ Method(_CRS, 0, NotSerialized)
+ {
+ Return (RBUF)
+ }
+ }
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
new file mode 100644
index 0000000000..bd72842dd6
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+ Return (Package() {0, 0})
+}
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+ #include "southcluster.asl"
+}
+
+/* Chipset specific sleep states */
+#include "sleepstates.asl"
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl
new file mode 100644
index 0000000000..eb5ae76186
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
+Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
+Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
new file mode 100644
index 0000000000..34d3951424
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Device (PCI0)
+{
+ Name(_HID, EISAID("PNP0A08")) /* PCIe */
+ Name(_CID, EISAID("PNP0A03")) /* PCI */
+
+ Name(_ADR, 0)
+ Name(_BBN, 0)
+
+ Name(MCRS, ResourceTemplate()
+ {
+ /* Bus Numbers */
+ WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+ /* IO Region 0 */
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+ /* PCI Config Space */
+ IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ /* IO Region 1 */
+ WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+ /* VGA memory (0xa0000-0xbffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000, , , ASEG)
+
+ /* OPROM reserved (0xc0000-0xc3fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+ 0x00004000, , , OPR0)
+
+ /* OPROM reserved (0xc4000-0xc7fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+ 0x00004000, , , OPR1)
+
+ /* OPROM reserved (0xc8000-0xcbfff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+ 0x00004000, , , OPR2)
+
+ /* OPROM reserved (0xcc000-0xcffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+ 0x00004000, , , OPR3)
+
+ /* OPROM reserved (0xd0000-0xd3fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+ 0x00004000, , , OPR4)
+
+ /* OPROM reserved (0xd4000-0xd7fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+ 0x00004000, , , OPR5)
+
+ /* OPROM reserved (0xd8000-0xdbfff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+ 0x00004000, , , OPR6)
+
+ /* OPROM reserved (0xdc000-0xdffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+ 0x00004000, , , OPR7)
+
+ /* BIOS Extension (0xe0000-0xe3fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+ 0x00004000, , , ESG0)
+
+ /* BIOS Extension (0xe4000-0xe7fff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+ 0x00004000, , , ESG1)
+
+ /* BIOS Extension (0xe8000-0xebfff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+ 0x00004000, , , ESG2)
+
+ /* BIOS Extension (0xec000-0xeffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+ 0x00004000, , , ESG3)
+
+ /* System BIOS (0xf0000-0xfffff) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+ 0x00010000, , , FSEG)
+
+ /* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+ DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, , , PMEM)
+
+ /* High PCI Memory Region */
+ QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, , , UMEM)
+ })
+
+ Method(_CRS, 0, Serialized)
+ {
+ /* Update PCI resource area */
+ CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+ CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+ CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+ /*
+ * Hardcode TOLM to 2GB for now as BayTrail FSP uses this value.
+ *
+ * TODO: for generic usage, read TOLM value from register, or
+ * from global NVS (not implemented by U-Boot yet).
+ */
+ Store(0x80000000, PMIN)
+ Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+ Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+ /* Update High PCI resource area */
+ CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
+ CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
+ CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
+
+ /* Set base address to 48GB and allocate 16GB for PCI space */
+ Store(0xc00000000, UMIN)
+ Store(0x400000000, ULEN)
+ Add(UMIN, Subtract(ULEN, 1), UMAX)
+
+ Return (MCRS)
+ }
+
+ /* Device Resource Consumption */
+ Device (PDRC)
+ {
+ Name(_HID, EISAID("PNP0C02"))
+ Name(_UID, 1)
+
+ Name(PDRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+ Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
+ Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
+ Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
+ Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
+ Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+ Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+ Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
+ })
+
+ /* Current Resource Settings */
+ Method(_CRS, 0, Serialized)
+ {
+ Return (PDRS)
+ }
+ }
+
+ Method(_OSC, 4)
+ {
+ /* Check for proper GUID */
+ If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ /* Let OS control everything */
+ Return (Arg3)
+ } Else {
+ /* Unrecognized UUID */
+ CreateDWordField(Arg3, 0, CDW1)
+ Or(CDW1, 4, CDW1)
+ Return (Arg3)
+ }
+ }
+
+ /* LPC Bridge 0:1f.0 */
+ #include "lpc.asl"
+
+ /* USB EHCI 0:1d.0 */
+ #include "usb.asl"
+
+ /* USB XHCI 0:14.0 */
+ #include "xhci.asl"
+
+ /* IRQ routing for each PCI device */
+ #include "irqroute.asl"
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/usb.asl b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
new file mode 100644
index 0000000000..311f471843
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* EHCI Controller 0:1d.0 */
+
+Device (EHC1)
+{
+ Name(_ADR, 0x001d0000)
+
+ /* Power Resources for Wake */
+ Name(_PRW, Package() { 13, 4 })
+
+ /* Highest D state in S3 state */
+ Name(_S3D, 2)
+
+ /* Highest D state in S4 state */
+ Name(_S4D, 2)
+
+ Device (HUB7)
+ {
+ Name(_ADR, 0x00000000)
+
+ Device(PRT1) { Name(_ADR, 1) } /* USB Port 0 */
+ Device(PRT2) { Name(_ADR, 2) } /* USB Port 1 */
+ Device(PRT3) { Name(_ADR, 3) } /* USB Port 2 */
+ Device(PRT4) { Name(_ADR, 4) } /* USB Port 3 */
+ }
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
new file mode 100644
index 0000000000..a5a4404651
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+ Name(_ADR, 0x00140000)
+
+ /* Power Resources for Wake */
+ Name(_PRW, Package() { 13, 3 })
+
+ /* Highest D state in S3 state */
+ Name(_S3D, 3)
+
+ Device (RHUB)
+ {
+ Name(_ADR, 0x00000000)
+
+ Device (PRT1) { Name(_ADR, 1) } /* USB Port 0 */
+ Device (PRT2) { Name(_ADR, 2) } /* USB Port 1 */
+ Device (PRT3) { Name(_ADR, 3) } /* USB Port 2 */
+ Device (PRT4) { Name(_ADR, 4) } /* USB Port 3 */
+ }
+}
diff --git a/arch/x86/include/asm/arch-baytrail/device.h b/arch/x86/include/asm/arch-baytrail/device.h
new file mode 100644
index 0000000000..798d35bccf
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/device.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DEVICE_H_
+#define _DEVICE_H_
+
+/*
+ * Internal PCI device numbers within the SoC.
+ *
+ * Note it must start with 0x_ prefix, as the device number macro will be
+ * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
+ */
+
+/* SoC transaction router */
+#define SOC_DEV 0x00
+
+/* Graphics and Display */
+#define GFX_DEV 0x02
+
+/* MIPI */
+#define MIPI_DEV 0x03
+
+/* EMMC Port */
+#define EMMC_DEV 0x10
+
+/* SDIO Port */
+#define SDIO_DEV 0x11
+
+/* SD Port */
+#define SD_DEV 0x12
+
+/* SATA */
+#define SATA_DEV 0x13
+
+/* xHCI */
+#define XHCI_DEV 0x14
+
+/* LPE Audio */
+#define LPE_DEV 0x15
+
+/* OTG */
+#define OTG_DEV 0x16
+
+/* MMC45 Port */
+#define MMC45_DEV 0x17
+
+/* Serial IO 1 */
+#define SIO1_DEV 0x18
+
+/* Trusted Execution Engine */
+#define TXE_DEV 0x1a
+
+/* HD Audio */
+#define HDA_DEV 0x1b
+
+/* PCIe Ports */
+#define PCIE_DEV 0x1c
+
+/* EHCI */
+#define EHCI_DEV 0x1d
+
+/* Serial IO 2 */
+#define SIO2_DEV 0x1e
+
+/* Platform Controller Unit */
+#define PCU_DEV 0x1f
+
+#endif /* _DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/iomap.h b/arch/x86/include/asm/arch-baytrail/iomap.h
new file mode 100644
index 0000000000..62a91051e4
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/iomap.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IOMAP_H_
+#define _BAYTRAIL_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE 0x10000000
+
+/* Temporary Base Address */
+#define TEMP_BASE_ADDRESS 0xfd000000
+
+/* Transactions in this range will abort */
+#define ABORT_BASE_ADDRESS 0xfeb00000
+#define ABORT_BASE_SIZE 0x00100000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS 0xfed00000
+#define HPET_BASE_SIZE 0x400
+
+/* SPI Bus */
+#define SPI_BASE_ADDRESS 0xfed01000
+#define SPI_BASE_SIZE 0x400
+
+/* Power Management Controller */
+#define PMC_BASE_ADDRESS 0xfed03000
+#define PMC_BASE_SIZE 0x400
+
+/* Power Management Unit */
+#define PUNIT_BASE_ADDRESS 0xfed05000
+#define PUNIT_BASE_SIZE 0x800
+
+/* Intel Legacy Block */
+#define ILB_BASE_ADDRESS 0xfed08000
+#define ILB_BASE_SIZE 0x400
+
+/* IO Memory */
+#define IO_BASE_ADDRESS 0xfed0c000
+#define IO_BASE_OFFSET_GPSCORE 0x0000
+#define IO_BASE_OFFSET_GPNCORE 0x1000
+#define IO_BASE_OFFSET_GPSSUS 0x2000
+#define IO_BASE_SIZE 0x4000
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS 0xfed1c000
+#define RCBA_BASE_SIZE 0x400
+
+/* MODPHY */
+#define MPHY_BASE_ADDRESS 0xfef00000
+#define MPHY_BASE_SIZE 0x100000
+
+/* IO Port bases */
+#define ACPI_BASE_ADDRESS 0x0400
+#define ACPI_BASE_SIZE 0x80
+
+#define GPIO_BASE_ADDRESS 0x0500
+#define GPIO_BASE_SIZE 0x100
+
+#define SMBUS_BASE_ADDRESS 0xefa0
+
+#endif /* _BAYTRAIL_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/irq.h b/arch/x86/include/asm/arch-baytrail/irq.h
new file mode 100644
index 0000000000..cd66f83c41
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/irq.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IRQ_H_
+#define _BAYTRAIL_IRQ_H_
+
+#define PIRQA_APIC_IRQ 16
+#define PIRQB_APIC_IRQ 17
+#define PIRQC_APIC_IRQ 18
+#define PIRQD_APIC_IRQ 19
+#define PIRQE_APIC_IRQ 20
+#define PIRQF_APIC_IRQ 21
+#define PIRQG_APIC_IRQ 22
+#define PIRQH_APIC_IRQ 23
+
+/* The below IRQs are for when devices are in ACPI mode */
+#define LPE_DMA0_IRQ 24
+#define LPE_DMA1_IRQ 25
+#define LPE_SSP0_IRQ 26
+#define LPE_SSP1_IRQ 27
+#define LPE_SSP2_IRQ 28
+#define LPE_IPC2HOST_IRQ 29
+#define LPSS_I2C1_IRQ 32
+#define LPSS_I2C2_IRQ 33
+#define LPSS_I2C3_IRQ 34
+#define LPSS_I2C4_IRQ 35
+#define LPSS_I2C5_IRQ 36
+#define LPSS_I2C6_IRQ 37
+#define LPSS_I2C7_IRQ 38
+#define LPSS_HSUART1_IRQ 39
+#define LPSS_HSUART2_IRQ 40
+#define LPSS_SPI_IRQ 41
+#define LPSS_DMA1_IRQ 42
+#define LPSS_DMA2_IRQ 43
+#define SCC_EMMC_IRQ 44
+#define SCC_SDIO_IRQ 46
+#define SCC_SD_IRQ 47
+#define GPIO_NC_IRQ 48
+#define GPIO_SC_IRQ 49
+#define GPIO_SUS_IRQ 50
+/* GPIO direct / dedicated IRQs */
+#define GPIO_S0_DED_IRQ_0 51
+#define GPIO_S0_DED_IRQ_1 52
+#define GPIO_S0_DED_IRQ_2 53
+#define GPIO_S0_DED_IRQ_3 54
+#define GPIO_S0_DED_IRQ_4 55
+#define GPIO_S0_DED_IRQ_5 56
+#define GPIO_S0_DED_IRQ_6 57
+#define GPIO_S0_DED_IRQ_7 58
+#define GPIO_S0_DED_IRQ_8 59
+#define GPIO_S0_DED_IRQ_9 60
+#define GPIO_S0_DED_IRQ_10 61
+#define GPIO_S0_DED_IRQ_11 62
+#define GPIO_S0_DED_IRQ_12 63
+#define GPIO_S0_DED_IRQ_13 64
+#define GPIO_S0_DED_IRQ_14 65
+#define GPIO_S0_DED_IRQ_15 66
+#define GPIO_S5_DED_IRQ_0 67
+#define GPIO_S5_DED_IRQ_1 68
+#define GPIO_S5_DED_IRQ_2 69
+#define GPIO_S5_DED_IRQ_3 70
+#define GPIO_S5_DED_IRQ_4 71
+#define GPIO_S5_DED_IRQ_5 72
+#define GPIO_S5_DED_IRQ_6 73
+#define GPIO_S5_DED_IRQ_7 74
+#define GPIO_S5_DED_IRQ_8 75
+#define GPIO_S5_DED_IRQ_9 76
+#define GPIO_S5_DED_IRQ_10 77
+#define GPIO_S5_DED_IRQ_11 78
+#define GPIO_S5_DED_IRQ_12 79
+#define GPIO_S5_DED_IRQ_13 80
+#define GPIO_S5_DED_IRQ_14 81
+#define GPIO_S5_DED_IRQ_15 82
+/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */
+#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot
+#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot
+#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot)
+#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot)
+
+#endif /* _BAYTRAIL_IRQ_H_ */
generated by cgit (git 2.34.1) at 2024-12-26 03:00:12 +0000