diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 112 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/u-boot-nand.lds | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc8xxx/srio.c | 210 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 46 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_srio.h | 64 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 387 |
7 files changed, 635 insertions, 197 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2e4a06c35a..2cd5db7c59 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -37,6 +37,7 @@ #include <asm/mmu.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> +#include <asm/fsl_srio.h> #include <linux/compiler.h> #include "mp.h" #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -48,8 +49,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern void srio_init(void); - #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -443,6 +442,12 @@ skip_l2: #ifdef CONFIG_SYS_SRIO srio_init(); +#ifdef CONFIG_SRIOBOOT_MASTER + srio_boot_master(); +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF + srio_boot_master_release_slave(); +#endif +#endif #endif #if defined(CONFIG_MP) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 4d37d6e863..8e99ef6c68 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -179,41 +179,50 @@ l2_disabled: andi. r1,r3,L1CSR0_DCE@l beq 2b +/* + * Ne need to setup interrupt vector for NAND SPL + * because NAND SPL never compiles it. + */ +#if !defined(CONFIG_NAND_SPL) /* Setup interrupt vectors */ lis r1,CONFIG_SYS_MONITOR_BASE@h mtspr IVPR,r1 - li r1,0x0100 - mtspr IVOR0,r1 /* 0: Critical input */ - li r1,0x0200 - mtspr IVOR1,r1 /* 1: Machine check */ - li r1,0x0300 - mtspr IVOR2,r1 /* 2: Data storage */ - li r1,0x0400 - mtspr IVOR3,r1 /* 3: Instruction storage */ - li r1,0x0500 - mtspr IVOR4,r1 /* 4: External interrupt */ - li r1,0x0600 - mtspr IVOR5,r1 /* 5: Alignment */ - li r1,0x0700 - mtspr IVOR6,r1 /* 6: Program check */ - li r1,0x0800 - mtspr IVOR7,r1 /* 7: floating point unavailable */ - li r1,0x0900 - mtspr IVOR8,r1 /* 8: System call */ + lis r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h + ori r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l + + addi r4,r3,CriticalInput - _start + _START_OFFSET + mtspr IVOR0,r4 /* 0: Critical input */ + addi r4,r3,MachineCheck - _start + _START_OFFSET + mtspr IVOR1,r4 /* 1: Machine check */ + addi r4,r3,DataStorage - _start + _START_OFFSET + mtspr IVOR2,r4 /* 2: Data storage */ + addi r4,r3,InstStorage - _start + _START_OFFSET + mtspr IVOR3,r4 /* 3: Instruction storage */ + addi r4,r3,ExtInterrupt - _start + _START_OFFSET + mtspr IVOR4,r4 /* 4: External interrupt */ + addi r4,r3,Alignment - _start + _START_OFFSET + mtspr IVOR5,r4 /* 5: Alignment */ + addi r4,r3,ProgramCheck - _start + _START_OFFSET + mtspr IVOR6,r4 /* 6: Program check */ + addi r4,r3,FPUnavailable - _start + _START_OFFSET + mtspr IVOR7,r4 /* 7: floating point unavailable */ + addi r4,r3,SystemCall - _start + _START_OFFSET + mtspr IVOR8,r4 /* 8: System call */ /* 9: Auxiliary processor unavailable(unsupported) */ - li r1,0x0a00 - mtspr IVOR10,r1 /* 10: Decrementer */ - li r1,0x0b00 - mtspr IVOR11,r1 /* 11: Interval timer */ - li r1,0x0c00 - mtspr IVOR12,r1 /* 12: Watchdog timer */ - li r1,0x0d00 - mtspr IVOR13,r1 /* 13: Data TLB error */ - li r1,0x0e00 - mtspr IVOR14,r1 /* 14: Instruction TLB error */ - li r1,0x0f00 - mtspr IVOR15,r1 /* 15: Debug */ + addi r4,r3,Decrementer - _start + _START_OFFSET + mtspr IVOR10,r4 /* 10: Decrementer */ + addi r4,r3,IntervalTimer - _start + _START_OFFSET + mtspr IVOR11,r4 /* 11: Interval timer */ + addi r4,r3,WatchdogTimer - _start + _START_OFFSET + mtspr IVOR12,r4 /* 12: Watchdog timer */ + addi r4,r3,DataTLBError - _start + _START_OFFSET + mtspr IVOR13,r4 /* 13: Data TLB error */ + addi r4,r3,InstructionTLBError - _start + _START_OFFSET + mtspr IVOR14,r4 /* 14: Instruction TLB error */ + addi r4,r3,DebugBreakpoint - _start + _START_OFFSET + mtspr IVOR15,r4 /* 15: Debug */ +#endif /* Clear and set up some registers. */ li r0,0x0000 @@ -434,13 +443,15 @@ create_ccsr_new_tlb: ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l +#ifdef CONFIG_ENABLE_36BIT_PHYS lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + mtspr MAS7, r7 +#endif mtspr MAS0, r0 mtspr MAS1, r1 mtspr MAS2, r2 mtspr MAS3, r3 - mtspr MAS7, r7 isync msync tlbwe @@ -456,12 +467,14 @@ create_ccsr_old_tlb: ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l +#ifdef CONFIG_ENABLE_36BIT_PHYS li r7, 0 /* The default CCSR address is always a 32-bit number */ + mtspr MAS7, r7 +#endif mtspr MAS0, r0 /* MAS1 is the same as above */ mtspr MAS2, r2 mtspr MAS3, r3 - mtspr MAS7, r7 isync msync tlbwe @@ -1490,6 +1503,39 @@ trap_init: cmplw 0,r7,r8 blt 2b + /* Update IVORs as per relocated vector table address */ + li r7,0x0100 + mtspr IVOR0,r7 /* 0: Critical input */ + li r7,0x0200 + mtspr IVOR1,r7 /* 1: Machine check */ + li r7,0x0300 + mtspr IVOR2,r7 /* 2: Data storage */ + li r7,0x0400 + mtspr IVOR3,r7 /* 3: Instruction storage */ + li r7,0x0500 + mtspr IVOR4,r7 /* 4: External interrupt */ + li r7,0x0600 + mtspr IVOR5,r7 /* 5: Alignment */ + li r7,0x0700 + mtspr IVOR6,r7 /* 6: Program check */ + li r7,0x0800 + mtspr IVOR7,r7 /* 7: floating point unavailable */ + li r7,0x0900 + mtspr IVOR8,r7 /* 8: System call */ + /* 9: Auxiliary processor unavailable(unsupported) */ + li r7,0x0a00 + mtspr IVOR10,r7 /* 10: Decrementer */ + li r7,0x0b00 + mtspr IVOR11,r7 /* 11: Interval timer */ + li r7,0x0c00 + mtspr IVOR12,r7 /* 12: Watchdog timer */ + li r7,0x0d00 + mtspr IVOR13,r7 /* 13: Data TLB error */ + li r7,0x0e00 + mtspr IVOR14,r7 /* 14: Instruction TLB error */ + li r7,0x0f00 + mtspr IVOR15,r7 /* 15: Debug */ + lis r7,0x0 mtspr IVPR,r7 diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index 04bc73170a..b1a1dac16f 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -87,7 +87,7 @@ SECTIONS .bootpg ADDR(.text) - 0x1000 : { - arch/powerpc/cpu/mpc85xx/start.o KEEP(*(.bootpg)) + KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) } :text = 0xffff . = ADDR(.text) + 0x80000; diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index e46d328067..c7f394972b 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -21,6 +21,16 @@ #include <config.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> +#include <asm/fsl_srio.h> + +#define SRIO_PORT_ACCEPT_ALL 0x10000001 +#define SRIO_IB_ATMU_AR 0x80f55000 +#define SRIO_OB_ATMU_AR_MAINT 0x80077000 +#define SRIO_OB_ATMU_AR_RW 0x80045000 +#define SRIO_LCSBA1CSR_OFFSET 0x5c +#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */ +#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */ +#define SRIO_LCSBA1CSR 0x60000000 #if defined(CONFIG_FSL_CORENET) #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 @@ -84,3 +94,203 @@ void srio_init(void) setbits_be32(&gur->devdisr, _DEVDISR_RMU); } } + +#ifdef CONFIG_SRIOBOOT_MASTER +void srio_boot_master(void) +{ + struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + + /* set port accept-all */ + out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr, + SRIO_PORT_ACCEPT_ALL); + + debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", + CONFIG_SRIOBOOT_MASTER_PORT); + /* configure inbound window for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window for slave's image; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + + /* configure inbound window for slave's u-boot image */ + debug("SRIOBOOT - MASTER: Inbound window for slave's image; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwbar, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + + /* configure inbound window for slave's ucode */ + debug("SRIOBOOT - MASTER: Inbound window for slave's ucode; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS, + (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS, + CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar, + CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar, + CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE)); + + /* configure inbound window for slave's ENV */ + debug("SRIOBOOT - MASTER: Inbound window for slave's ENV; " + "Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n", + CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS, + CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS, + CONFIG_SRIOBOOT_SLAVE_ENV_SIZE); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar, + CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar, + CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar, + SRIO_IB_ATMU_AR + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE)); +} + +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF +void srio_boot_master_release_slave(void) +{ + struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + u32 escsr; + debug("SRIOBOOT - MASTER: " + "Check the port status and release slave core ...\n"); + + escsr = in_be32((void *)&srio->lp_serial + .port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr); + if (escsr & 0x2) { + if (escsr & 0x10100) { + debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n", + CONFIG_SRIOBOOT_MASTER_PORT); + } else { + debug("SRIOBOOT - MASTER: " + "Port [ %d ] is ready, now release slave's core ...\n", + CONFIG_SRIOBOOT_MASTER_PORT); + /* + * configure outbound window + * with maintenance attribute to set slave's LCSBA1CSR + */ + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowtar, 0); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowtear, 0); + if (CONFIG_SRIOBOOT_MASTER_PORT) + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowbar, + CONFIG_SYS_SRIO2_MEM_PHYS >> 12); + else + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowbar, + CONFIG_SYS_SRIO1_MEM_PHYS >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[1].rowar, + SRIO_OB_ATMU_AR_MAINT + | atmu_size_mask(SRIO_MAINT_WIN_SIZE)); + + /* + * configure outbound window + * with R/W attribute to set slave's BRR + */ + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowtar, + SRIO_LCSBA1CSR >> 9); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowtear, 0); + if (CONFIG_SRIOBOOT_MASTER_PORT) + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowbar, + (CONFIG_SYS_SRIO2_MEM_PHYS + + SRIO_MAINT_WIN_SIZE) >> 12); + else + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowbar, + (CONFIG_SYS_SRIO1_MEM_PHYS + + SRIO_MAINT_WIN_SIZE) >> 12); + out_be32((void *)&srio->atmu + .port[CONFIG_SRIOBOOT_MASTER_PORT] + .outbw[2].rowar, + SRIO_OB_ATMU_AR_RW + | atmu_size_mask(SRIO_RW_WIN_SIZE)); + + /* + * Set the LCSBA1CSR register in slave + * by the maint-outbound window + */ + if (CONFIG_SRIOBOOT_MASTER_PORT) { + out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET, + SRIO_LCSBA1CSR); + while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET) + != SRIO_LCSBA1CSR) + ; + /* + * And then set the BRR register + * to release slave core + */ + out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + + SRIO_MAINT_WIN_SIZE + + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, + CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + } else { + out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET, + SRIO_LCSBA1CSR); + while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + + SRIO_LCSBA1CSR_OFFSET) + != SRIO_LCSBA1CSR) + ; + /* + * And then set the BRR register + * to release slave core + */ + out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + + SRIO_MAINT_WIN_SIZE + + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, + CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + } + debug("SRIOBOOT - MASTER: " + "Release slave successfully! Now the slave should start up!\n"); + } + } else + debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", + CONFIG_SRIOBOOT_MASTER_PORT); +} +#endif +#endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8654625fac..191629b628 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -65,6 +65,11 @@ #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_RMU +#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1 @@ -85,6 +90,11 @@ #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_RMU +#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_MPC8569) #define CONFIG_MAX_CPUS 1 @@ -94,6 +104,11 @@ #define MAX_QE_RISC 4 #define QE_NUM_OF_SNUM 46 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_RMU +#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_MPC8572) #define CONFIG_MAX_CPUS 2 @@ -298,6 +313,11 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_RMU +#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_PPC_P2040) #define CONFIG_MAX_CPUS 4 @@ -317,6 +337,9 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #elif defined(CONFIG_PPC_P2041) #define CONFIG_MAX_CPUS 4 @@ -338,6 +361,9 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -359,6 +385,9 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #elif defined(CONFIG_PPC_P3060) #define CONFIG_MAX_CPUS 8 @@ -375,6 +404,9 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 @@ -387,6 +419,9 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -417,6 +452,11 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_RMU +#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) @@ -438,6 +478,9 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -458,6 +501,9 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #else #error Processor type not defined for this platform diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h new file mode 100644 index 0000000000..a905a266c4 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_srio.h @@ -0,0 +1,64 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FSL_SRIO_H_ +#define _FSL_SRIO_H_ + +enum atmu_size { + ATMU_SIZE_4K = 0xb, + ATMU_SIZE_8K, + ATMU_SIZE_16K, + ATMU_SIZE_32K, + ATMU_SIZE_64K, + ATMU_SIZE_128K, + ATMU_SIZE_256K, + ATMU_SIZE_512K, + ATMU_SIZE_1M, + ATMU_SIZE_2M, + ATMU_SIZE_4M, + ATMU_SIZE_8M, + ATMU_SIZE_16M, + ATMU_SIZE_32M, + ATMU_SIZE_64M, + ATMU_SIZE_128M, + ATMU_SIZE_256M, + ATMU_SIZE_512M, + ATMU_SIZE_1G, + ATMU_SIZE_2G, + ATMU_SIZE_4G, + ATMU_SIZE_8G, + ATMU_SIZE_16G, + ATMU_SIZE_32G, + ATMU_SIZE_64G, +}; + +#define atmu_size_mask(sz) (__ilog2_u64(sz) - 1) +#define atmu_size_bytes(x) (1ULL << ((x & 0x3f) + 1)) + +extern void srio_init(void); +#ifdef CONFIG_SRIOBOOT_MASTER +extern void srio_boot_master(void); +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF +extern void srio_boot_master_release_slave(void); +#endif +#endif +#endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9b08cb8c1a..632e3c1669 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1353,171 +1353,235 @@ typedef struct ccsr_cpm { } ccsr_cpm_t; #endif -/* RapidIO Registers */ -typedef struct ccsr_rio { - u32 didcar; /* Device Identity Capability */ - u32 dicar; /* Device Information Capability */ - u32 aidcar; /* Assembly Identity Capability */ - u32 aicar; /* Assembly Information Capability */ - u32 pefcar; /* Processing Element Features Capability */ - u32 spicar; /* Switch Port Information Capability */ - u32 socar; /* Source Operations Capability */ - u32 docar; /* Destination Operations Capability */ +#ifdef CONFIG_SYS_SRIO +/* Architectural regsiters */ +struct rio_arch { + u32 didcar; /* Device Identity CAR */ + u32 dicar; /* Device Information CAR */ + u32 aidcar; /* Assembly Identity CAR */ + u32 aicar; /* Assembly Information CAR */ + u32 pefcar; /* Processing Element Features CAR */ + u8 res0[4]; + u32 socar; /* Source Operations CAR */ + u32 docar; /* Destination Operations CAR */ u8 res1[32]; - u32 msr; /* Mailbox Cmd And Status */ - u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */ + u32 mcsr; /* Mailbox CSR */ + u32 pwdcsr; /* Port-Write and Doorbell CSR */ u8 res2[4]; u32 pellccsr; /* Processing Element Logic Layer CCSR */ u8 res3[12]; - u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */ - u32 bdidcsr; /* Base Device ID Cmd & Status */ + u32 lcsbacsr; /* Local Configuration Space BACSR */ + u32 bdidcsr; /* Base Device ID CSR */ u8 res4[4]; - u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */ - u32 ctcsr; /* Component Tag Cmd & Status */ - u8 res5[144]; - u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */ - u8 res6[28]; - u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */ - u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */ - u8 res7[20]; - u32 pgccsr; /* Port General Cmd & Status */ - u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */ - u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */ - u32 plascsr; /* Port Local Ackid Status Cmd & Status */ - u8 res8[12]; - u32 pescsr; /* Port Error & Status Cmd & Status */ - u32 pccsr; /* Port Control Cmd & Status */ - u8 res9[65184]; - u32 cr; /* Port Control Cmd & Status */ - u8 res10[12]; - u32 pcr; /* Port Configuration */ - u32 peir; /* Port Error Injection */ - u8 res11[3048]; - u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */ - u8 res12[12]; - u32 rowar0; /* RIO Outbound Attrs 0 */ - u8 res13[12]; - u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */ - u8 res14[4]; - u32 rowbar1; /* RIO Outbound Window Base Addr 1 */ - u8 res15[4]; - u32 rowar1; /* RIO Outbound Attrs 1 */ - u8 res16[12]; - u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */ - u8 res17[4]; - u32 rowbar2; /* RIO Outbound Window Base Addr 2 */ - u8 res18[4]; - u32 rowar2; /* RIO Outbound Attrs 2 */ - u8 res19[12]; - u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */ - u8 res20[4]; - u32 rowbar3; /* RIO Outbound Window Base Addr 3 */ - u8 res21[4]; - u32 rowar3; /* RIO Outbound Attrs 3 */ - u8 res22[12]; - u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */ - u8 res23[4]; - u32 rowbar4; /* RIO Outbound Window Base Addr 4 */ - u8 res24[4]; - u32 rowar4; /* RIO Outbound Attrs 4 */ - u8 res25[12]; - u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */ - u8 res26[4]; - u32 rowbar5; /* RIO Outbound Window Base Addr 5 */ - u8 res27[4]; - u32 rowar5; /* RIO Outbound Attrs 5 */ - u8 res28[12]; - u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */ - u8 res29[4]; - u32 rowbar6; /* RIO Outbound Window Base Addr 6 */ - u8 res30[4]; - u32 rowar6; /* RIO Outbound Attrs 6 */ - u8 res31[12]; - u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */ - u8 res32[4]; - u32 rowbar7; /* RIO Outbound Window Base Addr 7 */ - u8 res33[4]; - u32 rowar7; /* RIO Outbound Attrs 7 */ - u8 res34[12]; - u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */ - u8 res35[4]; - u32 rowbar8; /* RIO Outbound Window Base Addr 8 */ - u8 res36[4]; - u32 rowar8; /* RIO Outbound Attrs 8 */ - u8 res37[76]; - u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */ - u8 res38[4]; - u32 riwbar4; /* RIO Inbound Window Base Addr 4 */ - u8 res39[4]; - u32 riwar4; /* RIO Inbound Attrs 4 */ - u8 res40[12]; - u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */ - u8 res41[4]; - u32 riwbar3; /* RIO Inbound Window Base Addr 3 */ - u8 res42[4]; - u32 riwar3; /* RIO Inbound Attrs 3 */ - u8 res43[12]; - u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */ - u8 res44[4]; - u32 riwbar2; /* RIO Inbound Window Base Addr 2 */ - u8 res45[4]; - u32 riwar2; /* RIO Inbound Attrs 2 */ - u8 res46[12]; - u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */ - u8 res47[4]; - u32 riwbar1; /* RIO Inbound Window Base Addr 1 */ - u8 res48[4]; - u32 riwar1; /* RIO Inbound Attrs 1 */ - u8 res49[12]; - u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */ - u8 res50[12]; - u32 riwar0; /* RIO Inbound Attrs 0 */ - u8 res51[12]; - u32 pnfedr; /* Port Notification/Fatal Error Detect */ - u32 pnfedir; /* Port Notification/Fatal Error Detect */ - u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */ - u32 pecr; /* Port Error Control */ - u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */ - u32 pepr1; /* Port Error Packet 1 */ - u32 pepr2; /* Port Error Packet 2 */ - u8 res52[4]; - u32 predr; /* Port Recoverable Error Detect */ - u8 res53[4]; - u32 pertr; /* Port Error Recovery Threshold */ - u32 prtr; /* Port Retry Threshold */ - u8 res54[464]; - u32 omr; /* Outbound Mode */ - u32 osr; /* Outbound Status */ - u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */ - u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */ - u32 eosar; /* Extended Outbound Unit Source Addr */ - u32 osar; /* Outbound Unit Source Addr */ - u32 odpr; /* Outbound Destination Port */ - u32 odatr; /* Outbound Destination Attrs */ - u32 odcr; /* Outbound Doubleword Count */ - u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */ - u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */ - u8 res55[52]; - u32 imr; /* Outbound Mode */ - u32 isr; /* Inbound Status */ - u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */ - u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */ - u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */ - u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */ - u8 res56[1000]; - u32 dmr; /* Doorbell Mode */ - u32 dsr; /* Doorbell Status */ - u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */ - u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */ - u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */ - u32 dqhpar; /* Doorbell Queue Head Ptr Addr */ - u8 res57[104]; - u32 pwmr; /* Port-Write Mode */ - u32 pwsr; /* Port-Write Status */ - u32 epwqbar; /* Extended Port-Write Queue Base Addr */ - u32 pwqbar; /* Port-Write Queue Base Addr */ - u8 res58[60176]; -} ccsr_rio_t; + u32 hbdidlcsr; /* Host Base Device ID Lock CSR */ + u32 ctcsr; /* Component Tag CSR */ +}; + +/* Extended Features Space: 1x/4x LP-Serial Port registers */ +struct rio_lp_serial_port { + u32 plmreqcsr; /* Port Link Maintenance Request CSR */ + u32 plmrespcsr; /* Port Link Maintenance Response CS */ + u32 plascsr; /* Port Local Ackid Status CSR */ + u8 res0[12]; + u32 pescsr; /* Port Error and Status CSR */ + u32 pccsr; /* Port Control CSR */ +}; + +/* Extended Features Space: 1x/4x LP-Serial registers */ +struct rio_lp_serial { + u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */ + u8 res0[28]; + u32 pltoccsr; /* Port Link Time-out CCSR */ + u32 prtoccsr; /* Port Response Time-out CCSR */ + u8 res1[20]; + u32 pgccsr; /* Port General CSR */ + struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; +}; + +/* Logical error reporting registers */ +struct rio_logical_err { + u32 erbh; /* Error Reporting Block Header Register */ + u8 res0[4]; + u32 ltledcsr; /* Logical/Transport layer error DCSR */ + u32 ltleecsr; /* Logical/Transport layer error ECSR */ + u8 res1[4]; + u32 ltlaccsr; /* Logical/Transport layer ACCSR */ + u32 ltldidccsr; /* Logical/Transport layer DID CCSR */ + u32 ltlcccsr; /* Logical/Transport layer control CCSR */ +}; + +/* Physical error reporting port registers */ +struct rio_phys_err_port { + u32 edcsr; /* Port error detect CSR */ + u32 erecsr; /* Port error rate enable CSR */ + u32 ecacsr; /* Port error capture attributes CSR */ + u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */ + u32 peccsr[3]; /* Port error capture CSR */ + u8 res0[12]; + u32 ercsr; /* Port error rate CSR */ + u32 ertcsr; /* Port error rate threshold CSR */ + u8 res1[16]; +}; + +/* Physical error reporting registers */ +struct rio_phys_err { + struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; +}; + +/* Implementation Space: General Port-Common */ +struct rio_impl_common { + u8 res0[4]; + u32 llcr; /* Logical Layer Configuration Register */ + u8 res1[8]; + u32 epwisr; /* Error / Port-Write Interrupt SR */ + u8 res2[12]; + u32 lretcr; /* Logical Retry Error Threshold CR */ + u8 res3[92]; + u32 pretcr; /* Physical Retry Erorr Threshold CR */ + u8 res4[124]; +}; + +/* Implementation Space: Port Specific */ +struct rio_impl_port_spec { + u32 adidcsr; /* Port Alt. Device ID CSR */ + u8 res0[28]; + u32 ptaacr; /* Port Pass-Through/Accept-All CR */ + u32 lopttlcr; + u8 res1[8]; + u32 iecsr; /* Port Implementation Error CSR */ + u8 res2[12]; + u32 pcr; /* Port Phsyical Configuration Register */ + u8 res3[20]; + u32 slcsr; /* Port Serial Link CSR */ + u8 res4[4]; + u32 sleicr; /* Port Serial Link Error Injection */ + u32 a0txcr; /* Port Arbitration 0 Tx CR */ + u32 a1txcr; /* Port Arbitration 1 Tx CR */ + u32 a2txcr; /* Port Arbitration 2 Tx CR */ + u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */ + u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */ +}; + +/* Implementation Space: register */ +struct rio_implement { + struct rio_impl_common com; + struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; +}; + +/* Revision Control Register */ +struct rio_rev_ctrl { + u32 ipbrr[2]; /* IP Block Revision Register */ +}; + +struct rio_atmu_row { + u32 rowtar; /* RapidIO Outbound Window TAR */ + u32 rowtear; /* RapidIO Outbound Window TEAR */ + u32 rowbar; + u8 res0[4]; + u32 rowar; /* RapidIO Outbound Attributes Register */ + u32 rowsr[3]; /* Port RapidIO outbound window segment register */ +}; + +struct rio_atmu_riw { + u32 riwtar; /* RapidIO Inbound Window Translation AR */ + u8 res0[4]; + u32 riwbar; /* RapidIO Inbound Window Base AR */ + u8 res1[4]; + u32 riwar; /* RapidIO Inbound Attributes Register */ + u8 res2[12]; +}; + +/* ATMU window registers */ +struct rio_atmu_win { + struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM]; + u8 res0[64]; + struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM]; +}; + +struct rio_atmu { + struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; +}; + +#ifdef CONFIG_SYS_FSL_RMU +struct rio_msg { + u32 omr; /* Outbound Mode Register */ + u32 osr; /* Outbound Status Register */ + u32 eodqdpar; /* Extended Outbound DQ DPAR */ + u32 odqdpar; /* Outbound Descriptor Queue DPAR */ + u32 eosar; /* Extended Outbound Unit Source AR */ + u32 osar; /* Outbound Unit Source AR */ + u32 odpr; /* Outbound Destination Port Register */ + u32 odatr; /* Outbound Destination Attributes Register */ + u32 odcr; /* Outbound Doubleword Count Register */ + u32 eodqepar; /* Extended Outbound DQ EPAR */ + u32 odqepar; /* Outbound Descriptor Queue EPAR */ + u32 oretr; /* Outbound Retry Error Threshold Register */ + u32 omgr; /* Outbound Multicast Group Register */ + u32 omlr; /* Outbound Multicast List Register */ + u8 res0[40]; + u32 imr; /* Outbound Mode Register */ + u32 isr; /* Inbound Status Register */ + u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */ + u32 idqdpar; /* Inbound Descriptor Queue DPAR */ + u32 eifqepar; /* Extended Inbound Frame Queue EPAR */ + u32 ifqepar; /* Inbound Frame Queue EPAR */ + u32 imirir; /* Inbound Maximum Interrutp RIR */ + u8 res1[4]; + u32 eihqepar; /* Extended inbound message header queue EPAR */ + u32 ihqepar; /* Inbound message header queue EPAR */ + u8 res2[120]; +}; + +struct rio_dbell { + u32 odmr; /* Outbound Doorbell Mode Register */ + u32 odsr; /* Outbound Doorbell Status Register */ + u8 res0[16]; + u32 oddpr; /* Outbound Doorbell Destination Port */ + u32 oddatr; /* Outbound Doorbell Destination AR */ + u8 res1[12]; + u32 oddretr; /* Outbound Doorbell Retry Threshold CR */ + u8 res2[48]; + u32 idmr; /* Inbound Doorbell Mode Register */ + u32 idsr; /* Inbound Doorbell Status Register */ + u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */ + u32 iqdpar; /* Inbound Doorbell Queue DPAR */ + u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */ + u32 idqepar; /* Inbound Doorbell Queue EPAR */ + u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */ +}; + +struct rio_pw { + u32 pwmr; /* Port-Write Mode Register */ + u32 pwsr; /* Port-Write Status Register */ + u32 epwqbar; /* Extended Port-Write Queue BAR */ + u32 pwqbar; /* Port-Write Queue Base Address Register */ +}; +#endif + +/* RapidIO Registers */ +struct ccsr_rio { + struct rio_arch arch; + u8 res0[144]; + struct rio_lp_serial lp_serial; + u8 res1[1152]; + struct rio_logical_err logical_err; + u8 res2[32]; + struct rio_phys_err phys_err; + u8 res3[63808]; + struct rio_implement impl; + u8 res4[2552]; + struct rio_rev_ctrl rev; + struct rio_atmu atmu; +#ifdef CONFIG_SYS_FSL_RMU + u8 res5[8192]; + struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM]; + u8 res6[512]; + struct rio_dbell dbell; + u8 res7[100]; + struct rio_pw pw; +#endif +}; +#endif /* Quick Engine Block Pin Muxing Registers */ typedef struct par_io { @@ -2443,6 +2507,7 @@ struct ccsr_rman { #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 +#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) @@ -2516,6 +2581,8 @@ struct ccsr_rman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) #define CONFIG_SYS_FSL_FM2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) +#define CONFIG_SYS_FSL_SRIO_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET) #define CONFIG_SYS_PCI1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) |