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-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig321
-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile103
-rw-r--r--arch/powerpc/cpu/mpc85xx/b4860_ids.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/b4860_serdes.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c11
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c6
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init_early.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c13
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c6
-rw-r--r--arch/powerpc/cpu/mpc85xx/pci.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c36
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S6
-rw-r--r--arch/powerpc/cpu/mpc85xx/t2080_serdes.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/t4240_serdes.c4
-rw-r--r--arch/powerpc/cpu/mpc86xx/Kconfig10
-rw-r--r--arch/powerpc/cpu/mpc86xx/Makefile4
-rw-r--r--arch/powerpc/cpu/mpc86xx/cpu.c6
-rw-r--r--arch/powerpc/cpu/mpc86xx/speed.c2
-rw-r--r--arch/powerpc/include/asm/config.h4
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h205
-rw-r--r--arch/powerpc/include/asm/config_mpc86xx.h6
-rw-r--r--arch/powerpc/include/asm/cpm_85xx.h2
-rw-r--r--arch/powerpc/include/asm/fsl_law.h12
-rw-r--r--arch/powerpc/include/asm/fsl_lbc.h6
-rw-r--r--arch/powerpc/include/asm/fsl_secure_boot.h39
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h98
-rw-r--r--arch/powerpc/include/asm/immap_86xx.h2
-rw-r--r--arch/powerpc/include/asm/processor.h2
30 files changed, 545 insertions, 381 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 9bcbda006d..3ee7d2f0c5 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -10,25 +10,37 @@ choice
config TARGET_SBC8548
bool "Support sbc8548"
+ select ARCH_MPC8548
config TARGET_SOCRATES
bool "Support socrates"
+ select ARCH_MPC8544
+
+config TARGET_B4420QDS
+ bool "Support B4420QDS"
+ select ARCH_B4420
+ select SUPPORT_SPL
+ select PHYS_64BIT
config TARGET_B4860QDS
bool "Support B4860QDS"
+ select ARCH_B4860
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_BSC9131RDB
bool "Support BSC9131RDB"
+ select ARCH_BSC9131
select SUPPORT_SPL
config TARGET_BSC9132QDS
bool "Support BSC9132QDS"
+ select ARCH_BSC9132
select SUPPORT_SPL
config TARGET_C29XPCIE
bool "Support C29XPCIE"
+ select ARCH_C29X
select SUPPORT_SPL
select SUPPORT_TPL
select PHYS_64BIT
@@ -36,135 +48,266 @@ config TARGET_C29XPCIE
config TARGET_P3041DS
bool "Support P3041DS"
select PHYS_64BIT
+ select ARCH_P3041
config TARGET_P4080DS
bool "Support P4080DS"
select PHYS_64BIT
+ select ARCH_P4080
config TARGET_P5020DS
bool "Support P5020DS"
select PHYS_64BIT
+ select ARCH_P5020
config TARGET_P5040DS
bool "Support P5040DS"
select PHYS_64BIT
+ select ARCH_P5040
config TARGET_MPC8536DS
bool "Support MPC8536DS"
+ select ARCH_MPC8536
config TARGET_MPC8540ADS
bool "Support MPC8540ADS"
+ select ARCH_MPC8540
config TARGET_MPC8541CDS
bool "Support MPC8541CDS"
+ select ARCH_MPC8541
config TARGET_MPC8544DS
bool "Support MPC8544DS"
+ select ARCH_MPC8544
config TARGET_MPC8548CDS
bool "Support MPC8548CDS"
+ select ARCH_MPC8548
config TARGET_MPC8555CDS
bool "Support MPC8555CDS"
+ select ARCH_MPC8555
config TARGET_MPC8560ADS
bool "Support MPC8560ADS"
+ select ARCH_MPC8560
config TARGET_MPC8568MDS
bool "Support MPC8568MDS"
+ select ARCH_MPC8568
config TARGET_MPC8569MDS
bool "Support MPC8569MDS"
+ select ARCH_MPC8569
config TARGET_MPC8572DS
bool "Support MPC8572DS"
+ select ARCH_MPC8572
+
+config TARGET_P1010RDB_PA
+ bool "Support P1010RDB_PA"
+ select ARCH_P1010
+ select SUPPORT_SPL
+ select SUPPORT_TPL
-config TARGET_P1010RDB
- bool "Support P1010RDB"
+config TARGET_P1010RDB_PB
+ bool "Support P1010RDB_PB"
+ select ARCH_P1010
select SUPPORT_SPL
select SUPPORT_TPL
config TARGET_P1022DS
bool "Support P1022DS"
+ select ARCH_P1022
select SUPPORT_SPL
select SUPPORT_TPL
config TARGET_P1023RDB
bool "Support P1023RDB"
+ select ARCH_P1023
+
+config TARGET_P1020MBG
+ bool "Support P1020MBG-PC"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P1020
+
+config TARGET_P1020RDB_PC
+ bool "Support P1020RDB-PC"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P1020
-config TARGET_P1_P2_RDB_PC
- bool "Support p1_p2_rdb_pc"
+config TARGET_P1020RDB_PD
+ bool "Support P1020RDB-PD"
select SUPPORT_SPL
select SUPPORT_TPL
+ select ARCH_P1020
+
+config TARGET_P1020UTM
+ bool "Support P1020UTM"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P1020
+
+config TARGET_P1021RDB
+ bool "Support P1021RDB"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P1021
+
+config TARGET_P1024RDB
+ bool "Support P1024RDB"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P1024
+
+config TARGET_P1025RDB
+ bool "Support P1025RDB"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P1025
+
+config TARGET_P2020RDB
+ bool "Support P2020RDB-PC"
+ select SUPPORT_SPL
+ select SUPPORT_TPL
+ select ARCH_P2020
config TARGET_P1_TWR
bool "Support p1_twr"
+ select ARCH_P1025
config TARGET_P2041RDB
bool "Support P2041RDB"
+ select ARCH_P2041
select PHYS_64BIT
config TARGET_QEMU_PPCE500
bool "Support qemu-ppce500"
+ select ARCH_QEMU_E500
select PHYS_64BIT
-config TARGET_T102XQDS
- bool "Support T102xQDS"
+config TARGET_T1024QDS
+ bool "Support T1024QDS"
+ select ARCH_T1024
select SUPPORT_SPL
select PHYS_64BIT
-config TARGET_T102XRDB
- bool "Support T102xRDB"
+config TARGET_T1023RDB
+ bool "Support T1023RDB"
+ select ARCH_T1023
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T1024RDB
+ bool "Support T1024RDB"
+ select ARCH_T1024
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_T1040QDS
bool "Support T1040QDS"
+ select ARCH_T1040
+ select PHYS_64BIT
+
+config TARGET_T1040RDB
+ bool "Support T1040RDB"
+ select ARCH_T1040
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T1040D4RDB
+ bool "Support T1040D4RDB"
+ select ARCH_T1040
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T1042RDB
+ bool "Support T1042RDB"
+ select ARCH_T1042
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T1042D4RDB
+ bool "Support T1042D4RDB"
+ select ARCH_T1042
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T1042RDB_PI
+ bool "Support T1042RDB_PI"
+ select ARCH_T1042
+ select SUPPORT_SPL
select PHYS_64BIT
-config TARGET_T104XRDB
- bool "Support T104xRDB"
+config TARGET_T2080QDS
+ bool "Support T2080QDS"
+ select ARCH_T2080
select SUPPORT_SPL
select PHYS_64BIT
-config TARGET_T208XQDS
- bool "Support T208xQDS"
+config TARGET_T2080RDB
+ bool "Support T2080RDB"
+ select ARCH_T2080
select SUPPORT_SPL
select PHYS_64BIT
-config TARGET_T208XRDB
- bool "Support T208xRDB"
+config TARGET_T2081QDS
+ bool "Support T2081QDS"
+ select ARCH_T2081
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T4160QDS
+ bool "Support T4160QDS"
+ select ARCH_T4160
+ select SUPPORT_SPL
+ select PHYS_64BIT
+
+config TARGET_T4160RDB
+ bool "Support T4160RDB"
+ select ARCH_T4160
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_T4240QDS
bool "Support T4240QDS"
+ select ARCH_T4240
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_T4240RDB
bool "Support T4240RDB"
+ select ARCH_T4240
select SUPPORT_SPL
select PHYS_64BIT
config TARGET_CONTROLCENTERD
bool "Support controlcenterd"
+ select ARCH_P1022
config TARGET_KMP204X
bool "Support kmp204x"
+ select ARCH_P2041
select PHYS_64BIT
config TARGET_XPEDITE520X
bool "Support xpedite520x"
+ select ARCH_MPC8548
config TARGET_XPEDITE537X
bool "Support xpedite537x"
+ select ARCH_MPC8572
config TARGET_XPEDITE550X
bool "Support xpedite550x"
+ select ARCH_P2020
config TARGET_UCP1020
bool "Support uCP1020"
+ select ARCH_P1020
config TARGET_CYRUS
bool "Support Varisys Cyrus"
@@ -172,6 +315,156 @@ config TARGET_CYRUS
endchoice
+config ARCH_B4420
+ bool
+
+config ARCH_B4860
+ bool
+
+config ARCH_BSC9131
+ bool
+
+config ARCH_BSC9132
+ bool
+
+config ARCH_C29X
+ bool
+
+config ARCH_MPC8536
+ bool
+
+config ARCH_MPC8540
+ bool
+
+config ARCH_MPC8541
+ bool
+
+config ARCH_MPC8544
+ bool
+
+config ARCH_MPC8548
+ bool
+
+config ARCH_MPC8555
+ bool
+
+config ARCH_MPC8560
+ bool
+
+config ARCH_MPC8568
+ bool
+
+config ARCH_MPC8569
+ bool
+
+config ARCH_MPC8572
+ bool
+
+config ARCH_P1010
+ bool
+
+config ARCH_P1011
+ bool
+
+config ARCH_P1020
+ bool
+
+config ARCH_P1021
+ bool
+
+config ARCH_P1022
+ bool
+
+config ARCH_P1023
+ bool
+
+config ARCH_P1024
+ bool
+
+config ARCH_P1025
+ bool
+
+config ARCH_P2020
+ bool
+
+config ARCH_P2041
+ bool
+
+config ARCH_P3041
+ bool
+
+config ARCH_P4080
+ bool
+
+config ARCH_P5020
+ bool
+
+config ARCH_P5040
+ bool
+
+config ARCH_QEMU_E500
+ bool
+
+config ARCH_T1023
+ bool
+
+config ARCH_T1024
+ bool
+
+config ARCH_T1040
+ bool
+
+config ARCH_T1042
+ bool
+
+config ARCH_T2080
+ bool
+
+config ARCH_T2081
+ bool
+
+config ARCH_T4160
+ bool
+
+config ARCH_T4240
+ bool
+
+config MAX_CPUS
+ int "Maximum number of CPUs permitted for MPC85xx"
+ default 12 if ARCH_T4240
+ default 8 if ARCH_P4080 || \
+ ARCH_T4160
+ default 4 if ARCH_B4860 || \
+ ARCH_P2041 || \
+ ARCH_P3041 || \
+ ARCH_P5040 || \
+ ARCH_T1040 || \
+ ARCH_T1042 || \
+ ARCH_T2080 || \
+ ARCH_T2081
+ default 2 if ARCH_B4420 || \
+ ARCH_BSC9132 || \
+ ARCH_MPC8572 || \
+ ARCH_P1020 || \
+ ARCH_P1021 || \
+ ARCH_P1022 || \
+ ARCH_P1023 || \
+ ARCH_P1024 || \
+ ARCH_P1025 || \
+ ARCH_P2020 || \
+ ARCH_P5020 || \
+ ARCH_T1020 || \
+ ARCH_T1022 || \
+ ARCH_T1023 || \
+ ARCH_T1024
+ default 1
+ help
+ Set this number to the maximum number of possible CPUs in the SoC.
+ SoCs may have multiple clusters with each cluster may have multiple
+ ports. If some ports are reserved but higher ports are used for
+ cores, count the reserved ports. This will allocate enough memory
+ in spin table to properly handle all cores.
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index f4c4fe2602..46ed22cafc 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -39,24 +39,23 @@ obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments
-obj-$(CONFIG_PPC_P2041) += p2041_ids.o
-obj-$(CONFIG_PPC_P3041) += p3041_ids.o
-obj-$(CONFIG_PPC_P4080) += p4080_ids.o
-obj-$(CONFIG_PPC_P5020) += p5020_ids.o
-obj-$(CONFIG_PPC_P5040) += p5040_ids.o
-obj-$(CONFIG_PPC_T4240) += t4240_ids.o
-obj-$(CONFIG_PPC_T4160) += t4240_ids.o
-obj-$(CONFIG_PPC_T4080) += t4240_ids.o
-obj-$(CONFIG_PPC_B4420) += b4860_ids.o
-obj-$(CONFIG_PPC_B4860) += b4860_ids.o
-obj-$(CONFIG_PPC_T1040) += t1040_ids.o
-obj-$(CONFIG_PPC_T1042) += t1040_ids.o
+obj-$(CONFIG_ARCH_P2041) += p2041_ids.o
+obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
+obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
+obj-$(CONFIG_ARCH_P5020) += p5020_ids.o
+obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
+obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
+obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
+obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
+obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
+obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
+obj-$(CONFIG_ARCH_T1042) += t1040_ids.o
obj-$(CONFIG_PPC_T1020) += t1040_ids.o
obj-$(CONFIG_PPC_T1022) += t1040_ids.o
-obj-$(CONFIG_PPC_T1023) += t1024_ids.o
-obj-$(CONFIG_PPC_T1024) += t1024_ids.o
-obj-$(CONFIG_PPC_T2080) += t2080_ids.o
-obj-$(CONFIG_PPC_T2081) += t2080_ids.o
+obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
+obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
+obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
+obj-$(CONFIG_ARCH_T2081) += t2080_ids.o
obj-$(CONFIG_QE) += qe_io.o
@@ -65,52 +64,46 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
# SoC specific SERDES support
-obj-$(CONFIG_PPC_C29X) += c29x_serdes.o
-obj-$(CONFIG_MPC8536) += mpc8536_serdes.o
-obj-$(CONFIG_MPC8544) += mpc8544_serdes.o
-obj-$(CONFIG_MPC8548) += mpc8548_serdes.o
-obj-$(CONFIG_MPC8568) += mpc8568_serdes.o
-obj-$(CONFIG_MPC8569) += mpc8569_serdes.o
-obj-$(CONFIG_MPC8572) += mpc8572_serdes.o
-obj-$(CONFIG_P1010) += p1010_serdes.o
-obj-$(CONFIG_P1011) += p1021_serdes.o
-obj-$(CONFIG_P1012) += p1021_serdes.o
-obj-$(CONFIG_P1013) += p1022_serdes.o
-obj-$(CONFIG_P1014) += p1010_serdes.o
-obj-$(CONFIG_P1017) += p1023_serdes.o
-obj-$(CONFIG_P1020) += p1021_serdes.o
-obj-$(CONFIG_P1021) += p1021_serdes.o
-obj-$(CONFIG_P1022) += p1022_serdes.o
-obj-$(CONFIG_P1023) += p1023_serdes.o
-obj-$(CONFIG_P1024) += p1021_serdes.o
-obj-$(CONFIG_P1025) += p1021_serdes.o
-obj-$(CONFIG_P2010) += p2020_serdes.o
-obj-$(CONFIG_P2020) += p2020_serdes.o
-obj-$(CONFIG_PPC_P2041) += p2041_serdes.o
-obj-$(CONFIG_PPC_P3041) += p3041_serdes.o
-obj-$(CONFIG_PPC_P4080) += p4080_serdes.o
-obj-$(CONFIG_PPC_P5020) += p5020_serdes.o
-obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
-obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
-obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
-obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
-obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
-obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
-obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
-obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
-obj-$(CONFIG_PPC_T1042) += t1040_serdes.o
+obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o
+obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
+obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
+obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
+obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o
+obj-$(CONFIG_ARCH_MPC8569) += mpc8569_serdes.o
+obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
+obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
+obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
+obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
+obj-$(CONFIG_ARCH_P1021) += p1021_serdes.o
+obj-$(CONFIG_ARCH_P1022) += p1022_serdes.o
+obj-$(CONFIG_ARCH_P1023) += p1023_serdes.o
+obj-$(CONFIG_ARCH_P1024) += p1021_serdes.o
+obj-$(CONFIG_ARCH_P1025) += p1021_serdes.o
+obj-$(CONFIG_ARCH_P2020) += p2020_serdes.o
+obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
+obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
+obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
+obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o
+obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
+obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
+obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
+obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
+obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
+obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
+obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o
+obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o
obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
-obj-$(CONFIG_PPC_T1023) += t1024_serdes.o
-obj-$(CONFIG_PPC_T1024) += t1024_serdes.o
-obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
-obj-$(CONFIG_PPC_T2081) += t2080_serdes.o
+obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
+obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
+obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o
+obj-$(CONFIG_ARCH_T2081) += t2080_serdes.o
obj-y += cpu.o
obj-y += cpu_init.o
obj-y += cpu_init_early.o
obj-y += interrupts.o
-ifneq ($(CONFIG_QEMU_E500),y)
+ifneq ($(CONFIG_ARCH_QEMU_E500),y)
obj-y += speed.o
endif
obj-y += tlb.o
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 85eba0b22d..4ceb6f51f3 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -62,7 +62,7 @@ struct liodn_id_table liodn_tbl[] = {
SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
-#ifndef CONFIG_PPC_B4420
+#ifndef CONFIG_ARCH_B4420
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
@@ -81,7 +81,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = {
SET_FMAN_RX_1G_LIODN(1, 3, 91),
SET_FMAN_RX_1G_LIODN(1, 4, 92),
SET_FMAN_RX_1G_LIODN(1, 5, 93),
-#ifndef CONFIG_PPC_B4420
+#ifndef CONFIG_ARCH_B4420
SET_FMAN_RX_10G_LIODN(1, 0, 94),
SET_FMAN_RX_10G_LIODN(1, 1, 95),
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index 63172def68..a5709dddc0 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -15,7 +15,7 @@ struct serdes_config {
u8 lanes[SRDS_MAX_LANES];
};
-#ifdef CONFIG_PPC_B4860
+#ifdef CONFIG_ARCH_B4860
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0x01, {AURORA, AURORA, CPRI6, CPRI5,
@@ -180,7 +180,7 @@ static struct serdes_config serdes2_cfg_tbl[] = {
};
#endif
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
static struct serdes_config serdes1_cfg_tbl[] = {
{0x0D, {NONE, NONE, CPRI6, CPRI5,
CPRI4, CPRI3, NONE, NONE} },
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3b06ae42e4..402a1ff33c 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -26,12 +26,12 @@ static void check_erratum_a4849(uint32_t svr)
void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
unsigned int i;
-#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
+#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
static const uint8_t offsets[] = {
0x50, 0x54, 0x58, 0x90, 0x94, 0x98
};
#endif
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
static const uint8_t offsets[] = {
0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
};
@@ -45,11 +45,11 @@ static void check_erratum_a4849(uint32_t svr)
}
}
-#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
+#if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
x108 = 0x12;
#endif
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
/*
* For P4080, the erratum document says that the value at offset 0x108
* should be 0x12 on rev2, or 0x1c on rev3.
@@ -323,7 +323,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (IS_SVR_REV(svr, 1, 0))
puts("Work-around for Erratum A-008044 enabled\n");
#endif
-#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS)
+#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && \
+ (defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS))
puts("Work-around for Erratum XFI on B4860QDS enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index cabf64cf8c..d180c73929 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -293,8 +293,8 @@ int checkcpu (void)
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* Everything after the first generation of PQ3 parts has RSTCR */
-#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
+ defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
unsigned long val, msr;
/*
@@ -404,7 +404,7 @@ void mpc85xx_reginfo(void)
phys_size_t initdram(int board_type)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
- defined(CONFIG_QEMU_E500)
+ defined(CONFIG_ARCH_QEMU_E500)
return fsl_ddr_sdram_size();
#else
return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 53b3729f98..c2402a8bda 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -442,7 +442,7 @@ ulong cpu_init_f(void)
#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
struct law_entry law;
#endif
-#ifdef CONFIG_MPC8548
+#ifdef CONFIG_ARCH_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
uint svr = get_svr();
@@ -959,7 +959,7 @@ int cpu_init_r(void)
#ifdef CONFIG_FSL_CAAM
sec_init();
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
if ((SVR_SOC_VER(svr) == SVR_C292) ||
(SVR_SOC_VER(svr) == SVR_C293))
sec_init_idx(1);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index aa519b03fe..345d693ec4 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -97,7 +97,7 @@ void cpu_init_early_f(void *fdt)
/* gd area was zeroed during startup */
-#ifdef CONFIG_QEMU_E500
+#ifdef CONFIG_ARCH_QEMU_E500
/*
* CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
* so we need to populate it before it accesses it.
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 047c972ac7..12001f85e9 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -490,7 +490,7 @@ static void ft_fixup_qe_snum(void *blob)
}
#endif
-#if defined(CONFIG_PPC_P4080)
+#if defined(CONFIG_ARCH_P4080)
static void fdt_fixup_usb(void *fdt)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -511,8 +511,8 @@ static void fdt_fixup_usb(void *fdt)
#define fdt_fixup_usb(x)
#endif
-#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T4240) || \
- defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
+#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
+ defined(CONFIG_ARCH_T4160)
void fdt_fixup_dma3(void *blob)
{
/* the 3rd DMA is not functional if SRIO2 is chosen */
@@ -520,7 +520,7 @@ void fdt_fixup_dma3(void *blob)
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
-#if defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_ARCH_T2080)
u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
@@ -529,8 +529,7 @@ void fdt_fixup_dma3(void *blob)
case 0x29:
case 0x2d:
case 0x2e:
-#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
- defined(CONFIG_PPC_T4080)
+#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
@@ -556,7 +555,7 @@ void fdt_fixup_dma3(void *blob)
#define fdt_fixup_dma3(x)
#endif
-#if defined(CONFIG_PPC_T1040)
+#if defined(CONFIG_ARCH_T1040)
static void fdt_fixup_l2_switch(void *blob)
{
uchar l2swaddr[6];
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 810ddb0867..677b062044 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -391,7 +391,7 @@ const char *serdes_clock_to_string(u32 clock)
case SRDS_PLLCR0_RFCK_SEL_161_13:
return "161.1328123";
default:
-#if defined(CONFIG_T4240QDS)
+#if defined(CONFIG_TARGET_T4240QDS) || defined(CONFIG_TARGET_T4160QDS)
return "???";
#else
return "122.88";
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index b6c4341544..1bc0c64cfc 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -76,7 +76,7 @@ static const struct {
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
@@ -491,7 +491,7 @@ void fsl_serdes_init(void)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
serdes_corenet_t *srds2_regs;
#endif
int lane, bank, idx;
@@ -577,7 +577,7 @@ void fsl_serdes_init(void)
}
}
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
/*
* Lanes on bank 4 on P5040 are commented-out, but for some SERDES
* protocols, these lanes are routed to SATA. We use serdes_prtcl_map
diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c
index c6d2fda5db..538729f388 100644
--- a/arch/powerpc/cpu/mpc85xx/pci.c
+++ b/arch/powerpc/cpu/mpc85xx/pci.c
@@ -120,7 +120,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pci_register_hose(hose);
-#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
+#if defined(CONFIG_TARGET_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS)
/*
* This is a SW workaround for an apparent HW problem
* in the PCI controller on the MPC85555/41 CDS boards.
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e732969e41..fcf5d92af5 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -130,9 +130,8 @@ void get_sys_info(sys_info_t *sys_info)
* it uses 6.
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
*/
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
- defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \
- defined(CONFIG_PPC_T2081)
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
+ defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
svr = get_svr();
switch (SVR_SOC_VER(svr)) {
case SVR_T4240:
@@ -202,11 +201,11 @@ void get_sys_info(sys_info_t *sys_info)
}
#endif
-#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
- defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
+ defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
-#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
#define FM1_CLK_SEL 0x00000007
#define FM1_CLK_SHIFT 0
#else
@@ -216,7 +215,7 @@ void get_sys_info(sys_info_t *sys_info)
#define FM1_CLK_SHIFT 26
#endif
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
-#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
#else
rcw_tmp = in_be32(&gur->rcwsr[7]);
@@ -456,7 +455,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
-#if defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_ARCH_T2080)
#define ESDHC_CLK_SEL 0x00000007
#define ESDHC_CLK_SHIFT 0
#define ESDHC_CLK_RCWSR 15
@@ -480,7 +479,7 @@ void get_sys_info(sys_info_t *sys_info)
case 4:
sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
break;
-#if defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_ARCH_T2080)
case 5:
sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
break;
@@ -596,7 +595,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#ifdef CONFIG_QE
-#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
sys_info->freq_qe = sys_info->freq_systembus;
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
@@ -625,8 +624,8 @@ void get_sys_info(sys_info_t *sys_info)
* for four times the clock divider values.
*/
lcrr_div *= 4;
-#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
- !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
+#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
+ !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560)
/*
* Yes, the entire PQ38 family use the same
* bit-representation for twice the clock divider values.
@@ -652,7 +651,7 @@ void get_sys_info(sys_info_t *sys_info)
int get_clocks (void)
{
sys_info_t sys_info;
-#ifdef CONFIG_MPC8544
+#ifdef CONFIG_ARCH_MPC8544
volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
#endif
#if defined(CONFIG_CPM2)
@@ -681,11 +680,11 @@ int get_clocks (void)
* for that SOC. This information is taken from application note
* AN2919.
*/
-#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
- defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
- defined(CONFIG_P1022)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
+ defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
+ defined(CONFIG_ARCH_P1022)
gd->arch.i2c1_clk = sys_info.freq_systembus;
-#elif defined(CONFIG_MPC8544)
+#elif defined(CONFIG_ARCH_MPC8544)
/*
* On the 8544, the I2C clock is the same as the SEC clock. This can be
* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
@@ -707,8 +706,7 @@ int get_clocks (void)
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
#else
-#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
- defined(CONFIG_P1014)
+#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
gd->arch.sdhc_clk = gd->bus_clk;
#else
gd->arch.sdhc_clk = gd->bus_clk / 2;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index c3e12349f7..932216c237 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -311,7 +311,7 @@ l2_disabled:
#endif
mtspr HID0,r0
-#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500)
+#if !defined(CONFIG_E500MC) && !defined(CONFIG_ARCH_QEMU_E500)
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mfspr r3,PVR
andi. r3,r3, 0xff
@@ -345,7 +345,7 @@ l2_disabled:
mtspr DBCR0,r0
#endif
-#ifdef CONFIG_MPC8569
+#ifdef CONFIG_ARCH_MPC8569
#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
@@ -376,7 +376,7 @@ l2_disabled:
tlbivax 0,r4
isync
-#endif /* CONFIG_MPC8569 */
+#endif /* CONFIG_ARCH_MPC8569 */
/*
* Search for the TLB that covers the code we're executing, and shrink it
diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
index c65f41d0f8..fc63fe3613 100644
--- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c
@@ -161,7 +161,7 @@ static const struct serdes_config serdes1_cfg_tbl[] = {
{}
};
-#ifndef CONFIG_PPC_T2081
+#ifndef CONFIG_ARCH_T2081
static const struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
@@ -181,7 +181,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
static const struct serdes_config *serdes_cfg_tbl[] = {
serdes1_cfg_tbl,
-#ifndef CONFIG_PPC_T2081
+#ifndef CONFIG_ARCH_T2081
serdes2_cfg_tbl,
#endif
};
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 7b43b282bb..3fc527d375 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -15,7 +15,7 @@ struct serdes_config {
u8 lanes[SRDS_MAX_LANES];
};
-#ifdef CONFIG_PPC_T4240
+#ifdef CONFIG_ARCH_T4240
static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
@@ -263,7 +263,7 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
};
-#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
+#elif defined(CONFIG_ARCH_T4160)
static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{1, {NONE, NONE, NONE, NONE,
diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
index fe1859d206..98fb702e86 100644
--- a/arch/powerpc/cpu/mpc86xx/Kconfig
+++ b/arch/powerpc/cpu/mpc86xx/Kconfig
@@ -10,18 +10,28 @@ choice
config TARGET_SBC8641D
bool "Support sbc8641d"
+ select ARCH_MPC8641
config TARGET_MPC8610HPCD
bool "Support MPC8610HPCD"
+ select ARCH_MPC8610
config TARGET_MPC8641HPCN
bool "Support MPC8641HPCN"
+ select ARCH_MPC8641
config TARGET_XPEDITE517X
bool "Support xpedite517x"
+ select ARCH_MPC8641
endchoice
+config ARCH_MPC8610
+ bool
+
+config ARCH_MPC8641
+ bool
+
source "board/freescale/mpc8610hpcd/Kconfig"
source "board/freescale/mpc8641hpcn/Kconfig"
source "board/sbc8641d/Kconfig"
diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile
index 0f790b0efc..88c23fc58c 100644
--- a/arch/powerpc/cpu/mpc86xx/Makefile
+++ b/arch/powerpc/cpu/mpc86xx/Makefile
@@ -19,6 +19,6 @@ obj-y += cpu_init.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-y += interrupts.o
obj-$(CONFIG_MP) += mp.o
-obj-$(CONFIG_MPC8610) += mpc8610_serdes.o
-obj-$(CONFIG_MPC8641) += mpc8641_serdes.o
+obj-$(CONFIG_ARCH_MPC8610) += mpc8610_serdes.o
+obj-$(CONFIG_ARCH_MPC8641) += mpc8641_serdes.o
obj-y += speed.o
diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c
index 30518544dd..7a9570c8ec 100644
--- a/arch/powerpc/cpu/mpc86xx/cpu.c
+++ b/arch/powerpc/cpu/mpc86xx/cpu.c
@@ -90,9 +90,9 @@ checkcpu(void)
puts("L2: ");
if (get_l2cr() & 0x80000000) {
-#if defined(CONFIG_MPC8610)
+#if defined(CONFIG_ARCH_MPC8610)
puts("256");
-#elif defined(CONFIG_MPC8641)
+#elif defined(CONFIG_ARCH_MPC8641)
puts("512");
#endif
puts(" KiB enabled\n");
@@ -139,7 +139,7 @@ get_tbclk(void)
void
watchdog_reset(void)
{
-#if defined(CONFIG_MPC8610)
+#if defined(CONFIG_ARCH_MPC8610)
/*
* This actually feed the hard enabled watchdog.
*/
diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c
index 5abe6f0bf2..05f23db457 100644
--- a/arch/powerpc/cpu/mpc86xx/speed.c
+++ b/arch/powerpc/cpu/mpc86xx/speed.c
@@ -115,7 +115,7 @@ int get_clocks(void)
* for that SOC. This information is taken from application note
* AN2919.
*/
-#ifdef CONFIG_MPC8610
+#ifdef CONFIG_ARCH_MPC8610
gd->arch.i2c1_clk = sys_info.freq_systembus;
#else
gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index bb23756d79..9d3a3b45c0 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -57,10 +57,6 @@
#endif
#endif
-#ifndef CONFIG_MAX_CPUS
-#define CONFIG_MAX_CPUS 1
-#endif
-
/*
* Provide a default boot page translation virtual address that lines up with
* Freescale's default e500 reset page.
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 6d845e859f..c92bc1ec40 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -35,8 +35,7 @@
#define CONFIG_SYS_NUM_TLBCAMS 16
#endif
-#if defined(CONFIG_MPC8536)
-#define CONFIG_MAX_CPUS 1
+#if defined(CONFIG_ARCH_MPC8536)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -44,21 +43,18 @@
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
-#elif defined(CONFIG_MPC8540)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_MPC8540)
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#elif defined(CONFIG_MPC8541)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_MPC8541)
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#elif defined(CONFIG_MPC8544)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_MPC8544)
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
@@ -66,8 +62,7 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A005125
-#elif defined(CONFIG_MPC8548)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_MPC8548)
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
@@ -85,21 +80,18 @@
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
-#elif defined(CONFIG_MPC8555)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_MPC8555)
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#elif defined(CONFIG_MPC8560)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_MPC8560)
#define CONFIG_SYS_FSL_NUM_LAWS 8
#define CONFIG_SYS_FSL_DDRC_GEN1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#elif defined(CONFIG_MPC8568)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_MPC8568)
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -113,8 +105,7 @@
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#elif defined(CONFIG_MPC8569)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_MPC8569)
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define QE_MURAM_SIZE 0x20000UL
@@ -129,8 +120,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
-#elif defined(CONFIG_MPC8572)
-#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_ARCH_MPC8572)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -140,8 +130,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
-#elif defined(CONFIG_P1010)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
@@ -169,8 +158,7 @@
#define CONFIG_ESDHC_HC_BLK_ADDR
/* P1011 is single core version of P1020 */
-#elif defined(CONFIG_P1011)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_P1011)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
@@ -183,75 +171,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
-/* P1012 is single core version of P1021 */
-#elif defined(CONFIG_P1012)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_TSECV2
-#define CONFIG_FSL_PCIE_DISABLE_ASPM
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define QE_MURAM_SIZE 0x6000UL
-#define MAX_QE_RISC 1
-#define QE_NUM_OF_SNUM 28
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-/* P1013 is single core version of P1022 */
-#elif defined(CONFIG_P1013)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_FSL_SATA_ERRATUM_A001
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_P1014)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_FSL_SDHC_V2_3
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
-#define CONFIG_TSECV2
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
-#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
-#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-
-/* P1017 is single core version of P1023 */
-#elif defined(CONFIG_P1017)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_FSL_SEC_COMPAT 4
-#define CONFIG_SYS_NUM_FMAN 1
-#define CONFIG_SYS_NUM_FM1_DTSEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_QMAN_NUM_PORTALS 3
-#define CONFIG_SYS_BMAN_NUM_PORTALS 3
-#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
-#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_P1020)
-#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_ARCH_P1020)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
@@ -266,8 +186,7 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
-#elif defined(CONFIG_P1021)
-#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_ARCH_P1021)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
@@ -283,8 +202,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#elif defined(CONFIG_P1022)
-#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_ARCH_P1022)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
@@ -298,8 +216,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_A004477
-#elif defined(CONFIG_P1023)
-#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_ARCH_P1023)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
@@ -317,8 +234,7 @@
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
/* P1024 is lower end variant of P1020 */
-#elif defined(CONFIG_P1024)
-#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_ARCH_P1024)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
@@ -332,8 +248,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1025 is lower end variant of P1021 */
-#elif defined(CONFIG_P1025)
-#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_ARCH_P1025)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
@@ -349,21 +264,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
-/* P2010 is single core version of P2020 */
-#elif defined(CONFIG_P2010)
-#define CONFIG_MAX_CPUS 1
-#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
-#define CONFIG_SYS_FSL_SEC_COMPAT 2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
-#define CONFIG_SYS_FSL_ERRATUM_A004508
-#define CONFIG_SYS_FSL_ERRATUM_A005125
-
-#elif defined(CONFIG_P2020)
-#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_ARCH_P2020)
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
@@ -380,10 +281,9 @@
#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
+#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
@@ -418,10 +318,9 @@
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
-#elif defined(CONFIG_PPC_P3041)
+#elif defined(CONFIG_ARCH_P3041)
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
@@ -458,10 +357,9 @@
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
-#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
+#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
@@ -509,11 +407,10 @@
#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
-#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
+#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
@@ -545,11 +442,10 @@
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
-#elif defined(CONFIG_PPC_P5040)
+#elif defined(CONFIG_ARCH_P5040)
#define CONFIG_SYS_PPC64
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
-#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
@@ -579,8 +475,7 @@
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#define CONFIG_SYS_FSL_ERRATUM_A005812
-#elif defined(CONFIG_BSC9131)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
@@ -598,8 +493,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004477
#define CONFIG_ESDHC_HC_BLK_ADDR
-#elif defined(CONFIG_BSC9132)
-#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
@@ -625,16 +519,14 @@
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_ESDHC_HC_BLK_ADDR
-#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
- defined(CONFIG_PPC_T4080)
+#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
#define CONFIG_E6500
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
-#ifdef CONFIG_PPC_T4240
-#define CONFIG_MAX_CPUS 12
+#ifdef CONFIG_ARCH_T4240
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
@@ -648,12 +540,8 @@
#define CONFIG_SYS_NUM_FM2_DTSEC 8
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
-#if defined(CONFIG_PPC_T4160)
-#define CONFIG_MAX_CPUS 8
+#if defined(CONFIG_ARCH_T4160)
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
-#elif defined(CONFIG_PPC_T4080)
-#define CONFIG_MAX_CPUS 4
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 }
#endif
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
@@ -691,7 +579,7 @@
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
-#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
+#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
#define CONFIG_E6500
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
@@ -733,9 +621,8 @@
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
-#ifdef CONFIG_PPC_B4860
+#ifdef CONFIG_ARCH_B4860
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
-#define CONFIG_MAX_CPUS 4
#define CONFIG_MAX_DSP_CPUS 12
#define CONFIG_NUM_DSP_CPUS 6
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
@@ -749,7 +636,6 @@
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_SRIO_LIODN
#else
-#define CONFIG_MAX_CPUS 2
#define CONFIG_MAX_DSP_CPUS 2
#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
@@ -759,7 +645,7 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#endif
-#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_E5500
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
@@ -769,11 +655,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#ifdef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDRC_GEN4
#endif
-#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
-#define CONFIG_MAX_CPUS 4
-#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
-#define CONFIG_MAX_CPUS 2
-#endif
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_NUM_LAWS 16
@@ -810,7 +691,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_ERRATUM_A008378
#define CONFIG_SYS_FSL_ERRATUM_A009663
-#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\
defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_E5500
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
@@ -821,11 +702,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#ifdef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDRC_GEN4
#endif
-#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
-#define CONFIG_MAX_CPUS 2
-#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
-#define CONFIG_MAX_CPUS 1
-#endif
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_NUM_LAWS 16
@@ -859,7 +735,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_ERRATUM_A008378
#define CONFIG_SYS_FSL_ERRATUM_A009663
-#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define CONFIG_E6500
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
@@ -867,14 +743,13 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_QMAN_V3
-#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_PCI_VER_3_X
-#if defined(CONFIG_PPC_T2080)
+#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 4
#define CONFIG_SYS_FSL_SRDS_2
@@ -882,7 +757,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#elif defined(CONFIG_PPC_T2081)
+#elif defined(CONFIG_ARCH_T2081)
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#endif
@@ -914,8 +789,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_SFP_VER_3_0
-#elif defined(CONFIG_PPC_C29X)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
@@ -930,8 +804,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
-#elif defined(CONFIG_QEMU_E500)
-#define CONFIG_MAX_CPUS 1
+#elif defined(CONFIG_ARCH_QEMU_E500)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
#else
@@ -955,7 +828,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_DDRC_GEN3
#endif
-#if !defined(CONFIG_PPC_C29X)
+#if !defined(CONFIG_ARCH_C29X)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#endif
diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
index 4f9b2252be..c41dc99681 100644
--- a/arch/powerpc/include/asm/config_mpc86xx.h
+++ b/arch/powerpc/include/asm/config_mpc86xx.h
@@ -11,12 +11,10 @@
/* SoC specific defines for Freescale MPC86xx processors */
-#if defined(CONFIG_MPC8610)
-#define CONFIG_MAX_CPUS 1
+#if defined(CONFIG_ARCH_MPC8610)
#define CONFIG_SYS_FSL_NUM_LAWS 10
-#elif defined(CONFIG_MPC8641)
-#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_ARCH_MPC8641)
#define CONFIG_SYS_FSL_NUM_LAWS 10
#else
diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h
index b137a71450..b46e20e5ce 100644
--- a/arch/powerpc/include/asm/cpm_85xx.h
+++ b/arch/powerpc/include/asm/cpm_85xx.h
@@ -77,7 +77,7 @@
*/
#define CPM_DATAONLY_BASE ((uint)128)
#define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
-#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
#else /* MPC8540, MPC8560 */
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 2a759c85b8..b348cc1f20 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -79,13 +79,13 @@ enum law_trgt_if {
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
LAW_TRGT_IF_PCI_2 = 0x01,
-#ifndef CONFIG_MPC8641
+#ifndef CONFIG_ARCH_MPC8641
LAW_TRGT_IF_PCIE_1 = 0x02,
#endif
-#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
LAW_TRGT_IF_OCN_DSP = 0x03,
#else
-#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
+#if !defined(CONFIG_ARCH_MPC8572) && !defined(CONFIG_ARCH_P2020)
LAW_TRGT_IF_PCIE_3 = 0x03,
#endif
#endif
@@ -95,7 +95,7 @@ enum law_trgt_if {
LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
-#if defined(CONFIG_BSC9132)
+#if defined(CONFIG_ARCH_BSC9132)
LAW_TRGT_IF_CLASS_DSP = 0x0d,
#else
LAW_TRGT_IF_RIO_2 = 0x0d,
@@ -117,11 +117,11 @@ enum law_trgt_if {
#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
-#ifdef CONFIG_MPC8641
+#ifdef CONFIG_ARCH_MPC8641
#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
#endif
-#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
+#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
#endif
#endif /* CONFIG_FSL_CORENET */
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 402edd7a2a..b8270c5ffd 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -325,9 +325,9 @@ void lbc_sdram_init(void);
*/
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
-#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
- defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
- defined(CONFIG_MPC8560)
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
+ defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \
+ defined(CONFIG_ARCH_MPC8560)
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index f9154d3b40..808adae82d 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -16,25 +16,30 @@
#if defined(CONFIG_FSL_CORENET)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
-#elif defined(CONFIG_BSC9132QDS)
+#elif defined(CONFIG_TARGET_BSC9132QDS)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
-#elif defined(CONFIG_C29XPCIE)
+#elif defined(CONFIG_TARGET_C29XPCIE)
#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
#else
#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
#endif
#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
-#if defined(CONFIG_B4860QDS) || \
- defined(CONFIG_T4240QDS) || \
+#if defined(CONFIG_TARGET_B4860QDS) || \
+ defined(CONFIG_TARGET_B4420QDS) || \
+ defined(CONFIG_TARGET_T4160QDS) || \
+ defined(CONFIG_TARGET_T4240QDS) || \
defined(CONFIG_T2080QDS) || \
defined(CONFIG_T2080RDB) || \
defined(CONFIG_T1040QDS) || \
defined(CONFIG_T104xD4QDS) || \
- defined(CONFIG_T104xRDB) || \
- defined(CONFIG_T104xD4RDB) || \
- defined(CONFIG_PPC_T1023) || \
- defined(CONFIG_PPC_T1024)
+ defined(CONFIG_TARGET_T1040RDB) || \
+ defined(CONFIG_TARGET_T1040D4RDB) || \
+ defined(CONFIG_TARGET_T1042RDB) || \
+ defined(CONFIG_TARGET_T1042D4RDB) || \
+ defined(CONFIG_TARGET_T1042RDB_PI) || \
+ defined(CONFIG_ARCH_T1023) || \
+ defined(CONFIG_ARCH_T1024)
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_CPC_REINIT_F
#endif
@@ -54,15 +59,15 @@
#endif
#endif
-#if defined(CONFIG_C29XPCIE)
+#if defined(CONFIG_TARGET_C29XPCIE)
#define CONFIG_KEY_REVOCATION
#endif
-#if defined(CONFIG_PPC_P3041) || \
- defined(CONFIG_PPC_P4080) || \
- defined(CONFIG_PPC_P5020) || \
- defined(CONFIG_PPC_P5040) || \
- defined(CONFIG_PPC_P2041)
+#if defined(CONFIG_ARCH_P3041) || \
+ defined(CONFIG_ARCH_P4080) || \
+ defined(CONFIG_ARCH_P5020) || \
+ defined(CONFIG_ARCH_P5040) || \
+ defined(CONFIG_ARCH_P2041)
#define CONFIG_FSL_TRUST_ARCH_v1
#endif
@@ -134,13 +139,13 @@
/* The bootscript header address is different for B4860 because the NOR
* mapping is different on B4 due to reduced NOR size.
*/
-#if defined(CONFIG_B4860QDS)
+#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
#elif defined(CONFIG_FSL_CORENET)
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
-#elif defined(CONFIG_BSC9132QDS)
+#elif defined(CONFIG_TARGET_BSC9132QDS)
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
-#elif defined(CONFIG_C29XPCIE)
+#elif defined(CONFIG_TARGET_C29XPCIE)
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
#else
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 76ea00b04f..786e4f6765 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -124,10 +124,10 @@ typedef struct ccsr_i2c {
u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
} ccsr_i2c_t;
-#if defined(CONFIG_MPC8540) \
- || defined(CONFIG_MPC8541) \
- || defined(CONFIG_MPC8548) \
- || defined(CONFIG_MPC8555)
+#if defined(CONFIG_ARCH_MPC8540) || \
+ defined(CONFIG_ARCH_MPC8541) || \
+ defined(CONFIG_ARCH_MPC8548) || \
+ defined(CONFIG_ARCH_MPC8555)
/* DUART Registers */
typedef struct ccsr_duart {
u8 res1[1280];
@@ -1759,8 +1759,7 @@ typedef struct ccsr_gur {
/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
- defined(CONFIG_PPC_T4080)
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
@@ -1770,13 +1769,13 @@ typedef struct ccsr_gur {
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
-#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
+#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
-#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
@@ -1797,7 +1796,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
-#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) || \
defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
@@ -1812,7 +1811,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
-#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
@@ -1848,7 +1847,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
@@ -1856,8 +1855,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
#endif
-#if defined(CONFIG_PPC_P2041) \
- || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
+#if defined(CONFIG_ARCH_P2041) || \
+ defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
@@ -1866,7 +1865,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
#endif
-#if defined(CONFIG_PPC_P5040)
+#if defined(CONFIG_ARCH_P5040)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
@@ -1875,8 +1874,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
#endif
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
- defined(CONFIG_PPC_T4080)
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
@@ -1885,7 +1883,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
#endif
-#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
@@ -2120,16 +2118,16 @@ typedef struct ccsr_rcpm {
#else
typedef struct ccsr_gur {
u32 porpllsr; /* POR PLL ratio status */
-#ifdef CONFIG_MPC8536
+#ifdef CONFIG_ARCH_MPC8536
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
-#elif defined(CONFIG_PPC_C29X)
+#elif defined(CONFIG_ARCH_C29X)
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
& MPC85xx_PORDEVSR2_DDR_SPD_0) \
>> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
#else
-#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
#else
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
@@ -2150,7 +2148,7 @@ typedef struct ccsr_gur {
#define PORBMSR_ROMLOC_NOR 0xf
u32 porimpscr; /* POR I/O impedance status & control */
u32 pordevsr; /* POR I/O device status regsiter */
-#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#if defined(CONFIG_ARCH_P1023)
#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
#define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
@@ -2162,26 +2160,26 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
#define MPC85xx_PORDEVSR_PCI1 0x00800000
-#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#if defined(CONFIG_ARCH_P1022)
#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
-#elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#elif defined(CONFIG_ARCH_P1023)
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
#else
-#if defined(CONFIG_P1010)
+#if defined(CONFIG_ARCH_P1010)
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
-#elif defined(CONFIG_BSC9132)
+#elif defined(CONFIG_ARCH_BSC9132)
#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
-#elif defined(CONFIG_PPC_C29X)
+#elif defined(CONFIG_ARCH_C29X)
#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
#else
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
-#endif /* if defined(CONFIG_P1010) */
+#endif /* if defined(CONFIG_ARCH_P1010) */
#endif
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
@@ -2193,7 +2191,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
u32 pordbgmsr; /* POR debug mode status */
u32 pordevsr2; /* POR I/O device status 2 */
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
#endif
@@ -2203,14 +2201,14 @@ typedef struct ccsr_gur {
u8 res1[8];
u32 gpporcr; /* General-purpose POR configuration */
u8 res2[12];
-#if defined(CONFIG_MPC8536)
+#if defined(CONFIG_ARCH_MPC8536)
u32 gencfgr; /* General Configuration Register */
#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
#else
u32 gpiocr; /* GPIO control */
#endif
u8 res3[12];
-#if defined(CONFIG_MPC8569)
+#if defined(CONFIG_ARCH_MPC8569)
u32 plppar1; /* Platform port pin assignment 1 */
u32 plppar2; /* Platform port pin assignment 2 */
u32 plpdir1; /* Platform port pin direction 1 */
@@ -2222,7 +2220,7 @@ typedef struct ccsr_gur {
u32 gpindr; /* General-purpose input data */
u8 res5[12];
u32 pmuxcr; /* Alt. function signal multiplex control */
-#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
+#if defined(CONFIG_ARCH_P1010)
#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
@@ -2268,7 +2266,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
#define MPC85xx_PMUXCR_CAN2_RES 0x00000003
#endif
-#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#if defined(CONFIG_ARCH_P1023)
#define MPC85xx_PMUXCR_TSEC1_1 0x10000000
#else
#define MPC85xx_PMUXCR_SD_DATA 0x80000000
@@ -2290,13 +2288,13 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_QE11 0x00000010
#define MPC85xx_PMUXCR_QE12 0x00000008
#endif
-#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#if defined(CONFIG_ARCH_P1022)
#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
#define MPC85xx_PMUXCR_TDM 0x00014800
#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
#define MPC85xx_PMUXCR_SPI 0x00000000
#endif
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
@@ -2340,17 +2338,17 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
#endif
-#ifdef CONFIG_BSC9132
+#ifdef CONFIG_ARCH_BSC9132
#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
#endif
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
#define MPC85xx_PMUXCR_SPI 0x00000000
#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
#endif
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
-#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
+#if defined(CONFIG_ARCH_P1010)
#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
#define MPC85xx_PMUXCR2_UART_TDM 0x80000000
#define MPC85xx_PMUXCR2_UART_RES 0xC0000000
@@ -2375,12 +2373,12 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
#endif
-#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#if defined(CONFIG_ARCH_P1022)
#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
#define MPC85xx_PMUXCR2_USB 0x00150000
#endif
-#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
@@ -2425,7 +2423,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
#endif
u32 pmuxcr3;
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_ARCH_BSC9131)
#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
@@ -2441,7 +2439,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
#endif
-#ifdef CONFIG_BSC9132
+#ifdef CONFIG_ARCH_BSC9132
#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
@@ -2484,11 +2482,11 @@ typedef struct ccsr_gur {
u32 svr; /* System version */
u8 res10[8];
u32 rstcr; /* Reset control */
-#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
+#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569)
u8 res11a[76];
par_io_t qe_par_io[7];
u8 res11b[1600];
-#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
u8 res11a[12];
u32 iovselsr;
u8 res11b[60];
@@ -2504,7 +2502,7 @@ typedef struct ccsr_gur {
u32 ddrdllcr; /* DDR DLL control */
u8 res14[12];
u32 lbcdllcr; /* LBC DLL control */
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_ARCH_BSC9131)
u8 res15[12];
u32 halt_req_mask;
#define HALTED_TO_HALT_REQ_MASK_0 0x80000000
@@ -2883,8 +2881,8 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
-#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
- && !defined(CONFIG_PPC_B4420)
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
+ !defined(CONFIG_ARCH_B4420)
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
@@ -2940,7 +2938,7 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
-#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
+#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
#else
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
@@ -2964,7 +2962,7 @@ struct ccsr_pman {
#endif
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
-#if defined(CONFIG_PPC_C29X)
+#if defined(CONFIG_ARCH_C29X)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
#else
@@ -2988,7 +2986,7 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
-#if defined(CONFIG_BSC9132)
+#if defined(CONFIG_ARCH_BSC9132)
#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
(CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
index b078569c45..1fbc63a5ce 100644
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -1195,7 +1195,7 @@ extern immap_t *immr;
#define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000
-#ifdef CONFIG_MPC8610
+#ifdef CONFIG_ARCH_MPC8610
#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000
#else
#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index fdfca9086f..fbf72bb7c6 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1048,7 +1048,7 @@
#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
-#ifdef CONFIG_MPC8536
+#ifdef CONFIG_ARCH_MPC8536
#define SVR_MAJ(svr) (((svr) >> 4) & 0x7) /* Major revision field*/
#else
#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/