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-rw-r--r--arch/arm/dts/rk3288-popmetal.dtsi23
-rw-r--r--arch/arm/dts/rk3399.dtsi1
-rw-r--r--arch/arm/include/asm/arch-rockchip/qos_rk3288.h20
-rw-r--r--arch/arm/mach-rockchip/rk3288-board.c20
-rw-r--r--arch/arm/mach-rockchip/rk3288/Kconfig2
-rw-r--r--arch/arm/mach-rockchip/rk3399/clk_rk3399.c6
6 files changed, 68 insertions, 4 deletions
diff --git a/arch/arm/dts/rk3288-popmetal.dtsi b/arch/arm/dts/rk3288-popmetal.dtsi
index f3bd4685bd..e5be4cb471 100644
--- a/arch/arm/dts/rk3288-popmetal.dtsi
+++ b/arch/arm/dts/rk3288-popmetal.dtsi
@@ -145,6 +145,18 @@
regulator-always-on;
vin-supply = <&vcc_io>;
};
+
+ vcc5v0_host: usb-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ regulator-name = "vcc5v0_host";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
};
&cpu0 {
@@ -471,6 +483,12 @@
rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+ usb_host {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&tsadc {
@@ -515,6 +533,11 @@
status = "okay";
};
+&usb_host1 {
+ vbus-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
&usbphy {
status = "okay";
};
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 179860c900..22277ff0ad 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -188,6 +188,7 @@
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru SCLK_EMMC>;
assigned-clock-rates = <200000000>;
+ max-frequency = <200000000>;
clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
clock-names = "clk_xin", "clk_ahb";
phys = <&emmc_phy>;
diff --git a/arch/arm/include/asm/arch-rockchip/qos_rk3288.h b/arch/arm/include/asm/arch-rockchip/qos_rk3288.h
new file mode 100644
index 0000000000..b3094fcfbe
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/qos_rk3288.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2016 Rockchip Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_QOS_RK3288_H
+#define _ASM_ARCH_QOS_RK3288_H
+
+#define PRIORITY_HIGH_SHIFT 2
+#define PRIORITY_LOW_SHIFT 0
+
+#define CPU_AXI_QOS_PRIORITY 0x08
+
+#define VIO0_VOP_QOS 0xffad0400
+#define VIO1_VOP_QOS 0xffad0000
+#define VIO1_ISP_R_QOS 0xffad0900
+#define VIO1_ISP_W0_QOS 0xffad0100
+#define VIO1_ISP_W1_QOS 0xffad0180
+
+#endif
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
index bca6075c2c..8bf45f7fc7 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -13,6 +13,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/periph.h>
#include <asm/arch/pmu_rk3288.h>
+#include <asm/arch/qos_rk3288.h>
#include <asm/arch/boot_mode.h>
#include <asm/gpio.h>
#include <dm/pinctrl.h>
@@ -51,9 +52,28 @@ __weak int rk_board_late_init(void)
return 0;
}
+int rk3288_qos_init(void)
+{
+ int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
+ /* set vop qos to higher priority */
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
+
+ if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+ "rockchip,rk3288-miniarm"))
+ {
+ /* set isp qos to higher priority */
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
+ writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
+ }
+ return 0;
+}
+
int board_late_init(void)
{
setup_boot_mode();
+ rk3288_qos_init();
return rk_board_late_init();
}
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index 223ae41dd4..54545f378c 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -61,7 +61,7 @@ config TARGET_CHROMEBIT_MICKEY
config TARGET_CHROMEBOOK_MINNIE
bool "Google/Rockchip Veyron-Minnie Chromebook"
help
- Jerry is a RK3288-based convertible clamshell device with 2 USB 3.0
+ Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS
EC (Cortex-M3) to provide access to the keyboard and battery
diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
index 7663591154..ce706a61e2 100644
--- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c
@@ -11,10 +11,10 @@
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3399.h>
-int rockchip_get_clk(struct udevice **devp)
+static int rockchip_get_cruclk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
- DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp);
+ DM_GET_DRIVER(clk_rk3399), devp);
}
void *rockchip_get_cru(void)
@@ -23,7 +23,7 @@ void *rockchip_get_cru(void)
struct udevice *dev;
int ret;
- ret = rockchip_get_clk(&dev);
+ ret = rockchip_get_cruclk(&dev);
if (ret)
return ERR_PTR(ret);