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-rw-r--r--arch/arm/include/asm/arch-tegra124/mc.h2
-rw-r--r--arch/arm/mach-tegra/ap.c40
2 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h
index 55577327d9..37998a4d60 100644
--- a/arch/arm/include/asm/arch-tegra124/mc.h
+++ b/arch/arm/include/asm/arch-tegra124/mc.h
@@ -74,6 +74,8 @@ struct mc_ctlr {
u32 mc_video_protect_reg_ctrl; /* offset 0x650 */
};
+#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
+
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0)
#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0)
diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c
index 869a2ed6bc..0b94e8aaf9 100644
--- a/arch/arm/mach-tegra/ap.c
+++ b/arch/arm/mach-tegra/ap.c
@@ -169,6 +169,43 @@ void protect_secure_section(void)
}
#endif
+#if defined(CONFIG_ARMV7_NONSEC)
+static void smmu_flush(struct mc_ctlr *mc)
+{
+ (void)readl(&mc->mc_smmu_config);
+}
+
+static void smmu_enable(void)
+{
+ struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
+ u32 value;
+
+ /*
+ * Enable translation for all clients since access to this register
+ * is restricted to TrustZone-secured requestors. The kernel will use
+ * the per-SWGROUP enable bits to enable or disable translations.
+ */
+ writel(0xffffffff, &mc->mc_smmu_translation_enable_0);
+ writel(0xffffffff, &mc->mc_smmu_translation_enable_1);
+ writel(0xffffffff, &mc->mc_smmu_translation_enable_2);
+ writel(0xffffffff, &mc->mc_smmu_translation_enable_3);
+
+ /*
+ * Enable SMMU globally since access to this register is restricted
+ * to TrustZone-secured requestors.
+ */
+ value = readl(&mc->mc_smmu_config);
+ value |= TEGRA_MC_SMMU_CONFIG_ENABLE;
+ writel(value, &mc->mc_smmu_config);
+
+ smmu_flush(mc);
+}
+#else
+static void smmu_enable(void)
+{
+}
+#endif
+
void s_init(void)
{
/* Init PMC scratch memory */
@@ -179,6 +216,9 @@ void s_init(void)
/* init the cache */
config_cache();
+ /* enable SMMU */
+ smmu_enable();
+
/* init vpr */
config_vpr();
}