diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Makefile | 4 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 4 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_secure_boot.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 2 |
6 files changed, 11 insertions, 7 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 808144edf2..9aef492990 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -56,6 +56,7 @@ config TARGET_P5020DS config TARGET_P5040DS bool "Support P5040DS" select PHYS_64BIT + select ARCH_P5040 config TARGET_MPC8536DS bool "Support MPC8536DS" @@ -328,6 +329,9 @@ config ARCH_P4080 config ARCH_P5020 bool +config ARCH_P5040 + bool + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index edd365aba1..7c1dbb9dfc 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -43,7 +43,7 @@ obj-$(CONFIG_ARCH_P2041) += p2041_ids.o obj-$(CONFIG_ARCH_P3041) += p3041_ids.o obj-$(CONFIG_ARCH_P4080) += p4080_ids.o obj-$(CONFIG_ARCH_P5020) += p5020_ids.o -obj-$(CONFIG_PPC_P5040) += p5040_ids.o +obj-$(CONFIG_ARCH_P5040) += p5040_ids.o obj-$(CONFIG_PPC_T4240) += t4240_ids.o obj-$(CONFIG_PPC_T4160) += t4240_ids.o obj-$(CONFIG_PPC_T4080) += t4240_ids.o @@ -85,7 +85,7 @@ obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o -obj-$(CONFIG_PPC_P5040) += p5040_serdes.o +obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o obj-$(CONFIG_PPC_T4240) += t4240_serdes.o obj-$(CONFIG_PPC_T4160) += t4240_serdes.o obj-$(CONFIG_PPC_T4080) += t4240_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 20d039f338..45b6bdc4c6 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -491,7 +491,7 @@ void fsl_serdes_init(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int cfg; serdes_corenet_t *srds_regs; -#ifdef CONFIG_PPC_P5040 +#ifdef CONFIG_ARCH_P5040 serdes_corenet_t *srds2_regs; #endif int lane, bank, idx; @@ -577,7 +577,7 @@ void fsl_serdes_init(void) } } -#ifdef CONFIG_PPC_P5040 +#ifdef CONFIG_ARCH_P5040 /* * Lanes on bank 4 on P5040 are commented-out, but for some SERDES * protocols, these lanes are routed to SATA. We use serdes_prtcl_map diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 496b84520e..23ee8f9a0d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -465,7 +465,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 -#elif defined(CONFIG_PPC_P5040) +#elif defined(CONFIG_ARCH_P5040) #define CONFIG_SYS_PPC64 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 47c3d980a5..7de554ac30 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -61,7 +61,7 @@ #if defined(CONFIG_ARCH_P3041) || \ defined(CONFIG_ARCH_P4080) || \ defined(CONFIG_ARCH_P5020) || \ - defined(CONFIG_PPC_P5040) || \ + defined(CONFIG_ARCH_P5040) || \ defined(CONFIG_ARCH_P2041) #define CONFIG_FSL_TRUST_ARCH_v1 #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 759671ab6a..b8b5379613 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1866,7 +1866,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_P5040) +#if defined(CONFIG_ARCH_P5040) #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000 |