diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/include/asm/arch-rockchip/boot_mode.h | 4 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/Kconfig | 1 | ||||
-rw-r--r-- | arch/arm/mach-rockchip/bootrom.c | 47 |
3 files changed, 50 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/boot_mode.h b/arch/arm/include/asm/arch-rockchip/boot_mode.h index 163b2e7b04..6b2a610cf4 100644 --- a/arch/arm/include/asm/arch-rockchip/boot_mode.h +++ b/arch/arm/include/asm/arch-rockchip/boot_mode.h @@ -15,7 +15,11 @@ #define BOOT_CHARGING (REBOOT_FLAG + 11) /* enter usb mass storage mode */ #define BOOT_UMS (REBOOT_FLAG + 12) +/* enter bootrom download mode */ +#define BOOT_BROM_DOWNLOAD 0xEF08A53C +#ifndef __ASSEMBLY__ int setup_boot_mode(void); +#endif #endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6144057ad4..a26736a5ac 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -118,6 +118,7 @@ config ROCKCHIP_RK3399 select SPL_DRIVERS_MISC_SUPPORT select DEBUG_UART_BOARD_INIT select BOARD_LATE_INIT + select ROCKCHIP_BROM_HELPER help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c index e369fdc25a..bef2a90d1f 100644 --- a/arch/arm/mach-rockchip/bootrom.c +++ b/arch/arm/mach-rockchip/bootrom.c @@ -6,6 +6,8 @@ #include <common.h> #include <asm/arch/bootrom.h> +#include <asm/arch/boot_mode.h> +#include <asm/io.h> #include <asm/setjmp.h> #include <asm/system.h> @@ -15,12 +17,45 @@ */ static jmp_buf brom_ctx __section(".data"); +static void _back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd) +{ + longjmp(brom_ctx, brom_cmd); +} + void back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd) { #if CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) puts("Returning to boot ROM...\n"); #endif - longjmp(brom_ctx, brom_cmd); + _back_to_bootrom(brom_cmd); +} + +/* + * we back to bootrom download mode if get a + * BOOT_BROM_DOWNLOAD flag in boot mode register + * + * note: the boot mode register is configured by + * application(next stage bootloader, kernel, etc), + * and the bootrom never check this register, so we need + * to check it and back to bootrom at very early bootstage(before + * some basic configurations(such as interrupts) been + * changed by TPL/SPL, as the bootrom download operation + * relys on many default settings(such as interrupts) by + * it's self. + */ +static bool check_back_to_brom_dnl_flag(void) +{ + u32 boot_mode; + + if (CONFIG_ROCKCHIP_BOOT_MODE_REG) { + boot_mode = readl(CONFIG_ROCKCHIP_BOOT_MODE_REG); + if (boot_mode == BOOT_BROM_DOWNLOAD) { + writel(0, CONFIG_ROCKCHIP_BOOT_MODE_REG); + return true; + } + } + + return false; } /* @@ -34,6 +69,8 @@ int save_boot_params(void) switch (ret) { case 0: + if (check_back_to_brom_dnl_flag()) + _back_to_bootrom(BROM_BOOT_ENTER_DNL); /* * This is the initial pass through this function * (i.e. saving the context), setjmp just setup up the @@ -54,7 +91,13 @@ int save_boot_params(void) */ ret = 0; break; - + case BROM_BOOT_ENTER_DNL: + /* + * A non-zero return value will instruct the BROM enter + * download mode. + */ + ret = 1; + break; default: #if CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) puts("FATAL: unexpected command to back_to_bootrom()\n"); |