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-rw-r--r--arch/arm/include/asm/arch-armada8k/cache_llc.h21
-rw-r--r--arch/arm/mach-mvebu/armada8k/Makefile1
-rw-r--r--arch/arm/mach-mvebu/armada8k/cache_llc.S39
3 files changed, 61 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-armada8k/cache_llc.h b/arch/arm/include/asm/arch-armada8k/cache_llc.h
new file mode 100644
index 0000000000..8f97e6d776
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada8k/cache_llc.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#ifndef _CACHE_LLC_H_
+#define _CACHE_LLC_H_
+
+/* Armada-7K/8K last level cache */
+
+#define MVEBU_A8K_REGS_BASE_MSB 0xf000
+#define LLC_BASE_ADDR 0x8000
+#define LLC_CACHE_SYNC 0x700
+#define LLC_CACHE_SYNC_COMPLETE 0x730
+#define LLC_FLUSH_BY_WAY 0x7fc
+#define LLC_WAY_MASK 0xffffffff
+#define LLC_CACHE_SYNC_MASK 0x1
+
+#endif /* _CACHE_LLC_H_ */
diff --git a/arch/arm/mach-mvebu/armada8k/Makefile b/arch/arm/mach-mvebu/armada8k/Makefile
index 84c69d90e7..0facf14942 100644
--- a/arch/arm/mach-mvebu/armada8k/Makefile
+++ b/arch/arm/mach-mvebu/armada8k/Makefile
@@ -5,3 +5,4 @@
#
obj-y = cpu.o
+obj-y += cache_llc.o
diff --git a/arch/arm/mach-mvebu/armada8k/cache_llc.S b/arch/arm/mach-mvebu/armada8k/cache_llc.S
new file mode 100644
index 0000000000..71aecb2dde
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada8k/cache_llc.S
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ * https://spdx.org/licenses
+ */
+
+#include <asm/arch-armada8k/cache_llc.h>
+#include <linux/linkage.h>
+
+/*
+ * int __asm_flush_l3_dcache
+ *
+ * flush Armada-8K last level cache.
+ *
+ */
+ENTRY(__asm_flush_l3_dcache)
+ /* flush cache */
+ mov x0, #LLC_BASE_ADDR
+ add x0, x0, #LLC_FLUSH_BY_WAY
+ movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
+ mov w1, #LLC_WAY_MASK
+ str w1, [x0]
+ /* sync cache */
+ mov x0, #LLC_BASE_ADDR
+ add x0, x0, #LLC_CACHE_SYNC
+ movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
+ str wzr, [x0]
+ /* check that cache sync completed */
+ mov x0, #LLC_BASE_ADDR
+ add x0, x0, #LLC_CACHE_SYNC_COMPLETE
+ movk x0, #MVEBU_A8K_REGS_BASE_MSB, lsl #16
+1: ldr w1, [x0]
+ and w1, w1, #LLC_CACHE_SYNC_MASK
+ cbnz w1, 1b
+ /* return success */
+ mov x0, #0
+ ret
+ENDPROC(__asm_flush_l3_dcache)