diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/Kconfig | 1 | ||||
-rw-r--r-- | arch/arc/Kconfig | 59 | ||||
-rw-r--r-- | arch/arc/config.mk | 12 | ||||
-rw-r--r-- | arch/arc/cpu/arcv2/Makefile | 7 | ||||
-rw-r--r-- | arch/arc/cpu/arcv2/start.S | 254 | ||||
-rw-r--r-- | arch/arc/include/asm/cache.h | 6 | ||||
-rw-r--r-- | arch/arm/Kconfig | 217 | ||||
-rw-r--r-- | arch/arm/Makefile | 24 | ||||
-rw-r--r-- | arch/arm/cpu/Makefile | 7 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/bcm2835/Kconfig | 12 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/bcm2835/Makefile | 12 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/start.S | 22 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/tnetv107x/Makefile | 6 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/tnetv107x/aemif.c | 78 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/tnetv107x/clock.c | 432 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/tnetv107x/init.c | 22 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S | 10 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/tnetv107x/mux.c | 319 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/tnetv107x/timer.c | 93 | ||||
-rw-r--r-- | arch/arm/cpu/arm720t/Makefile | 6 | ||||
-rw-r--r-- | arch/arm/cpu/arm720t/tegra-common/Makefile | 11 | ||||
-rw-r--r-- | arch/arm/cpu/arm720t/tegra114/Makefile | 21 | ||||
-rw-r--r-- | arch/arm/cpu/arm720t/tegra124/Makefile | 8 | ||||
-rw-r--r-- | arch/arm/cpu/arm720t/tegra20/Makefile | 10 | ||||
-rw-r--r-- | arch/arm/cpu/arm720t/tegra30/Makefile | 20 | ||||
-rw-r--r-- | arch/arm/cpu/arm920t/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/cpu/arm920t/a320/Makefile | 9 | ||||
-rw-r--r-- | arch/arm/cpu/arm920t/a320/reset.S | 10 | ||||
-rw-r--r-- | arch/arm/cpu/arm920t/a320/timer.c | 118 | ||||
-rw-r--r-- | arch/arm/cpu/arm920t/ks8695/Makefile | 9 | ||||
-rw-r--r-- | arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 189 | ||||
-rw-r--r-- | arch/arm/cpu/arm920t/ks8695/timer.c | 77 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/Makefile | 8 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/at91/config.mk | 2 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mb86r0x/Makefile | 8 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mb86r0x/clock.c | 27 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mb86r0x/reset.c | 24 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/mb86r0x/timer.c | 115 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/pantheon/Makefile | 9 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/pantheon/cpu.c | 85 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/pantheon/dram.c | 117 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/pantheon/timer.c | 201 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/Makefile | 6 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 3 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/at91/config.mk | 8 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/bcm2835/Makefile | 13 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/exynos/Kconfig | 35 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/exynos/clock.c | 621 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/exynos/power.c | 28 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/exynos/spl_boot.c | 1 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/ls102xa/cpu.c | 231 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap-common/emif-common.c | 4 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap3/Kconfig | 15 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap3/lowlevel_init.S | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/omap5/sdram.c | 83 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/rmobile/Kconfig | 6 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S | 12 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/s5pc1xx/Kconfig | 4 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/start.S | 7 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/Makefile | 5 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/board.c | 46 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/config.mk | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_helpers.c | 37 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/fel_utils.S | 42 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 82 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/tegra-common/Kconfig | 28 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/tegra-common/Makefile | 10 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/tegra20/Makefile | 11 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/uniphier/Kconfig | 8 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/cache.S | 6 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/cache_v8.c | 18 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 62 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 28 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 132 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/mp.c | 8 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/mp.h | 1 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/speed.c | 16 | ||||
-rw-r--r-- | arch/arm/dts/exynos4412-odroid.dts | 5 | ||||
-rw-r--r-- | arch/arm/dts/exynos5422-odroidxu3.dts | 5 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-a320/a320.h | 22 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-am33xx/cpu.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-bcm2835/gpio.h | 5 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-bcm2835/mbox.h | 10 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-bcm2835/sdhci.h | 18 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-bcm2835/timer.h | 18 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-bcm2835/wdog.h | 18 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-exynos/clk.h | 4 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/config.h | 38 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-ks8695/platform.h | 294 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-lpc32xx/config.h | 4 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-ls102xa/config.h | 15 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 40 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h | 57 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mb86r0x/hardware.h | 15 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mb86r0x/mb86r0x.h | 599 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-pantheon/config.h | 53 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-pantheon/cpu.h | 77 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-pantheon/gpio.h | 0 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-pantheon/mfp.h | 39 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-pantheon/pantheon.h | 38 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 9 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram.h | 28 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/sys_proto.h | 10 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-tnetv107x/clock.h | 53 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-tnetv107x/hardware.h | 160 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-tnetv107x/mux.h | 291 | ||||
-rw-r--r-- | arch/arm/include/asm/armv8/mmu.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/emif.h | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/global_data.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/spl.h | 4 | ||||
-rw-r--r-- | arch/arm/include/asm/system.h | 16 | ||||
-rw-r--r-- | arch/arm/lib/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/lib/asm-offsets.c | 46 | ||||
-rw-r--r-- | arch/arm/lib/bootm.c | 2 | ||||
-rw-r--r-- | arch/arm/lib/stack.c | 42 | ||||
-rw-r--r-- | arch/arm/mach-at91/Kconfig | 168 | ||||
-rw-r--r-- | arch/arm/mach-at91/Makefile (renamed from arch/arm/cpu/at91-common/Makefile) | 14 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm920t/Makefile (renamed from arch/arm/cpu/arm920t/at91/Makefile) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm920t/at91rm9200_devices.c (renamed from arch/arm/cpu/arm920t/at91/at91rm9200_devices.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm920t/clock.c (renamed from arch/arm/cpu/arm920t/at91/clock.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm920t/cpu.c (renamed from arch/arm/cpu/arm920t/at91/cpu.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm920t/lowlevel_init.S (renamed from arch/arm/cpu/arm920t/at91/lowlevel_init.S) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm920t/reset.c (renamed from arch/arm/cpu/arm920t/at91/reset.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm920t/timer.c (renamed from arch/arm/cpu/arm920t/at91/timer.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/Makefile (renamed from arch/arm/cpu/arm926ejs/at91/Makefile) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c (renamed from arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/clock.c (renamed from arch/arm/cpu/arm926ejs/at91/clock.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/cpu.c (renamed from arch/arm/cpu/arm926ejs/at91/cpu.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/eflash.c (renamed from arch/arm/cpu/arm926ejs/at91/eflash.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/led.c (renamed from arch/arm/cpu/arm926ejs/at91/led.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/lowlevel_init.S (renamed from arch/arm/cpu/arm926ejs/at91/lowlevel_init.S) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/reset.c (renamed from arch/arm/cpu/arm926ejs/at91/reset.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/arm926ejs/timer.c (renamed from arch/arm/cpu/arm926ejs/at91/timer.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/armv7/Makefile (renamed from arch/arm/cpu/armv7/at91/Makefile) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/armv7/clock.c (renamed from arch/arm/cpu/armv7/at91/clock.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/armv7/cpu.c (renamed from arch/arm/cpu/armv7/at91/cpu.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/armv7/reset.c (renamed from arch/arm/cpu/armv7/at91/reset.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/armv7/sama5d3_devices.c (renamed from arch/arm/cpu/armv7/at91/sama5d3_devices.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/armv7/sama5d4_devices.c (renamed from arch/arm/cpu/armv7/at91/sama5d4_devices.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/armv7/timer.c (renamed from arch/arm/cpu/armv7/at91/timer.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/config.mk | 9 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_common.h (renamed from arch/arm/include/asm/arch-at91/at91_common.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_dbu.h (renamed from arch/arm/include/asm/arch-at91/at91_dbu.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_eefc.h (renamed from arch/arm/include/asm/arch-at91/at91_eefc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_emac.h (renamed from arch/arm/include/asm/arch-at91/at91_emac.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_gpbr.h (renamed from arch/arm/include/asm/arch-at91/at91_gpbr.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91_matrix.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_mc.h (renamed from arch/arm/include/asm/arch-at91/at91_mc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_pdc.h (renamed from arch/arm/include/asm/arch-at91/at91_pdc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_pio.h (renamed from arch/arm/include/asm/arch-at91/at91_pio.h) | 12 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_pit.h (renamed from arch/arm/include/asm/arch-at91/at91_pit.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_pmc.h (renamed from arch/arm/include/asm/arch-at91/at91_pmc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_rstc.h (renamed from arch/arm/include/asm/arch-at91/at91_rstc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_rtt.h (renamed from arch/arm/include/asm/arch-at91/at91_rtt.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_spi.h (renamed from arch/arm/include/asm/arch-at91/at91_spi.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_st.h (renamed from arch/arm/include/asm/arch-at91/at91_st.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_tc.h (renamed from arch/arm/include/asm/arch-at91/at91_tc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_wdt.h (renamed from arch/arm/include/asm/arch-at91/at91_wdt.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91rm9200.h (renamed from arch/arm/include/asm/arch-at91/at91rm9200.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9260.h (renamed from arch/arm/include/asm/arch-at91/at91sam9260.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9260_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9260_matrix.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9261.h (renamed from arch/arm/include/asm/arch-at91/at91sam9261.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9261_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9261_matrix.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9263.h (renamed from arch/arm/include/asm/arch-at91/at91sam9263.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9263_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9263_matrix.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9_matrix.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9_sdramc.h (renamed from arch/arm/include/asm/arch-at91/at91sam9_sdramc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9_smc.h (renamed from arch/arm/include/asm/arch-at91/at91sam9_smc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9g45.h (renamed from arch/arm/include/asm/arch-at91/at91sam9g45.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9rl.h (renamed from arch/arm/include/asm/arch-at91/at91sam9rl.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9x5.h (renamed from arch/arm/include/asm/arch-at91/at91sam9x5.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h (renamed from arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/atmel_mpddrc.h (renamed from arch/arm/include/asm/arch-at91/atmel_mpddrc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/atmel_serial.h (renamed from arch/arm/include/asm/arch-at91/atmel_serial.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/atmel_usba_udc.h (renamed from arch/arm/include/asm/arch-at91/atmel_usba_udc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/clk.h (renamed from arch/arm/include/asm/arch-at91/clk.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/gpio.h (renamed from arch/arm/include/asm/arch-at91/gpio.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/hardware.h (renamed from arch/arm/include/asm/arch-at91/hardware.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/sama5_matrix.h (renamed from arch/arm/include/asm/arch-at91/sama5_matrix.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/sama5_sfr.h (renamed from arch/arm/include/asm/arch-at91/sama5_sfr.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/sama5d3.h (renamed from arch/arm/include/asm/arch-at91/sama5d3.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/sama5d3_smc.h (renamed from arch/arm/include/asm/arch-at91/sama5d3_smc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/sama5d4.h (renamed from arch/arm/include/asm/arch-at91/sama5d4.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/mpddrc.c (renamed from arch/arm/cpu/at91-common/mpddrc.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/phy.c (renamed from arch/arm/cpu/at91-common/phy.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/sdram.c (renamed from arch/arm/cpu/at91-common/sdram.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/spl.c (renamed from arch/arm/cpu/at91-common/spl.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/spl_at91.c (renamed from arch/arm/cpu/at91-common/spl_at91.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/spl_atmel.c (renamed from arch/arm/cpu/at91-common/spl_atmel.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-at91/u-boot-spl.lds (renamed from arch/arm/cpu/at91-common/u-boot-spl.lds) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/Kconfig (renamed from arch/arm/cpu/arm926ejs/davinci/Kconfig) | 4 | ||||
-rw-r--r-- | arch/arm/mach-davinci/Makefile (renamed from arch/arm/cpu/arm926ejs/davinci/Makefile) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/config.mk (renamed from arch/arm/cpu/arm926ejs/davinci/config.mk) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/cpu.c (renamed from arch/arm/cpu/arm926ejs/davinci/cpu.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/da830_pinmux.c (renamed from arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/da850_lowlevel.c (renamed from arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/da850_pinmux.c (renamed from arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/dm355.c (renamed from arch/arm/cpu/arm926ejs/davinci/dm355.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/dm365.c (renamed from arch/arm/cpu/arm926ejs/davinci/dm365.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/dm365_lowlevel.c (renamed from arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/dm644x.c (renamed from arch/arm/cpu/arm926ejs/davinci/dm644x.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/dm646x.c (renamed from arch/arm/cpu/arm926ejs/davinci/dm646x.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/dp83848.c (renamed from arch/arm/cpu/arm926ejs/davinci/dp83848.c) | 2 | ||||
-rw-r--r-- | arch/arm/mach-davinci/et1011c.c (renamed from arch/arm/cpu/arm926ejs/davinci/et1011c.c) | 2 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/aintc_defs.h (renamed from arch/arm/include/asm/arch-davinci/aintc_defs.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/da850_lowlevel.h (renamed from arch/arm/include/asm/arch-davinci/da850_lowlevel.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/da8xx-usb.h (renamed from arch/arm/include/asm/arch-davinci/da8xx-usb.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/davinci_misc.h (renamed from arch/arm/include/asm/arch-davinci/davinci_misc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/ddr2_defs.h (renamed from arch/arm/include/asm/arch-davinci/ddr2_defs.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/dm365_lowlevel.h (renamed from arch/arm/include/asm/arch-davinci/dm365_lowlevel.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/emac_defs.h (renamed from arch/arm/include/asm/arch-davinci/emac_defs.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/gpio.h (renamed from arch/arm/include/asm/arch-davinci/gpio.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/hardware.h (renamed from arch/arm/include/asm/arch-davinci/hardware.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/i2c_defs.h (renamed from arch/arm/include/asm/arch-davinci/i2c_defs.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/pinmux_defs.h (renamed from arch/arm/include/asm/arch-davinci/pinmux_defs.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/pll_defs.h (renamed from arch/arm/include/asm/arch-davinci/pll_defs.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/psc_defs.h (renamed from arch/arm/include/asm/arch-davinci/psc_defs.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/sdmmc_defs.h (renamed from arch/arm/include/asm/arch-davinci/sdmmc_defs.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/syscfg_defs.h (renamed from arch/arm/include/asm/arch-davinci/syscfg_defs.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/timer_defs.h (renamed from arch/arm/include/asm/arch-davinci/timer_defs.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/ksz8873.c (renamed from arch/arm/cpu/arm926ejs/davinci/ksz8873.c) | 2 | ||||
-rw-r--r-- | arch/arm/mach-davinci/lowlevel_init.S (renamed from arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/lxt972.c (renamed from arch/arm/cpu/arm926ejs/davinci/lxt972.c) | 2 | ||||
-rw-r--r-- | arch/arm/mach-davinci/misc.c (renamed from arch/arm/cpu/arm926ejs/davinci/misc.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/pinmux.c (renamed from arch/arm/cpu/arm926ejs/davinci/pinmux.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/psc.c (renamed from arch/arm/cpu/arm926ejs/davinci/psc.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/reset.c (renamed from arch/arm/cpu/arm926ejs/davinci/reset.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/spl.c (renamed from arch/arm/cpu/arm926ejs/davinci/spl.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-davinci/timer.c (renamed from arch/arm/cpu/arm926ejs/davinci/timer.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-highbank/Kconfig (renamed from arch/arm/cpu/armv7/highbank/Kconfig) | 0 | ||||
-rw-r--r-- | arch/arm/mach-highbank/Makefile (renamed from arch/arm/cpu/armv7/highbank/Makefile) | 0 | ||||
-rw-r--r-- | arch/arm/mach-highbank/timer.c (renamed from arch/arm/cpu/armv7/highbank/timer.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/Kconfig (renamed from arch/arm/cpu/armv7/keystone/Kconfig) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/Makefile (renamed from arch/arm/cpu/armv7/keystone/Makefile) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/clock-k2e.c (renamed from arch/arm/cpu/armv7/keystone/clock-k2e.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/clock-k2hk.c (renamed from arch/arm/cpu/armv7/keystone/clock-k2hk.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/clock-k2l.c (renamed from arch/arm/cpu/armv7/keystone/clock-k2l.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/clock.c (renamed from arch/arm/cpu/armv7/keystone/clock.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/cmd_clock.c (renamed from arch/arm/cpu/armv7/keystone/cmd_clock.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/cmd_ddr3.c (renamed from arch/arm/cpu/armv7/keystone/cmd_ddr3.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/cmd_mon.c (renamed from arch/arm/cpu/armv7/keystone/cmd_mon.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/ddr3.c (renamed from arch/arm/cpu/armv7/keystone/ddr3.c) | 5 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/clock-k2e.h (renamed from arch/arm/include/asm/arch-keystone/clock-k2e.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/clock-k2hk.h (renamed from arch/arm/include/asm/arch-keystone/clock-k2hk.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/clock-k2l.h (renamed from arch/arm/include/asm/arch-keystone/clock-k2l.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/clock.h (renamed from arch/arm/include/asm/arch-keystone/clock.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/clock_defs.h (renamed from arch/arm/include/asm/arch-keystone/clock_defs.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/ddr3.h (renamed from arch/arm/include/asm/arch-keystone/ddr3.h) | 5 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/hardware-k2e.h (renamed from arch/arm/include/asm/arch-keystone/hardware-k2e.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/hardware-k2hk.h (renamed from arch/arm/include/asm/arch-keystone/hardware-k2hk.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/hardware-k2l.h (renamed from arch/arm/include/asm/arch-keystone/hardware-k2l.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/hardware.h (renamed from arch/arm/include/asm/arch-keystone/hardware.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/i2c_defs.h (renamed from arch/arm/include/asm/arch-keystone/i2c_defs.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/mon.h (renamed from arch/arm/include/asm/arch-keystone/mon.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/msmc.h (renamed from arch/arm/include/asm/arch-keystone/msmc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/psc_defs.h (renamed from arch/arm/include/asm/arch-keystone/psc_defs.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/include/mach/xhci-keystone.h (renamed from arch/arm/include/asm/arch-keystone/xhci-keystone.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/init.c (renamed from arch/arm/cpu/armv7/keystone/init.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/keystone.c (renamed from arch/arm/cpu/armv7/keystone/keystone.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/msmc.c (renamed from arch/arm/cpu/armv7/keystone/msmc.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-keystone/psc.c (renamed from arch/arm/cpu/armv7/keystone/psc.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/Kconfig (renamed from arch/arm/cpu/arm926ejs/kirkwood/Kconfig) | 0 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/Makefile (renamed from arch/arm/cpu/arm926ejs/kirkwood/Makefile) | 0 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/cache.c (renamed from arch/arm/cpu/arm926ejs/kirkwood/cache.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/cpu.c (renamed from arch/arm/cpu/arm926ejs/kirkwood/cpu.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/include/mach/config.h (renamed from arch/arm/include/asm/arch-kirkwood/config.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/include/mach/cpu.h (renamed from arch/arm/include/asm/arch-kirkwood/cpu.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/include/mach/gpio.h (renamed from arch/arm/include/asm/arch-kirkwood/gpio.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/include/mach/kw88f6192.h (renamed from arch/arm/include/asm/arch-kirkwood/kw88f6192.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/include/mach/kw88f6281.h (renamed from arch/arm/include/asm/arch-kirkwood/kw88f6281.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/include/mach/mpp.h (renamed from arch/arm/include/asm/arch-kirkwood/mpp.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/include/mach/soc.h (renamed from arch/arm/include/asm/arch-kirkwood/soc.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/mpp.c (renamed from arch/arm/cpu/arm926ejs/kirkwood/mpp.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-nomadik/Kconfig (renamed from arch/arm/cpu/arm926ejs/nomadik/Kconfig) | 0 | ||||
-rw-r--r-- | arch/arm/mach-nomadik/Makefile (renamed from arch/arm/cpu/arm926ejs/nomadik/Makefile) | 0 | ||||
-rw-r--r-- | arch/arm/mach-nomadik/gpio.c (renamed from arch/arm/cpu/arm926ejs/nomadik/gpio.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-nomadik/include/mach/gpio.h (renamed from arch/arm/include/asm/arch-nomadik/gpio.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-nomadik/include/mach/mtu.h (renamed from arch/arm/include/asm/arch-nomadik/mtu.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-nomadik/reset.S (renamed from arch/arm/cpu/arm926ejs/nomadik/reset.S) | 0 | ||||
-rw-r--r-- | arch/arm/mach-nomadik/timer.c (renamed from arch/arm/cpu/arm926ejs/nomadik/timer.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/Kconfig (renamed from arch/arm/cpu/arm926ejs/orion5x/Kconfig) | 0 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/Makefile (renamed from arch/arm/cpu/arm926ejs/orion5x/Makefile) | 0 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/cpu.c (renamed from arch/arm/cpu/arm926ejs/orion5x/cpu.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/dram.c (renamed from arch/arm/cpu/arm926ejs/orion5x/dram.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/include/mach/cpu.h (renamed from arch/arm/include/asm/arch-orion5x/cpu.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/include/mach/mv88f5182.h (renamed from arch/arm/include/asm/arch-orion5x/mv88f5182.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/include/mach/orion5x.h (renamed from arch/arm/include/asm/arch-orion5x/orion5x.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/lowlevel_init.S (renamed from arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S) | 0 | ||||
-rw-r--r-- | arch/arm/mach-orion5x/timer.c (renamed from arch/arm/cpu/arm926ejs/orion5x/timer.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/Kconfig | 52 | ||||
-rw-r--r-- | arch/arm/mach-tegra/Makefile (renamed from arch/arm/cpu/tegra-common/Makefile) | 12 | ||||
-rw-r--r-- | arch/arm/mach-tegra/ap.c (renamed from arch/arm/cpu/tegra-common/ap.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/board.c (renamed from arch/arm/cpu/tegra-common/board.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/cache.c (renamed from arch/arm/cpu/tegra-common/cache.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/clock.c (renamed from arch/arm/cpu/tegra-common/clock.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/cmd_enterrcm.c (renamed from arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/cpu.c (renamed from arch/arm/cpu/arm720t/tegra-common/cpu.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/cpu.h (renamed from arch/arm/cpu/arm720t/tegra-common/cpu.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/lowlevel_init.S (renamed from arch/arm/cpu/tegra-common/lowlevel_init.S) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/pinmux-common.c (renamed from arch/arm/cpu/tegra-common/pinmux-common.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/powergate.c (renamed from arch/arm/cpu/tegra-common/powergate.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/spl.c (renamed from arch/arm/cpu/arm720t/tegra-common/spl.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/sys_info.c (renamed from arch/arm/cpu/tegra-common/sys_info.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra114/Kconfig (renamed from arch/arm/cpu/armv7/tegra114/Kconfig) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra114/Makefile (renamed from arch/arm/cpu/tegra114-common/Makefile) | 5 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra114/clock.c (renamed from arch/arm/cpu/tegra114-common/clock.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra114/cpu.c (renamed from arch/arm/cpu/arm720t/tegra114/cpu.c) | 2 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra114/funcmux.c (renamed from arch/arm/cpu/tegra114-common/funcmux.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra114/pinmux.c (renamed from arch/arm/cpu/tegra114-common/pinmux.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra124/Kconfig (renamed from arch/arm/cpu/armv7/tegra124/Kconfig) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra124/Makefile (renamed from arch/arm/cpu/tegra124-common/Makefile) | 2 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra124/clock.c (renamed from arch/arm/cpu/tegra124-common/clock.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra124/cpu.c (renamed from arch/arm/cpu/arm720t/tegra124/cpu.c) | 2 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra124/funcmux.c (renamed from arch/arm/cpu/tegra124-common/funcmux.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra124/pinmux.c (renamed from arch/arm/cpu/tegra124-common/pinmux.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra124/xusb-padctl.c (renamed from arch/arm/cpu/tegra124-common/xusb-padctl.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/Kconfig (renamed from arch/arm/cpu/armv7/tegra20/Kconfig) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/Makefile (renamed from arch/arm/cpu/tegra20-common/Makefile) | 10 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/clock.c (renamed from arch/arm/cpu/tegra20-common/clock.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/cpu.c (renamed from arch/arm/cpu/arm720t/tegra20/cpu.c) | 2 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/crypto.c (renamed from arch/arm/cpu/tegra20-common/crypto.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/crypto.h (renamed from arch/arm/cpu/tegra20-common/crypto.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/display.c (renamed from arch/arm/cpu/armv7/tegra20/display.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/emc.c (renamed from arch/arm/cpu/tegra20-common/emc.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/funcmux.c (renamed from arch/arm/cpu/tegra20-common/funcmux.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/pinmux.c (renamed from arch/arm/cpu/tegra20-common/pinmux.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/pmu.c (renamed from arch/arm/cpu/tegra20-common/pmu.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/pwm.c (renamed from arch/arm/cpu/armv7/tegra20/pwm.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/warmboot.c (renamed from arch/arm/cpu/tegra20-common/warmboot.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/warmboot_avp.c (renamed from arch/arm/cpu/tegra20-common/warmboot_avp.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra20/warmboot_avp.h (renamed from arch/arm/cpu/tegra20-common/warmboot_avp.h) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra30/Kconfig (renamed from arch/arm/cpu/armv7/tegra30/Kconfig) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra30/Makefile (renamed from arch/arm/cpu/tegra30-common/Makefile) | 5 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra30/clock.c (renamed from arch/arm/cpu/tegra30-common/clock.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra30/cpu.c (renamed from arch/arm/cpu/arm720t/tegra30/cpu.c) | 2 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra30/funcmux.c (renamed from arch/arm/cpu/tegra30-common/funcmux.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra30/pinmux.c (renamed from arch/arm/cpu/tegra30-common/pinmux.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/vpr.c (renamed from arch/arm/cpu/tegra-common/vpr.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-tegra/xusb-padctl.c (renamed from arch/arm/cpu/tegra-common/xusb-padctl.c) | 0 | ||||
-rw-r--r-- | arch/arm/mach-versatile/Kconfig (renamed from arch/arm/cpu/arm926ejs/versatile/Kconfig) | 0 | ||||
-rw-r--r-- | arch/arm/mach-versatile/Makefile (renamed from arch/arm/cpu/arm926ejs/versatile/Makefile) | 0 | ||||
-rw-r--r-- | arch/arm/mach-versatile/reset.S (renamed from arch/arm/cpu/arm926ejs/versatile/reset.S) | 0 | ||||
-rw-r--r-- | arch/arm/mach-versatile/timer.c (renamed from arch/arm/cpu/arm926ejs/versatile/timer.c) | 0 | ||||
-rw-r--r-- | arch/avr32/config.mk | 3 | ||||
-rw-r--r-- | arch/avr32/cpu/Makefile | 1 | ||||
-rw-r--r-- | arch/avr32/cpu/at32ap700x/mmu.c | 8 | ||||
-rw-r--r-- | arch/avr32/cpu/cpu.c | 2 | ||||
-rw-r--r-- | arch/avr32/cpu/exception.c | 6 | ||||
-rw-r--r-- | arch/avr32/cpu/mmc.c | 16 | ||||
-rw-r--r-- | arch/avr32/cpu/u-boot.lds | 2 | ||||
-rw-r--r-- | arch/avr32/include/asm/arch-at32ap700x/mmu.h | 6 | ||||
-rw-r--r-- | arch/avr32/include/asm/config.h | 1 | ||||
-rw-r--r-- | arch/avr32/include/asm/dma-mapping.h | 7 | ||||
-rw-r--r-- | arch/avr32/include/asm/global_data.h | 1 | ||||
-rw-r--r-- | arch/avr32/include/asm/u-boot.h | 10 | ||||
-rw-r--r-- | arch/avr32/lib/Makefile | 3 | ||||
-rw-r--r-- | arch/avr32/lib/board.c | 83 | ||||
-rw-r--r-- | arch/avr32/lib/dram_init.c | 17 | ||||
-rw-r--r-- | arch/avr32/lib/interrupts.c | 5 | ||||
-rw-r--r-- | arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 8 | ||||
-rw-r--r-- | arch/powerpc/cpu/ppc4xx/config.mk | 5 | ||||
-rw-r--r-- | arch/powerpc/cpu/ppc4xx/cpu_init.c | 2 | ||||
-rw-r--r-- | arch/powerpc/cpu/ppc4xx/start.S | 18 | ||||
-rw-r--r-- | arch/powerpc/cpu/ppc4xx/u-boot.lds | 8 | ||||
-rw-r--r-- | arch/powerpc/dts/Makefile | 11 | ||||
-rw-r--r-- | arch/powerpc/dts/arches.dts | 339 | ||||
-rw-r--r-- | arch/powerpc/dts/canyonlands.dts | 561 | ||||
-rw-r--r-- | arch/powerpc/dts/glacier.dts | 582 | ||||
-rw-r--r-- | arch/powerpc/include/asm/arch-ppc4xx/gpio.h | 7 | ||||
-rw-r--r-- | arch/powerpc/include/asm/linkage.h | 7 | ||||
-rw-r--r-- | arch/powerpc/include/asm/ppc460ex_gt.h | 2 | ||||
-rw-r--r-- | arch/powerpc/lib/Makefile | 1 | ||||
-rw-r--r-- | arch/powerpc/lib/stack.c | 31 | ||||
-rw-r--r-- | arch/sandbox/Kconfig | 24 | ||||
-rw-r--r-- | arch/sandbox/config.mk | 12 | ||||
-rw-r--r-- | arch/sandbox/cpu/start.c | 6 | ||||
-rw-r--r-- | arch/sandbox/cpu/state.c | 5 | ||||
-rw-r--r-- | arch/sandbox/include/asm/state.h | 15 | ||||
-rw-r--r-- | arch/x86/Kconfig | 15 |
390 files changed, 3677 insertions, 4824 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 132123bcaf..3d419bca3e 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -40,6 +40,7 @@ config OPENRISC config PPC bool "PowerPC architecture" select HAVE_PRIVATE_LIBGCC + select SUPPORT_OF_CONTROL config SANDBOX bool "Sandbox" diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index a8dc4e2336..24f5c02c76 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -8,30 +8,79 @@ config USE_PRIVATE_LIBGCC default y config SYS_CPU - default "arcv1" + default "arcv1" if ISA_ARCOMPACT + default "arcv2" if ISA_ARCV2 + +choice + prompt "ARC Instruction Set" + default ISA_ARCOMPACT + +config ISA_ARCOMPACT + bool "ARCompact ISA" + help + The original ARC ISA of ARC600/700 cores + +config ISA_ARCV2 + bool "ARC ISA v2" + help + ISA for the Next Generation ARC-HS cores + +endchoice choice prompt "CPU selection" - default CPU_ARC770D + default CPU_ARC770D if ISA_ARCOMPACT + default CPU_ARCHS38 if ISA_ARCV2 config CPU_ARC750D bool "ARC 750D" select ARC_MMU_V2 + depends on ISA_ARCOMPACT help Choose this option to build an U-Boot for ARC750D CPU. config CPU_ARC770D bool "ARC 770D" select ARC_MMU_V3 + depends on ISA_ARCOMPACT help Choose this option to build an U-Boot for ARC770D CPU. +config CPU_ARCEM6 + bool "ARC EM6" + select ARC_MMU_ABSENT + depends on ISA_ARCV2 + help + Next Generation ARC Core based on ISA-v2 ISA without MMU. + +config CPU_ARCHS36 + bool "ARC HS36" + select ARC_MMU_ABSENT + depends on ISA_ARCV2 + help + Next Generation ARC Core based on ISA-v2 ISA without MMU. + +config CPU_ARCHS38 + bool "ARC HS38" + select ARC_MMU_V4 + depends on ISA_ARCV2 + help + Next Generation ARC Core based on ISA-v2 ISA with MMU. + endchoice choice prompt "MMU Version" default ARC_MMU_V3 if CPU_ARC770D default ARC_MMU_V2 if CPU_ARC750D + default ARC_MMU_ABSENT if CPU_ARCEM6 + default ARC_MMU_ABSENT if CPU_ARCHS36 + default ARC_MMU_V4 if CPU_ARCHS38 + +config ARC_MMU_ABSENT + bool "No MMU" + help + No MMU config ARC_MMU_V2 bool "MMU v2" @@ -48,6 +97,12 @@ config ARC_MMU_V3 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) Shared Address Spaces (SASID) +config ARC_MMU_V4 + bool "MMU v4" + depends on CPU_ARCHS38 + help + Introduced as a part of ARC HS38 release. + endchoice config CPU_BIG_ENDIAN diff --git a/arch/arc/config.mk b/arch/arc/config.mk index f1e81b6895..4fcd4076c4 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -38,6 +38,18 @@ ifdef CONFIG_CPU_ARC770D PLATFORM_CPPFLAGS += -marc700 -mlock -mswape endif +ifdef CONFIG_CPU_ARCEM6 +PLATFORM_CPPFLAGS += -marcem +endif + +ifdef CONFIG_CPU_ARCHS34 +PLATFORM_CPPFLAGS += -marchs +endif + +ifdef CONFIG_CPU_ARCHS38 +PLATFORM_CPPFLAGS += -marchs +endif + PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2 # Needed for relocation diff --git a/arch/arc/cpu/arcv2/Makefile b/arch/arc/cpu/arcv2/Makefile new file mode 100644 index 0000000000..cc69e5a17e --- /dev/null +++ b/arch/arc/cpu/arcv2/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += start.o diff --git a/arch/arc/cpu/arcv2/start.S b/arch/arc/cpu/arcv2/start.S new file mode 100644 index 0000000000..3ce689675f --- /dev/null +++ b/arch/arc/cpu/arcv2/start.S @@ -0,0 +1,254 @@ +/* + * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <asm/arcregs.h> + +/* + * Note on the LD/ST addressing modes with address register write-back + * + * LD.a same as LD.aw + * + * LD.a reg1, [reg2, x] => Pre Incr + * Eff Addr for load = [reg2 + x] + * + * LD.ab reg1, [reg2, x] => Post Incr + * Eff Addr for load = [reg2] + */ + +.macro PUSH reg + st.a \reg, [%sp, -4] +.endm + +.macro PUSHAX aux + lr %r9, [\aux] + PUSH %r9 +.endm + +.macro SAVE_R1_TO_R24 + PUSH %r1 + PUSH %r2 + PUSH %r3 + PUSH %r4 + PUSH %r5 + PUSH %r6 + PUSH %r7 + PUSH %r8 + PUSH %r9 + PUSH %r10 + PUSH %r11 + PUSH %r12 + PUSH %r13 + PUSH %r14 + PUSH %r15 + PUSH %r16 + PUSH %r17 + PUSH %r18 + PUSH %r19 + PUSH %r20 + PUSH %r21 + PUSH %r22 + PUSH %r23 + PUSH %r24 +.endm + +.macro SAVE_ALL_SYS + /* saving %r0 to reg->r0 in advance since weread %ecr into it */ + st %r0, [%sp, -8] + lr %r0, [%ecr] /* all stack addressing is manual so far */ + st %r0, [%sp] + st %sp, [%sp, -4] + /* now move %sp to reg->r0 position so we can do "push" automatically */ + sub %sp, %sp, 8 + + SAVE_R1_TO_R24 + PUSH %r25 + PUSH %gp + PUSH %fp + PUSH %blink + PUSHAX %eret + PUSHAX %erstatus + PUSH %lp_count + PUSHAX %lp_end + PUSHAX %lp_start + PUSHAX %erbta +.endm + +.macro SAVE_EXCEPTION_SOURCE +#ifdef CONFIG_MMU + /* If MMU exists exception faulting address is loaded in EFA reg */ + lr %r0, [%efa] +#else + /* Otherwise in ERET (exception return) reg */ + lr %r0, [%eret] +#endif +.endm + +.section .ivt, "a",@progbits +.align 4 + /* Critical system events */ +.word _start /* 0 - 0x000 */ +.word memory_error /* 1 - 0x008 */ +.word instruction_error /* 2 - 0x010 */ + + /* Exceptions */ +.word EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */ +.word EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */ +.word EV_TLBMissD /* 0x110, Data TLB miss (0x22) */ +.word EV_TLBProtV /* 0x118, Protection Violation (0x23) + or Misaligned Access */ +.word EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */ +.word EV_Trap /* 0x128, Trap exception (0x25) */ +.word EV_Extension /* 0x130, Extn Intruction Excp (0x26) */ + + /* Device interrupts */ +.rept 29 + j interrupt_handler /* 3:31 - 0x018:0xF8 */ +.endr + +.text +.globl _start +_start: + /* Setup interrupt vector base that matches "__text_start" */ + sr __ivt_start, [ARC_AUX_INTR_VEC_BASE] + + /* Setup stack pointer */ + mov %sp, CONFIG_SYS_INIT_SP_ADDR + mov %fp, %sp + + /* Clear bss */ + mov %r0, __bss_start + mov %r1, __bss_end + +clear_bss: + st.ab 0, [%r0, 4] + brlt %r0, %r1, clear_bss + + /* Zero the one and only argument of "board_init_f" */ + mov_s %r0, 0 + j board_init_f + +memory_error: + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_memory_error + +instruction_error: + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_instruction_error + +interrupt_handler: + /* Todo - save and restore CPU context when interrupts will be in use */ + bl do_interrupt_handler + rtie + +EV_MachineCheck: + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_machine_check_fault + +EV_TLBMissI: + SAVE_ALL_SYS + mov %r0, %sp + j do_itlb_miss + +EV_TLBMissD: + SAVE_ALL_SYS + mov %r0, %sp + j do_dtlb_miss + +EV_TLBProtV: + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_tlb_prot_violation + +EV_PrivilegeV: + SAVE_ALL_SYS + mov %r0, %sp + j do_privilege_violation + +EV_Trap: + SAVE_ALL_SYS + mov %r0, %sp + j do_trap + +EV_Extension: + SAVE_ALL_SYS + mov %r0, %sp + j do_extension + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r0 = start_addr_sp + * r1 = new__gd + * r2 = relocaddr + */ +.align 4 +.globl relocate_code +relocate_code: + /* + * r0-r12 might be clobbered by C functions + * so we use r13-r16 for storage here + */ + mov %r13, %r0 /* save addr_sp */ + mov %r14, %r1 /* save addr of gd */ + mov %r15, %r2 /* save addr of destination */ + + mov %r16, %r2 /* %r9 - relocation offset */ + sub %r16, %r16, __image_copy_start + +/* Set up the stack */ +stack_setup: + mov %sp, %r13 + mov %fp, %sp + +/* Check if monitor is loaded right in place for relocation */ + mov %r0, __image_copy_start + cmp %r0, %r15 /* skip relocation if code loaded */ + bz do_board_init_r /* in target location already */ + +/* Copy data (__image_copy_start - __image_copy_end) to new location */ + mov %r1, %r15 + mov %r2, __image_copy_end + sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */ + asr %r2, %r2, 2 /* r3 <- amount of words to copy */ + mov %lp_count, %r2 + lp copy_end + ld.ab %r2,[%r0,4] + st.ab %r2,[%r1,4] +copy_end: + +/* Fix relocations related issues */ + bl do_elf_reloc_fixups +#ifndef CONFIG_SYS_ICACHE_OFF + bl invalidate_icache_all +#endif +#ifndef CONFIG_SYS_DCACHE_OFF + bl flush_dcache_all +#endif + +/* Update position of intterupt vector table */ + lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */ + add %r0, %r0, %r16 /* Update address */ + sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */ + +do_board_init_r: +/* Prepare for exection of "board_init_r" in relocated monitor */ + mov %r2, board_init_r /* old address of "board_init_r()" */ + add %r2, %r2, %r16 /* new address of "board_init_r()" */ + mov %r0, %r14 /* 1-st parameter: gd_t */ + mov %r1, %r15 /* 2-nd parameter: dest_addr */ + j [%r2] diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index 2725961221..8a77cd93af 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -17,10 +17,14 @@ #define ARCH_DMA_MINALIGN 128 #endif -#if defined(CONFIG_ARC_MMU_V2) +#if defined(ARC_MMU_ABSENT) +#define CONFIG_ARC_MMU_VER 0 +#elif defined(CONFIG_ARC_MMU_V2) #define CONFIG_ARC_MMU_VER 2 #elif defined(CONFIG_ARC_MMU_V3) #define CONFIG_ARC_MMU_VER 3 +#elif defined(CONFIG_ARC_MMU_V4) +#define CONFIG_ARC_MMU_VER 4 #endif #endif /* __ASM_ARC_CACHE_H */ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a3eb8760e9..eb92297cb3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -73,21 +73,8 @@ config TARGET_INTEGRATORCP_CM920T bool "Support integratorcp_cm920t" select CPU_ARM920T -config TARGET_A320EVB - bool "Support a320evb" - select CPU_ARM920T - -config TARGET_AT91RM9200EK - bool "Support at91rm9200ek" - select CPU_ARM920T - -config TARGET_EB_CPUX9K2 - bool "Support eb_cpux9k2" - select CPU_ARM920T - -config TARGET_CPUAT91 - bool "Support cpuat91" - select CPU_ARM920T +config ARCH_AT91 + bool "Atmel AT91" config TARGET_EDB93XX bool "Support edb93xx" @@ -97,14 +84,6 @@ config TARGET_SCB9328 bool "Support scb9328" select CPU_ARM920T -config TARGET_CM4008 - bool "Support cm4008" - select CPU_ARM920T - -config TARGET_CM41XX - bool "Support cm41xx" - select CPU_ARM920T - config TARGET_VCMA9 bool "Support VCMA9" select CPU_ARM920T @@ -129,100 +108,6 @@ config TARGET_GPLUGD bool "Support gplugd" select CPU_ARM926EJS -config TARGET_AFEB9260 - bool "Support afeb9260" - select CPU_ARM926EJS - -config TARGET_AT91SAM9260EK - bool "Support at91sam9260ek" - select CPU_ARM926EJS - -config TARGET_AT91SAM9261EK - bool "Support at91sam9261ek" - select CPU_ARM926EJS - -config TARGET_AT91SAM9263EK - bool "Support at91sam9263ek" - select CPU_ARM926EJS - -config TARGET_AT91SAM9M10G45EK - bool "Support at91sam9m10g45ek" - select CPU_ARM926EJS - -config TARGET_AT91SAM9N12EK - bool "Support at91sam9n12ek" - select CPU_ARM926EJS - -config TARGET_AT91SAM9RLEK - bool "Support at91sam9rlek" - select CPU_ARM926EJS - -config TARGET_AT91SAM9X5EK - bool "Support at91sam9x5ek" - select CPU_ARM926EJS - -config TARGET_SNAPPER9260 - bool "Support snapper9260" - select CPU_ARM926EJS - -config TARGET_VL_MA2SC - bool "Support vl_ma2sc" - select CPU_ARM926EJS - -config TARGET_SBC35_A9G20 - bool "Support sbc35_a9g20" - select CPU_ARM926EJS - -config TARGET_TNY_A9260 - bool "Support tny_a9260" - select CPU_ARM926EJS - -config TARGET_USB_A9263 - bool "Support usb_a9263" - select CPU_ARM926EJS - -config TARGET_ETHERNUT5 - bool "Support ethernut5" - select CPU_ARM926EJS - -config TARGET_MEESC - bool "Support meesc" - select CPU_ARM926EJS - -config TARGET_OTC570 - bool "Support otc570" - select CPU_ARM926EJS - -config TARGET_CPU9260 - bool "Support cpu9260" - select CPU_ARM926EJS - -config TARGET_PM9261 - bool "Support pm9261" - select CPU_ARM926EJS - -config TARGET_PM9263 - bool "Support pm9263" - select CPU_ARM926EJS - -config TARGET_PM9G45 - bool "Support pm9g45" - select CPU_ARM926EJS - -config TARGET_CORVUS - select SUPPORT_SPL - bool "Support corvus" - select CPU_ARM926EJS - -config TARGET_TAURUS - select SUPPORT_SPL - bool "Support taurus" - select CPU_ARM926EJS - -config TARGET_STAMP9G20 - bool "Support stamp9g20" - select CPU_ARM926EJS - config ARCH_DAVINCI bool "TI DaVinci" select CPU_ARM926EJS @@ -247,10 +132,6 @@ config TARGET_DEVKIT3250 bool "Support devkit3250" select CPU_ARM926EJS -config TARGET_JADECPU - bool "Support jadecpu" - select CPU_ARM926EJS - config TARGET_MX25PDK bool "Support mx25pdk" select CPU_ARM926EJS @@ -330,10 +211,6 @@ config ORION5X bool "Marvell Orion" select CPU_ARM926EJS -config TARGET_DKB - bool "Support dkb" - select CPU_ARM926EJS - config TARGET_SPEAR300 bool "Support spear300" select CPU_ARM926EJS @@ -413,9 +290,9 @@ config TARGET_RPI bool "Support rpi" select CPU_ARM1176 -config TARGET_TNETV107X_EVM - bool "Support tnetv107x_evm" - select CPU_ARM1176 +config TARGET_RPI_2 + bool "Support rpi_2" + select CPU_V7 config TARGET_INTEGRATORAP_CM946ES bool "Support integratorap_cm946es" @@ -514,26 +391,6 @@ config TARGET_TI816X_EVM select CPU_V7 select SUPPORT_SPL -config TARGET_SAMA5D3_XPLAINED - bool "Support sama5d3_xplained" - select CPU_V7 - select SUPPORT_SPL - -config TARGET_SAMA5D3XEK - bool "Support sama5d3xek" - select CPU_V7 - select SUPPORT_SPL - -config TARGET_SAMA5D4_XPLAINED - bool "Support sama5d4_xplained" - select CPU_V7 - select SUPPORT_SPL - -config TARGET_SAMA5D4EK - bool "Support sama5d4ek" - select CPU_V7 - select SUPPORT_SPL - config TARGET_BCM28155_AP bool "Support bcm28155_ap" select CPU_V7 @@ -743,9 +600,8 @@ config TEGRA bool "NVIDIA Tegra" select SUPPORT_SPL select SPL - select OF_CONTROL if !SPL_BUILD - select CPU_ARM720T if SPL_BUILD - select CPU_V7 if !SPL_BUILD + select OF_CONTROL + select CPU_V7 config TARGET_VEXPRESS64_AEMV8A bool "Support vexpress_aemv8a" @@ -837,21 +693,25 @@ config ARCH_UNIPHIER select CPU_V7 select SUPPORT_SPL select SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL endchoice -source "arch/arm/cpu/arm926ejs/davinci/Kconfig" +source "arch/arm/mach-at91/Kconfig" + +source "arch/arm/mach-davinci/Kconfig" + +source "arch/arm/cpu/arm1176/bcm2835/Kconfig" source "arch/arm/cpu/armv7/exynos/Kconfig" -source "arch/arm/cpu/armv7/highbank/Kconfig" +source "arch/arm/mach-highbank/Kconfig" -source "arch/arm/cpu/armv7/keystone/Kconfig" +source "arch/arm/mach-keystone/Kconfig" -source "arch/arm/cpu/arm926ejs/kirkwood/Kconfig" +source "arch/arm/mach-kirkwood/Kconfig" -source "arch/arm/cpu/arm926ejs/nomadik/Kconfig" +source "arch/arm/mach-nomadik/Kconfig" source "arch/arm/cpu/armv7/omap3/Kconfig" @@ -859,17 +719,17 @@ source "arch/arm/cpu/armv7/omap4/Kconfig" source "arch/arm/cpu/armv7/omap5/Kconfig" -source "arch/arm/cpu/arm926ejs/orion5x/Kconfig" +source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/cpu/armv7/rmobile/Kconfig" source "arch/arm/cpu/armv7/s5pc1xx/Kconfig" -source "arch/arm/cpu/armv7/tegra-common/Kconfig" +source "arch/arm/mach-tegra/Kconfig" source "arch/arm/cpu/armv7/uniphier/Kconfig" -source "arch/arm/cpu/arm926ejs/versatile/Kconfig" +source "arch/arm/mach-versatile/Kconfig" source "arch/arm/cpu/armv7/zynq/Kconfig" @@ -878,47 +738,25 @@ source "arch/arm/cpu/armv7/Kconfig" source "board/aristainetos/Kconfig" source "board/BuR/kwb/Kconfig" source "board/BuR/tseries/Kconfig" -source "board/BuS/eb_cpux9k2/Kconfig" -source "board/BuS/vl_ma2sc/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/db-mv784mp-gp/Kconfig" -source "board/Marvell/dkb/Kconfig" source "board/Marvell/gplugd/Kconfig" -source "board/afeb9260/Kconfig" source "board/altera/socfpga/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/integrator/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" -source "board/atmel/at91rm9200ek/Kconfig" -source "board/atmel/at91sam9260ek/Kconfig" -source "board/atmel/at91sam9261ek/Kconfig" -source "board/atmel/at91sam9263ek/Kconfig" -source "board/atmel/at91sam9m10g45ek/Kconfig" -source "board/atmel/at91sam9n12ek/Kconfig" -source "board/atmel/at91sam9rlek/Kconfig" -source "board/atmel/at91sam9x5ek/Kconfig" -source "board/atmel/sama5d3_xplained/Kconfig" -source "board/atmel/sama5d3xek/Kconfig" -source "board/atmel/sama5d4_xplained/Kconfig" -source "board/atmel/sama5d4ek/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/balloon3/Kconfig" source "board/barco/platinum/Kconfig" source "board/barco/titanium/Kconfig" source "board/bluegiga/apx4devkit/Kconfig" -source "board/bluewater/snapper9260/Kconfig" source "board/boundary/nitrogen6x/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" -source "board/calao/sbc35_a9g20/Kconfig" -source "board/calao/tny_a9260/Kconfig" -source "board/calao/usb_a9263/Kconfig" source "board/cirrus/edb93xx/Kconfig" -source "board/cm4008/Kconfig" -source "board/cm41xx/Kconfig" source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_fx6/Kconfig" source "board/congatec/cgtqmx6eval/Kconfig" @@ -926,14 +764,8 @@ source "board/creative/xfi3/Kconfig" source "board/davedenx/qong/Kconfig" source "board/denx/m28evk/Kconfig" source "board/denx/m53evk/Kconfig" -source "board/egnite/ethernut5/Kconfig" source "board/embest/mx6boards/Kconfig" -source "board/esd/meesc/Kconfig" -source "board/esd/otc570/Kconfig" source "board/esg/ima3-mx53/Kconfig" -source "board/eukrea/cpu9260/Kconfig" -source "board/eukrea/cpuat91/Kconfig" -source "board/faraday/a320evb/Kconfig" source "board/freescale/ls2085a/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" @@ -977,18 +809,14 @@ source "board/phytec/pcm051/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/pxa255_idp/Kconfig" source "board/raspberrypi/rpi/Kconfig" -source "board/ronetix/pm9261/Kconfig" -source "board/ronetix/pm9263/Kconfig" -source "board/ronetix/pm9g45/Kconfig" +source "board/raspberrypi/rpi_2/Kconfig" source "board/samsung/smdk2410/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" source "board/scb9328/Kconfig" source "board/schulercontrol/sc_sps_1/Kconfig" -source "board/siemens/corvus/Kconfig" source "board/siemens/draco/Kconfig" source "board/siemens/pxm2/Kconfig" source "board/siemens/rut/Kconfig" -source "board/siemens/taurus/Kconfig" source "board/silica/pengwyn/Kconfig" source "board/solidrun/hummingboard/Kconfig" source "board/spear/spear300/Kconfig" @@ -1000,15 +828,12 @@ source "board/st-ericsson/snowball/Kconfig" source "board/st-ericsson/u8500/Kconfig" source "board/st/stv0991/Kconfig" source "board/sunxi/Kconfig" -source "board/syteco/jadecpu/Kconfig" source "board/syteco/zmx25/Kconfig" -source "board/taskit/stamp9g20/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/ti/am335x/Kconfig" source "board/ti/am43xx/Kconfig" source "board/ti/ti814x/Kconfig" source "board/ti/ti816x/Kconfig" -source "board/ti/tnetv107xevm/Kconfig" source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/tqc/tqma6/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ebb7dc34ac..878ae26ce4 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -2,6 +2,27 @@ # SPDX-License-Identifier: GPL-2.0+ # +# Machine directory name. This list is sorted alphanumerically +# by CONFIG_* macro name. +machine-$(CONFIG_ARCH_AT91) += at91 +machine-$(CONFIG_ARCH_DAVINCI) += davinci +machine-$(CONFIG_ARCH_HIGHBANK) += highbank +machine-$(CONFIG_ARCH_KEYSTONE) += keystone +# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD +machine-$(CONFIG_KIRKWOOD) += kirkwood +# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA +machine-$(CONFIG_ARCH_NOMADIK) += nomadik +# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X +machine-$(CONFIG_ORION5X) += orion5x +machine-$(CONFIG_TEGRA) += tegra +machine-$(CONFIG_ARCH_VERSATILE) += versatile + +machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) + +PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) + +libs-y += $(machdirs) + head-y := arch/arm/cpu/$(CPU)/start.o ifeq ($(CONFIG_SPL_BUILD),y) @@ -27,3 +48,6 @@ endif ifneq (,$(filter $(SOC), armada-xp kirkwood)) libs-y += arch/arm/mvebu-common/ endif + +# deprecated +-include $(machdirs)/config.mk diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index 35d8d387bd..6bea3d3a2d 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -1,6 +1 @@ -obj-$(CONFIG_AT91FAMILY) += at91-common/ -obj-$(CONFIG_TEGRA20) += tegra20-common/ -obj-$(CONFIG_TEGRA30) += tegra30-common/ -obj-$(CONFIG_TEGRA114) += tegra114-common/ -obj-$(CONFIG_TEGRA124) += tegra124-common/ -obj-$(CONFIG_TEGRA) += tegra-common/ +obj- += dummy.o diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile index ead2303373..480e130489 100644 --- a/arch/arm/cpu/arm1176/Makefile +++ b/arch/arm/cpu/arm1176/Makefile @@ -12,4 +12,3 @@ extra-y = start.o obj-y = cpu.o obj-$(CONFIG_BCM2835) += bcm2835/ -obj-$(CONFIG_TNETV107X) += tnetv107x/ diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig new file mode 100644 index 0000000000..73cc72b411 --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/Kconfig @@ -0,0 +1,12 @@ +if TARGET_RPI || TARGET_RPI_2 + +config DM + default y + +config DM_SERIAL + default y + +config DM_GPIO + default y + +endif diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile index 0ad36906df..7e5dbe1fde 100644 --- a/arch/arm/cpu/arm1176/bcm2835/Makefile +++ b/arch/arm/cpu/arm1176/bcm2835/Makefile @@ -1,15 +1,7 @@ # -# See file CREDITS for list of people who contributed to this -# project. +# (C) Copyright 2012 Stephen Warren # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0 # obj-y := lowlevel_init.o diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 0704bdde27..ac937bf5b0 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -96,28 +96,6 @@ mmu_disable: mov pc, r2 mmu_disable_phys: -#ifdef CONFIG_DISABLE_TCM - /* - * Disable the TCMs - */ - mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ - cmp r0, #0 - beq skip_tcmdisable - mov r1, #0 - mov r2, #1 - tst r0, r2 - mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ - tst r0, r2, LSL #16 - mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ -skip_tcmdisable: -#endif -#endif - -#ifdef CONFIG_PERIPORT_REMAP - /* Peri port setup */ - ldr r0, =CONFIG_PERIPORT_BASE - orr r0, r0, #CONFIG_PERIPORT_SIZE - mcr p15,0,r0,c15,c2,4 #endif /* diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile deleted file mode 100644 index a4c1edfc71..0000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += aemif.o clock.o init.o mux.o timer.o -obj-y += lowlevel_init.o diff --git a/arch/arm/cpu/arm1176/tnetv107x/aemif.c b/arch/arm/cpu/arm1176/tnetv107x/aemif.c deleted file mode 100644 index a0f57289e9..0000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/aemif.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * TNETV107X: Asynchronous EMIF Configuration - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/mux.h> - -#define ASYNC_EMIF_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE -#define ASYNC_EMIF_CONFIG(cs) (ASYNC_EMIF_BASE+0x10+(cs)*4) -#define ASYNC_EMIF_ONENAND_CONTROL (ASYNC_EMIF_BASE+0x5c) -#define ASYNC_EMIF_NAND_CONTROL (ASYNC_EMIF_BASE+0x60) -#define ASYNC_EMIF_WAITCYCLE_CONFIG (ASYNC_EMIF_BASE+0x4) - -#define CONFIG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) -#define CONFIG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) -#define CONFIG_WR_SETUP(v) (((v) & 0x0f) << 26) -#define CONFIG_WR_STROBE(v) (((v) & 0x3f) << 20) -#define CONFIG_WR_HOLD(v) (((v) & 0x07) << 17) -#define CONFIG_RD_SETUP(v) (((v) & 0x0f) << 13) -#define CONFIG_RD_STROBE(v) (((v) & 0x3f) << 7) -#define CONFIG_RD_HOLD(v) (((v) & 0x07) << 4) -#define CONFIG_TURN_AROUND(v) (((v) & 0x03) << 2) -#define CONFIG_WIDTH(v) (((v) & 0x03) << 0) - -#define NUM_CS 4 - -#define set_config_field(reg, field, val) \ - do { \ - if (val != -1) { \ - reg &= ~CONFIG_##field(0xffffffff); \ - reg |= CONFIG_##field(val); \ - } \ - } while (0) - -void configure_async_emif(int cs, struct async_emif_config *cfg) -{ - unsigned long tmp; - - if (cfg->mode == ASYNC_EMIF_MODE_NAND) { - tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL); - tmp |= (1 << cs); - __raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL); - - } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) { - tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL); - tmp |= (1 << cs); - __raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL); - } - - tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs)); - - set_config_field(tmp, SELECT_STROBE, cfg->select_strobe); - set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait); - set_config_field(tmp, WR_SETUP, cfg->wr_setup); - set_config_field(tmp, WR_STROBE, cfg->wr_strobe); - set_config_field(tmp, WR_HOLD, cfg->wr_hold); - set_config_field(tmp, RD_SETUP, cfg->rd_setup); - set_config_field(tmp, RD_STROBE, cfg->rd_strobe); - set_config_field(tmp, RD_HOLD, cfg->rd_hold); - set_config_field(tmp, TURN_AROUND, cfg->turn_around); - set_config_field(tmp, WIDTH, cfg->width); - - __raw_writel(tmp, ASYNC_EMIF_CONFIG(cs)); -} - -void init_async_emif(int num_cs, struct async_emif_config *config) -{ - int cs; - - clk_enable(TNETV107X_LPSC_AEMIF); - - for (cs = 0; cs < num_cs; cs++) - configure_async_emif(cs, config + cs); -} diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c deleted file mode 100644 index 7ba28d329f..0000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/clock.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * TNETV107X: Clock management APIs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm-generic/errno.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/arch/clock.h> - -#define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE -#define PSC_BASE TNETV107X_PSC_BASE - -#define BIT(x) (1 << (x)) - -#define MAX_PREDIV 64 -#define MAX_POSTDIV 8UL -#define MAX_MULT 512 -#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV) - -/* LPSC registers */ -#define PSC_PTCMD 0x120 -#define PSC_PTSTAT 0x128 -#define PSC_MDSTAT(n) (0x800 + (n) * 4) -#define PSC_MDCTL(n) (0xA00 + (n) * 4) - -#define PSC_MDCTL_LRSTZ BIT(8) - -#define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg))) -#define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg))) - -/* SSPLL registers */ -struct sspll_regs { - u32 modes; - u32 postdiv; - u32 prediv; - u32 mult_factor; - u32 divider_range; - u32 bw_divider; - u32 spr_amount; - u32 spr_rate_div; - u32 diag; -}; - -/* SSPLL base addresses */ -static struct sspll_regs *sspll_regs[] = { - (struct sspll_regs *)(CLOCK_BASE + 0x040), - (struct sspll_regs *)(CLOCK_BASE + 0x080), - (struct sspll_regs *)(CLOCK_BASE + 0x0c0), -}; - -#define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg)) -#define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg)) -#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg)) - - -/* PLL Control Registers */ -struct pllctl_regs { - u32 ctl; /* 00 */ - u32 ocsel; /* 04 */ - u32 secctl; /* 08 */ - u32 __pad0; - u32 mult; /* 10 */ - u32 prediv; /* 14 */ - u32 div1; /* 18 */ - u32 div2; /* 1c */ - u32 div3; /* 20 */ - u32 oscdiv1; /* 24 */ - u32 postdiv; /* 28 */ - u32 bpdiv; /* 2c */ - u32 wakeup; /* 30 */ - u32 __pad1; - u32 cmd; /* 38 */ - u32 stat; /* 3c */ - u32 alnctl; /* 40 */ - u32 dchange; /* 44 */ - u32 cken; /* 48 */ - u32 ckstat; /* 4c */ - u32 systat; /* 50 */ - u32 ckctl; /* 54 */ - u32 __pad2[2]; - u32 div4; /* 60 */ - u32 div5; /* 64 */ - u32 div6; /* 68 */ - u32 div7; /* 6c */ - u32 div8; /* 70 */ -}; - -struct lpsc_map { - int pll, div; -}; - -static struct pllctl_regs *pllctl_regs[] = { - (struct pllctl_regs *)(CLOCK_BASE + 0x700), - (struct pllctl_regs *)(CLOCK_BASE + 0x300), - (struct pllctl_regs *)(CLOCK_BASE + 0x500), -}; - -#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) -#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) -#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) - -#define pllctl_reg_rmw(pll, reg, mask, val) \ - pllctl_reg_write(pll, reg, \ - (pllctl_reg_read(pll, reg) & ~(mask)) | val) - -#define pllctl_reg_setbits(pll, reg, mask) \ - pllctl_reg_rmw(pll, reg, 0, mask) - -#define pllctl_reg_clrbits(pll, reg, mask) \ - pllctl_reg_rmw(pll, reg, mask, 0) - -/* PLLCTL Bits */ -#define PLLCTL_CLKMODE BIT(8) -#define PLLCTL_PLLSELB BIT(7) -#define PLLCTL_PLLENSRC BIT(5) -#define PLLCTL_PLLDIS BIT(4) -#define PLLCTL_PLLRST BIT(3) -#define PLLCTL_PLLPWRDN BIT(1) -#define PLLCTL_PLLEN BIT(0) - -#define PLLDIV_ENABLE BIT(15) - -static int pll_div_offset[] = { -#define div_offset(reg) offsetof(struct pllctl_regs, reg) - div_offset(div1), div_offset(div2), div_offset(div3), - div_offset(div4), div_offset(div5), div_offset(div6), - div_offset(div7), div_offset(div8), -}; - -static unsigned long pll_bypass_mask[] = { 1, 4, 2 }; -static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff }; - -/* Mappings from PLL+DIV to subsystem clocks */ -#define sys_arm1176_clk {SYS_PLL, 0} -#define sys_dsp_clk {SYS_PLL, 1} -#define sys_ddr_clk {SYS_PLL, 2} -#define sys_full_clk {SYS_PLL, 3} -#define sys_lcd_clk {SYS_PLL, 4} -#define sys_vlynq_ref_clk {SYS_PLL, 5} -#define sys_tsc_clk {SYS_PLL, 6} -#define sys_half_clk {SYS_PLL, 7} - -#define eth_clk_5 {ETH_PLL, 0} -#define eth_clk_50 {ETH_PLL, 1} -#define eth_clk_125 {ETH_PLL, 2} -#define eth_clk_250 {ETH_PLL, 3} -#define eth_clk_25 {ETH_PLL, 4} - -#define tdm_clk {TDM_PLL, 0} -#define tdm_extra_clk {TDM_PLL, 1} -#define tdm1_clk {TDM_PLL, 2} - -static const struct lpsc_map lpsc_clk_map[] = { - [TNETV107X_LPSC_ARM] = sys_arm1176_clk, - [TNETV107X_LPSC_GEM] = sys_dsp_clk, - [TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk, - [TNETV107X_LPSC_TPCC] = sys_full_clk, - [TNETV107X_LPSC_TPTC0] = sys_full_clk, - [TNETV107X_LPSC_TPTC1] = sys_full_clk, - [TNETV107X_LPSC_RAM] = sys_full_clk, - [TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk, - [TNETV107X_LPSC_LCD] = sys_lcd_clk, - [TNETV107X_LPSC_ETHSS] = eth_clk_125, - [TNETV107X_LPSC_AEMIF] = sys_full_clk, - [TNETV107X_LPSC_CHIP_CFG] = sys_half_clk, - [TNETV107X_LPSC_TSC] = sys_tsc_clk, - [TNETV107X_LPSC_ROM] = sys_half_clk, - [TNETV107X_LPSC_UART2] = sys_half_clk, - [TNETV107X_LPSC_PKTSEC] = sys_half_clk, - [TNETV107X_LPSC_SECCTL] = sys_half_clk, - [TNETV107X_LPSC_KEYMGR] = sys_half_clk, - [TNETV107X_LPSC_KEYPAD] = sys_half_clk, - [TNETV107X_LPSC_GPIO] = sys_half_clk, - [TNETV107X_LPSC_MDIO] = sys_half_clk, - [TNETV107X_LPSC_SDIO0] = sys_half_clk, - [TNETV107X_LPSC_UART0] = sys_half_clk, - [TNETV107X_LPSC_UART1] = sys_half_clk, - [TNETV107X_LPSC_TIMER0] = sys_half_clk, - [TNETV107X_LPSC_TIMER1] = sys_half_clk, - [TNETV107X_LPSC_WDT_ARM] = sys_half_clk, - [TNETV107X_LPSC_WDT_DSP] = sys_half_clk, - [TNETV107X_LPSC_SSP] = sys_half_clk, - [TNETV107X_LPSC_TDM0] = tdm_clk, - [TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk, - [TNETV107X_LPSC_MCDMA] = sys_half_clk, - [TNETV107X_LPSC_USB0] = sys_half_clk, - [TNETV107X_LPSC_TDM1] = tdm1_clk, - [TNETV107X_LPSC_DEBUGSS] = sys_half_clk, - [TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250, - [TNETV107X_LPSC_SYSTEM] = sys_half_clk, - [TNETV107X_LPSC_IMCOP] = sys_dsp_clk, - [TNETV107X_LPSC_SPARE] = sys_half_clk, - [TNETV107X_LPSC_SDIO1] = sys_half_clk, - [TNETV107X_LPSC_USB1] = sys_half_clk, - [TNETV107X_LPSC_USBSS] = sys_half_clk, - [TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk, - [TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk, -}; - -static const unsigned long pll_ext_freq[] = { - [SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ, - [ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ, - [TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ, -}; - -static unsigned long pll_freq_get(int pll) -{ - unsigned long mult = 1, prediv = 1, postdiv = 1; - unsigned long ref = CONFIG_SYS_INT_OSC_FREQ; - unsigned long ret; - u32 bypass; - - bypass = __raw_readl((u32 *)(CLOCK_BASE)); - if (!(bypass & pll_bypass_mask[pll])) { - mult = sspll_reg_read(pll, mult_factor); - prediv = sspll_reg_read(pll, prediv) + 1; - postdiv = sspll_reg_read(pll, postdiv) + 1; - } - - if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE) - ref = pll_ext_freq[pll]; - - if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN)) - return ref; - - ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256); - ret /= (prediv * postdiv); - - return ret; -} - -static unsigned long __pll_div_freq_get(int pll, unsigned int fpll, - int div) -{ - int divider = 1; - unsigned long divreg; - - divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]); - - if (divreg & PLLDIV_ENABLE) - divider = (divreg & pll_div_mask[pll]) + 1; - - return fpll / divider; -} - -static unsigned long pll_div_freq_get(int pll, int div) -{ - unsigned int fpll = pll_freq_get(pll); - - return __pll_div_freq_get(pll, fpll, div); -} - -static void __pll_div_freq_set(int pll, unsigned int fpll, int div, - unsigned long hz) -{ - int divider = (fpll / hz - 1); - - divider &= pll_div_mask[pll]; - divider |= PLLDIV_ENABLE; - - __raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]); - pllctl_reg_setbits(pll, alnctl, (1 << div)); - pllctl_reg_setbits(pll, dchange, (1 << div)); -} - -static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz) -{ - unsigned int fpll = pll_freq_get(pll); - - __pll_div_freq_set(pll, fpll, div, hz); - - pllctl_reg_write(pll, cmd, 1); - - /* Wait until new divider takes effect */ - while (pllctl_reg_read(pll, stat) & 0x01); - - return __pll_div_freq_get(pll, fpll, div); -} - -unsigned long clk_get_rate(unsigned int clk) -{ - return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div); -} - -unsigned long clk_round_rate(unsigned int clk, unsigned long hz) -{ - unsigned long fpll, divider, pll; - - pll = lpsc_clk_map[clk].pll; - fpll = pll_freq_get(pll); - divider = (fpll / hz - 1); - divider &= pll_div_mask[pll]; - - return fpll / (divider + 1); -} - -int clk_set_rate(unsigned int clk, unsigned long _hz) -{ - unsigned long hz; - - hz = clk_round_rate(clk, _hz); - if (hz != _hz) - return -EINVAL; /* Cannot set to target freq */ - - pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz); - return 0; -} - -void lpsc_control(int mod, unsigned long state, int lrstz) -{ - u32 mdctl; - - mdctl = psc_reg_read(PSC_MDCTL(mod)); - mdctl &= ~0x1f; - mdctl |= state; - - if (lrstz == 0) - mdctl &= ~PSC_MDCTL_LRSTZ; - else if (lrstz == 1) - mdctl |= PSC_MDCTL_LRSTZ; - - psc_reg_write(PSC_MDCTL(mod), mdctl); - - psc_reg_write(PSC_PTCMD, 1); - - /* wait for power domain transition to end */ - while (psc_reg_read(PSC_PTSTAT) & 1); - - /* Wait for module state change */ - while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state); -} - -int lpsc_status(unsigned int id) -{ - return psc_reg_read(PSC_MDSTAT(id)) & 0x1f; -} - -static void init_pll(const struct pll_init_data *data) -{ - unsigned long fpll; - unsigned long best_pre = 0, best_post = 0, best_mult = 0; - unsigned long div, prediv, postdiv, mult; - unsigned long delta, actual; - long best_delta = -1; - int i; - u32 tmp; - - if (data->pll == SYS_PLL) - return; /* cannot reconfigure system pll on the fly */ - - tmp = pllctl_reg_read(data->pll, ctl); - if (data->internal_osc) { - tmp &= ~PLLCTL_CLKMODE; - fpll = CONFIG_SYS_INT_OSC_FREQ; - } else { - tmp |= PLLCTL_CLKMODE; - fpll = pll_ext_freq[data->pll]; - } - pllctl_reg_write(data->pll, ctl, tmp); - - mult = data->pll_freq / fpll; - for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) { - div = (fpll * mult) / data->pll_freq; - if (div < 1 || div > MAX_DIV) - continue; - - for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) { - prediv = div / postdiv; - if (prediv < 1 || prediv > MAX_PREDIV) - continue; - - actual = (fpll / prediv) * (mult / postdiv); - delta = (actual - data->pll_freq); - if (delta < 0) - delta = -delta; - if ((delta < best_delta) || (best_delta == -1)) { - best_delta = delta; - best_mult = mult; - best_pre = prediv; - best_post = postdiv; - if (delta == 0) - goto done; - } - } - } -done: - - if (best_delta == -1) { - printf("pll cannot derive %lu from %lu\n", - data->pll_freq, fpll); - return; - } - - fpll = fpll * best_mult; - fpll /= best_pre * best_post; - - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC); - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN); - - pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST); - - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN); - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS); - - sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8); - sspll_reg_write(data->pll, prediv, best_pre - 1); - sspll_reg_write(data->pll, postdiv, best_post - 1); - - for (i = 0; i < 10; i++) - if (data->div_freq[i]) - __pll_div_freq_set(data->pll, fpll, i, - data->div_freq[i]); - - pllctl_reg_write(data->pll, cmd, 1); - - /* Wait until pll "go" operation completes */ - while (pllctl_reg_read(data->pll, stat) & 0x01); - - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST); - pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN); -} - -void init_plls(int num_pll, struct pll_init_data *config) -{ - int i; - - for (i = 0; i < num_pll; i++) - init_pll(&config[i]); -} diff --git a/arch/arm/cpu/arm1176/tnetv107x/init.c b/arch/arm/cpu/arm1176/tnetv107x/init.c deleted file mode 100644 index d8708267d7..0000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/init.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * TNETV107X: Architecture initialization - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> - -void chip_configuration_unlock(void) -{ - __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0); - __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1); -} - -int arch_cpu_init(void) -{ - icache_enable(); - chip_configuration_unlock(); - - return 0; -} diff --git a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S deleted file mode 100644 index a8bce4784c..0000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * TNETV107X: Low-level pre-relocation initialization - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.globl lowlevel_init -lowlevel_init: - /* nothing for now, maybe needed for more exotic boot modes */ - mov pc, lr diff --git a/arch/arm/cpu/arm1176/tnetv107x/mux.c b/arch/arm/cpu/arm1176/tnetv107x/mux.c deleted file mode 100644 index 310d84dfb4..0000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/mux.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * TNETV107X: Pinmux configuration - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/mux.h> - -#define MUX_MODE_1 0x00 -#define MUX_MODE_2 0x04 -#define MUX_MODE_3 0x0c -#define MUX_MODE_4 0x1c - -#define MUX_DEBUG 0 - -static const struct pin_config pin_table[] = { - /* reg shift mode */ - TNETV107X_MUX_CFG(0, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 20, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 25, MUX_MODE_4), - TNETV107X_MUX_CFG(4, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(4, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(4, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(4, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 20, MUX_MODE_3), - TNETV107X_MUX_CFG(4, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 25, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 20, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 25, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 20, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 25, MUX_MODE_4), - TNETV107X_MUX_CFG(7, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(7, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(7, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(7, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(7, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(7, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(8, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(8, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(8, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(8, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(8, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(8, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(8, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(9, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(9, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(9, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(9, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 20, MUX_MODE_4), - TNETV107X_MUX_CFG(10, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(11, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(11, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(13, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(13, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(13, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(13, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(15, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(15, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(16, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(16, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(17, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 0, MUX_MODE_3), - TNETV107X_MUX_CFG(17, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(17, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(17, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(17, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(17, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(17, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(18, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(18, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(18, 0, MUX_MODE_3), - TNETV107X_MUX_CFG(18, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(18, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(18, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(18, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(18, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(18, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(18, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(18, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(18, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(19, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(20, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(22, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(22, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(22, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(22, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 20, MUX_MODE_3), - TNETV107X_MUX_CFG(22, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 25, MUX_MODE_3), - TNETV107X_MUX_CFG(23, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(23, 0, MUX_MODE_3), - TNETV107X_MUX_CFG(23, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(23, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(23, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(23, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(24, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(24, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(24, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(25, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 0, MUX_MODE_3), - TNETV107X_MUX_CFG(25, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(25, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(25, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(25, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(25, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(25, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(25, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(26, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(26, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(26, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(26, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 25, MUX_MODE_2), -}; - -const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]); - -int mux_select_pin(short index) -{ - const struct pin_config *cfg; - unsigned long mask, mode, reg; - - if (index >= pin_table_size) - return 0; - - cfg = &pin_table[index]; - - mask = 0x1f << cfg->mask_offset; - mode = cfg->mode << cfg->mask_offset; - - reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index)); - reg = (reg & ~mask) | mode; - __raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index)); - - return 1; -} - -int mux_select_pins(const short *pins) -{ - int i, ret = 1; - - for (i = 0; pins[i] >= 0; i++) - ret &= mux_select_pin(pins[i]); - - return ret; -} diff --git a/arch/arm/cpu/arm1176/tnetv107x/timer.c b/arch/arm/cpu/arm1176/tnetv107x/timer.c deleted file mode 100644 index 6e0dd0d2bd..0000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/timer.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * TNETV107X: Timer implementation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> - -struct timer_regs { - u_int32_t pid12; - u_int32_t pad[3]; - u_int32_t tim12; - u_int32_t tim34; - u_int32_t prd12; - u_int32_t prd34; - u_int32_t tcr; - u_int32_t tgcr; - u_int32_t wdtcr; -}; - -#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE) - -#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) -#define TIM_CLK_DIV 16 - -static ulong timestamp; -static ulong lastinc; - -int timer_init(void) -{ - clk_enable(TNETV107X_LPSC_TIMER0); - - lastinc = timestamp = 0; - - /* We are using timer34 in unchained 32-bit mode, full speed */ - __raw_writel(0x0, ®s->tcr); - __raw_writel(0x0, ®s->tgcr); - __raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), ®s->tgcr); - __raw_writel(0x0, ®s->tim34); - __raw_writel(TIMER_LOAD_VAL, ®s->prd34); - __raw_writel(2 << 22, ®s->tcr); - - return 0; -} - -static ulong get_timer_raw(void) -{ - ulong now = __raw_readl(®s->tim34); - - if (now >= lastinc) - timestamp += now - lastinc; - else - timestamp += now + TIMER_LOAD_VAL - lastinc; - - lastinc = now; - - return timestamp; -} - -ulong get_timer(ulong base) -{ - return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base; -} - -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -void __udelay(unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - tmo = CONFIG_SYS_HZ_CLOCK / 1000; - tmo *= usec; - tmo /= (1000 * TIM_CLK_DIV); - - endtime = get_timer_raw() + tmo; - - do { - ulong now = get_timer_raw(); - diff = endtime - now; - } while (diff >= 0); -} - -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/arm/cpu/arm720t/Makefile b/arch/arm/cpu/arm720t/Makefile index 9f61ea2516..243a123378 100644 --- a/arch/arm/cpu/arm720t/Makefile +++ b/arch/arm/cpu/arm720t/Makefile @@ -7,9 +7,3 @@ extra-y = start.o obj-y = interrupts.o cpu.o - -obj-$(CONFIG_TEGRA) += tegra-common/ -obj-$(CONFIG_TEGRA20) += tegra20/ -obj-$(CONFIG_TEGRA30) += tegra30/ -obj-$(CONFIG_TEGRA114) += tegra114/ -obj-$(CONFIG_TEGRA124) += tegra124/ diff --git a/arch/arm/cpu/arm720t/tegra-common/Makefile b/arch/arm/cpu/arm720t/tegra-common/Makefile deleted file mode 100644 index a9c2b675ae..0000000000 --- a/arch/arm/cpu/arm720t/tegra-common/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2010,2011 Nvidia Corporation. -# -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_SPL_BUILD) += spl.o -obj-y += cpu.o diff --git a/arch/arm/cpu/arm720t/tegra114/Makefile b/arch/arm/cpu/arm720t/tegra114/Makefile deleted file mode 100644 index ea3e55ea62..0000000000 --- a/arch/arm/cpu/arm720t/tegra114/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. -# -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see <http://www.gnu.org/licenses/>. -# - -#obj-y += cpu.o t11x.o -obj-y += cpu.o diff --git a/arch/arm/cpu/arm720t/tegra124/Makefile b/arch/arm/cpu/arm720t/tegra124/Makefile deleted file mode 100644 index 61abf45d3d..0000000000 --- a/arch/arm/cpu/arm720t/tegra124/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2013-2014 -# NVIDIA Corporation <www.nvidia.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += cpu.o diff --git a/arch/arm/cpu/arm720t/tegra20/Makefile b/arch/arm/cpu/arm720t/tegra20/Makefile deleted file mode 100644 index 12243fa9be..0000000000 --- a/arch/arm/cpu/arm720t/tegra20/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2010,2011 Nvidia Corporation. -# -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += cpu.o diff --git a/arch/arm/cpu/arm720t/tegra30/Makefile b/arch/arm/cpu/arm720t/tegra30/Makefile deleted file mode 100644 index 6ff4c55213..0000000000 --- a/arch/arm/cpu/arm720t/tegra30/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. -# -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see <http://www.gnu.org/licenses/>. -# - -obj-y += cpu.o diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index a72e5de99e..6582938db0 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -10,9 +10,6 @@ extra-y = start.o obj-y += cpu.o obj-$(CONFIG_USE_IRQ) += interrupts.o -obj-$(if $(filter a320,$(SOC)),y) += a320/ -obj-$(CONFIG_AT91FAMILY) += at91/ obj-$(CONFIG_EP93XX) += ep93xx/ obj-$(CONFIG_IMX) += imx/ -obj-$(CONFIG_KS8695) += ks8695/ obj-$(CONFIG_S3C24X0) += s3c24x0/ diff --git a/arch/arm/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile deleted file mode 100644 index bbdab588c5..0000000000 --- a/arch/arm/cpu/arm920t/a320/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += reset.o -obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/a320/reset.S b/arch/arm/cpu/arm920t/a320/reset.S deleted file mode 100644 index 81f9dc983f..0000000000 --- a/arch/arm/cpu/arm920t/a320/reset.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.global reset_cpu -reset_cpu: - b reset_cpu diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c deleted file mode 100644 index 1ac5b60129..0000000000 --- a/arch/arm/cpu/arm920t/a320/timer.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <div64.h> -#include <asm/io.h> -#include <faraday/ftpmu010.h> -#include <faraday/fttmr010.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define TIMER_CLOCK 32768 -#define TIMER_LOAD_VAL 0xffffffff - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, gd->arch.timer_rate_hz); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= gd->arch.timer_rate_hz; - do_div(usec, 1000000); - - return usec; -} - -int timer_init(void) -{ - struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; - unsigned int cr; - - debug("%s()\n", __func__); - - /* disable timers */ - writel(0, &tmr->cr); - - /* use 32768Hz oscillator for RTC, WDT, TIMER */ - ftpmu010_32768osc_enable(); - - /* setup timer */ - writel(TIMER_LOAD_VAL, &tmr->timer3_load); - writel(TIMER_LOAD_VAL, &tmr->timer3_counter); - writel(0, &tmr->timer3_match1); - writel(0, &tmr->timer3_match2); - - /* we don't want timer to issue interrupts */ - writel(FTTMR010_TM3_MATCH1 | - FTTMR010_TM3_MATCH2 | - FTTMR010_TM3_OVERFLOW, - &tmr->interrupt_mask); - - cr = readl(&tmr->cr); - cr |= FTTMR010_TM3_CLOCK; /* use external clock */ - cr |= FTTMR010_TM3_ENABLE; - writel(cr, &tmr->cr); - - gd->arch.timer_rate_hz = TIMER_CLOCK; - gd->arch.tbu = gd->arch.tbl = 0; - - return 0; -} - -/* - * Get the current 64 bit timer tick count - */ -unsigned long long get_ticks(void) -{ - struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; - ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter); - - /* increment tbu if tbl has rolled over */ - if (now < gd->arch.tbl) - gd->arch.tbu++; - gd->arch.tbl = now; - return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; -} - -void __udelay(unsigned long usec) -{ - unsigned long long start; - ulong tmo; - - start = get_ticks(); /* get current timestamp */ - tmo = usec_to_tick(usec); /* convert usecs to ticks */ - while ((get_ticks() - start) < tmo) - ; /* loop till time has passed */ -} - -/* - * get_timer(base) can be used to check for timeouts or - * to measure elasped time relative to an event: - * - * ulong start_time = get_timer(0) sets start_time to the current - * time value. - * get_timer(start_time) returns the time elapsed since then. - * - * The time is used in CONFIG_SYS_HZ units! - */ -ulong get_timer(ulong base) -{ - return tick_to_time(get_ticks()) - base; -} - -/* - * Return the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return gd->arch.timer_rate_hz; -} diff --git a/arch/arm/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile deleted file mode 100644 index 400aa89e99..0000000000 --- a/arch/arm/cpu/arm920t/ks8695/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = lowlevel_init.o -obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S deleted file mode 100644 index a2a07f2f23..0000000000 --- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S +++ /dev/null @@ -1,189 +0,0 @@ -/* - * lowlevel_init.S - basic hardware initialization for the KS8695 CPU - * - * Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> -#include <asm/arch/platform.h> - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - -/* - ************************************************************************* - * - * Handy dandy macros - * - ************************************************************************* - */ - -/* Delay a bit */ -.macro DELAY_FOR cycles, reg0 - ldr \reg0, =\cycles - subs \reg0, \reg0, #1 - subne pc, pc, #0xc -.endm - -/* - ************************************************************************* - * - * Some local storage. - * - ************************************************************************* - */ - -/* Should we boot with an interactive console or not */ -.globl serial_console - -/* - ************************************************************************* - * - * Raw hardware initialization code. The important thing is to get - * SDRAM setup and running. We do some other basic things here too, - * like getting the PLL set for high speed, and init the LEDs. - * - ************************************************************************* - */ - -.globl lowlevel_init -lowlevel_init: - -#if DEBUG - /* - * enable UART for early debug trace - */ - ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR) - mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE) - str r2, [r1] - ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL) - mov r2, #KS8695_UART_LINEC_WLEN8 - str r2, [r1] /* 8 data bits, no parity, 1 stop */ - ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING) - mov r2, #0x41 - str r2, [r1] /* write 'A' */ -#endif -#if DEBUG - ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING) - mov r2, #0x42 - str r2, [r1] -#endif - - /* - * remap the memory and flash regions. we want to end up with - * ram from address 0, and flash at 32MB. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0) - ldr r2, =0xbfc00040 - str r2, [r1] /* large flash map */ - ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */ -highflash: - ldr r2, =0x8fe00040 - str r2, [r1] /* remap flash range */ - - /* - * remap the second select region to the 4MB immediately after - * the first region. This way if you have a larger flash (say 8Mb) - * then you can have it all mapped nicely. Has no effect if you - * only have a 4Mb or smaller flash. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1) - ldr r2, =0x9fe40040 - str r2, [r1] /* remap flash2 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL) - ldr r2, =0x30000005 - str r2, [r1] /* enable both flash selects */ - -#ifdef CONFIG_CM41xx - /* - * map the second flash chip, using the external IO lines. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0) - ldr r2, =0xafe80b6d - str r2, [r1] /* remap io0 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1) - ldr r2, =0xbfec0b6d - str r2, [r1] /* remap io1 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL) - ldr r2, =0x30050005 - str r2, [r1] /* enable second flash */ -#endif - - /* - * before relocating, we have to setup RAM timing - */ - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0) -#if (PHYS_SDRAM_1_SIZE == 0x02000000) - ldr r2, =0x7fc0000e /* 32MB */ -#else - ldr r2, =0x3fc0000e /* 16MB */ -#endif - str r2, [r1] /* configure sdram bank0 setup */ - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1) - mov r2, #0 - str r2, [r1] /* configure sdram bank1 setup */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL) - ldr r2, =0x0000000a - str r2, [r1] /* set RAS/CAS timing */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER) - ldr r2, =0x00030000 - str r2, [r1] /* send NOP command */ - DELAY_FOR 0x100, r0 - ldr r2, =0x00010000 - str r2, [r1] /* send PRECHARGE-ALL */ - DELAY_FOR 0x100, r0 - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH) - ldr r2, =0x00000020 - str r2, [r1] /* set for fast refresh */ - DELAY_FOR 0x100, r0 - ldr r2, =0x00000190 - str r2, [r1] /* set normal refresh timing */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER) - ldr r2, =0x00020033 - str r2, [r1] /* send mode command */ - DELAY_FOR 0x100, r0 - ldr r2, =0x01f00000 - str r2, [r1] /* enable sdram fifos */ - - /* - * set pll to top speed - */ - ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK) - mov r2, #0 - str r2, [r1] /* set pll clock to 166MHz */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0) - ldr r2, [r1] /* Get switch ctrl0 register */ - and r2, r2, #0x0fc00000 /* Mask out LED control bits */ - orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */ - str r2, [r1] - -#ifdef CONFIG_CM4008 - ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE) - ldr r2, =0x0000fe30 - str r2, [r1] /* enable LED's as outputs */ - ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA) - ldr r2, =0x0000fe20 - str r2, [r1] /* turn on power LED */ -#endif -#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx) - ldr r2, [r1] /* get current GPIO input data */ - tst r2, #0x8 /* check if "erase" depressed */ - beq nobutton - mov r2, #0 /* be quiet on boot, no console */ - ldr r1, =serial_console - str r2, [r1] -nobutton: -#endif - - add lr, lr, #0x02000000 /* flash is now mapped high */ - add ip, ip, #0x02000000 /* this is a hack */ - mov pc, lr /* all done, return */ - -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/arch/arm/cpu/arm920t/ks8695/timer.c b/arch/arm/cpu/arm920t/ks8695/timer.c deleted file mode 100644 index 23db5572de..0000000000 --- a/arch/arm/cpu/arm920t/ks8695/timer.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/platform.h> - -/* - * Initial timer set constants. Nothing complicated, just set for a 1ms - * tick. - */ -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1) -#define TIMER_COUNT (TIMER_INTERVAL / 2) -#define TIMER_PULSE TIMER_COUNT - -/* - * Handy KS8695 register access functions. - */ -#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a))) -#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v) - -ulong timer_ticks; - -int timer_init (void) -{ - /* Set the hadware timer for 1ms */ - ks8695_write(KS8695_TIMER1, TIMER_COUNT); - ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE); - ks8695_write(KS8695_TIMER_CTRL, 0x2); - timer_ticks = 0; - - return 0; -} - -ulong get_timer_masked(void) -{ - /* Check for timer wrap */ - if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) { - /* Clear interrupt condition */ - ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1); - timer_ticks++; - } - return timer_ticks; -} - -ulong get_timer(ulong base) -{ - return (get_timer_masked() - base); -} - -void __udelay(ulong usec) -{ - ulong start = get_timer_masked(); - ulong end; - - /* Only 1ms resolution :-( */ - end = usec / 1000; - while (get_timer(start) < end) - ; -} - -void reset_cpu (ulong ignored) -{ - ulong tc; - - /* Set timer0 to watchdog, and let it timeout */ - tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2; - ks8695_write(KS8695_TIMER_CTRL, tc); - ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff)); - ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1)); - - /* Should only wait here till watchdog resets */ - for (;;) - ; -} diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index adcea9f683..63fa159db6 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -15,16 +15,8 @@ endif endif obj-$(CONFIG_ARMADA100) += armada100/ -obj-$(CONFIG_AT91FAMILY) += at91/ -obj-$(CONFIG_ARCH_DAVINCI) += davinci/ -obj-$(CONFIG_KIRKWOOD) += kirkwood/ obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/ -obj-$(CONFIG_MB86R0x) += mb86r0x/ obj-$(CONFIG_MX25) += mx25/ obj-$(CONFIG_MX27) += mx27/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/ -obj-$(CONFIG_ARCH_NOMADIK) += nomadik/ -obj-$(CONFIG_ORION5X) += orion5x/ -obj-$(CONFIG_PANTHEON) += pantheon/ obj-$(if $(filter spear,$(SOC)),y) += spear/ -obj-$(CONFIG_ARCH_VERSATILE) += versatile/ diff --git a/arch/arm/cpu/arm926ejs/at91/config.mk b/arch/arm/cpu/arm926ejs/at91/config.mk deleted file mode 100644 index 370630d4de..0000000000 --- a/arch/arm/cpu/arm926ejs/at91/config.mk +++ /dev/null @@ -1,2 +0,0 @@ -PF_CPPFLAGS_TUNE := $(call cc-option,-mtune=arm926ejs,) -PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_TUNE) diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile deleted file mode 100644 index 365892c413..0000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = clock.o reset.o timer.o diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c deleted file mode 100644 index 1f6f66eba2..0000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser <weisserm@arcor.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -/* - * Get the peripheral bus frequency depending on pll pin settings - */ -ulong get_bus_freq(ulong dummy) -{ - struct mb86r0x_crg * crg = (struct mb86r0x_crg *) - MB86R0x_CRG_BASE; - uint32_t pllmode; - - pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE; - - if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20) - return 40000000; - - return 41164767; -} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c deleted file mode 100644 index 7bd77ff202..0000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser <weisserm@arcor.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -/* - * Reset the cpu by setting software reset request bit - */ -void reset_cpu(ulong ignored) -{ - struct mb86r0x_crg * crg = (struct mb86r0x_crg *) - MB86R0x_CRG_BASE; - - writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr); - while (1) - /* NOP */; - /* Never reached */ -} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c deleted file mode 100644 index bb078196d0..0000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian@popies.net> - * Lead Tech Design <www.leadtechdesign.com> - * - * (C) Copyright 2010 - * Matthias Weisser, Graf-Syteco <weisserm@arcor.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <div64.h> -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -#define TIMER_LOAD_VAL 0xffffffff -#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256) - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, TIMER_FREQ); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= TIMER_FREQ; - do_div(usec, 1000000); - - return usec; -} - -/* nothing really to do with interrupts, just starts up a counter. */ -int timer_init(void) -{ - struct mb86r0x_timer * timer = (struct mb86r0x_timer *) - MB86R0x_TIMER_BASE; - ulong ctrl = readl(&timer->control); - - writel(TIMER_LOAD_VAL, &timer->load); - - ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S | - MB86R0x_TIMER_SIZE_32; - - writel(ctrl, &timer->control); - - /* capture current value time */ - lastdec = readl(&timer->value); - timestamp = 0; /* start "advancing" time stamp from 0 */ - - return 0; -} - -/* - * timer without interrupts - */ -unsigned long long get_ticks(void) -{ - struct mb86r0x_timer * timer = (struct mb86r0x_timer *) - MB86R0x_TIMER_BASE; - ulong now = readl(&timer->value); - - if (now <= lastdec) { - /* normal mode (non roll) */ - /* move stamp forward with absolut diff ticks */ - timestamp += lastdec - now; - } else { - /* we have rollover of incrementer */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - return timestamp; -} - -ulong get_timer_masked(void) -{ - return tick_to_time(get_ticks()); -} - -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = usec_to_tick(usec); - tmp = get_ticks(); /* get current timestamp */ - - while ((get_ticks() - tmp) < tmo) /* loop till event */ - /*NOP*/; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - ulong tbclk; - - tbclk = TIMER_FREQ; - return tbclk; -} diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile deleted file mode 100644 index 988341f8fb..0000000000 --- a/arch/arm/cpu/arm926ejs/pantheon/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2011 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Lei Wen <leiwen@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = cpu.o timer.o dram.o diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c deleted file mode 100644 index 4e2a177c0d..0000000000 --- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/pantheon.h> - -#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1)) -#define SET_MRVL_ID (1<<8) -#define L2C_RAM_SEL (1<<4) - -int arch_cpu_init(void) -{ - u32 val; - struct panthcpu_registers *cpuregs = - (struct panthcpu_registers*) PANTHEON_CPU_BASE; - - struct panthapb_registers *apbclkres = - (struct panthapb_registers*) PANTHEON_APBC_BASE; - - struct panthmpmu_registers *mpmu = - (struct panthmpmu_registers*) PANTHEON_MPMU_BASE; - - struct panthapmu_registers *apmu = - (struct panthapmu_registers *) PANTHEON_APMU_BASE; - - /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */ - val = readl(&cpuregs->cpu_conf); - val = val | SET_MRVL_ID; - writel(val, &cpuregs->cpu_conf); - - /* Turn on clock gating (PMUM_CCGR) */ - writel(0xFFFFFFFF, &mpmu->ccgr); - - /* Turn on clock gating (PMUM_ACGR) */ - writel(0xFFFFFFFF, &mpmu->acgr); - - /* Turn on uart2 clock */ - writel(UARTCLK14745KHZ, &apbclkres->uart0); - - /* Enable GPIO clock */ - writel(APBC_APBCLK, &apbclkres->gpio); - -#ifdef CONFIG_I2C_MV - /* Enable I2C clock */ - writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi); - writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi); -#endif - -#ifdef CONFIG_MV_SDHCI - /* Enable mmc clock */ - writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST, - &apmu->sd1); - writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST, - &apmu->sd3); -#endif - - icache_enable(); - - return 0; -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - u32 id; - struct panthcpu_registers *cpuregs = - (struct panthcpu_registers*) PANTHEON_CPU_BASE; - - id = readl(&cpuregs->chip_id); - printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10)); - return 0; -} -#endif - -#ifdef CONFIG_I2C_MV -void i2c_clk_enable(void) -{ -} -#endif diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c deleted file mode 100644 index f77e3d0ab5..0000000000 --- a/arch/arm/cpu/arm926ejs/pantheon/dram.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com>, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/pantheon.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Pantheon DRAM controller supports upto 8 banks - * for chip select 0 and 1 - */ - -/* - * DDR Memory Control Registers - * Refer Datasheet 4.4 - */ -struct panthddr_map_registers { - u32 cs; /* Memory Address Map Register -CS */ - u32 pad[3]; -}; - -struct panthddr_registers { - u8 pad[0x100 - 0x000]; - struct panthddr_map_registers mmap[2]; -}; - -/* - * panth_sdram_base - reads SDRAM Base Address Register - */ -u32 panth_sdram_base(int chip_sel) -{ - struct panthddr_registers *ddr_regs = - (struct panthddr_registers *)PANTHEON_DRAM_BASE; - u32 result = 0; - u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); - - if (!CS_valid) - return 0; - - result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000; - return result; -} - -/* - * panth_sdram_size - reads SDRAM size - */ -u32 panth_sdram_size(int chip_sel) -{ - struct panthddr_registers *ddr_regs = - (struct panthddr_registers *)PANTHEON_DRAM_BASE; - u32 result = 0; - u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); - - if (!CS_valid) - return 0; - - result = readl(&ddr_regs->mmap[chip_sel].cs); - result = (result >> 16) & 0xF; - if (result < 0x7) { - printf("Unknown DRAM Size\n"); - return -1; - } else { - return ((0x8 << (result - 0x7)) * 1024 * 1024); - } -} - -#ifndef CONFIG_SYS_BOARD_DRAM_INIT -int dram_init(void) -{ - int i; - - gd->ram_size = 0; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = panth_sdram_base(i); - gd->bd->bi_dram[i].size = panth_sdram_size(i); - /* - * It is assumed that all memory banks are consecutive - * and without gaps. - * If the gap is found, ram_size will be reported for - * consecutive memory only - */ - if (gd->bd->bi_dram[i].start != gd->ram_size) - break; - - gd->ram_size += gd->bd->bi_dram[i].size; - - } - - for (; i < CONFIG_NR_DRAM_BANKS; i++) { - /* - * If above loop terminated prematurely, we need to set - * remaining banks' start address & size as 0. Otherwise other - * u-boot functions and Linux kernel gets wrong values which - * could result in crash - */ - gd->bd->bi_dram[i].start = 0; - gd->bd->bi_dram[i].size = 0; - } - return 0; -} - -/* - * If this function is not defined here, - * board.c alters dram bank zero configuration defined above. - */ -void dram_init_banksize(void) -{ - dram_init(); -} -#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c deleted file mode 100644 index 6382d3b0cf..0000000000 --- a/arch/arm/cpu/arm926ejs/pantheon/timer.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/pantheon.h> - -/* - * Timer registers - * Refer 6.2.9 in Datasheet - */ -struct panthtmr_registers { - u32 clk_ctrl; /* Timer clk control reg */ - u32 match[9]; /* Timer match registers */ - u32 count[3]; /* Timer count registers */ - u32 status[3]; - u32 ie[3]; - u32 preload[3]; /* Timer preload value */ - u32 preload_ctrl[3]; - u32 wdt_match_en; - u32 wdt_match_r; - u32 wdt_val; - u32 wdt_sts; - u32 icr[3]; - u32 wdt_icr; - u32 cer; /* Timer count enable reg */ - u32 cmr; - u32 ilr[3]; - u32 wcr; - u32 wfar; - u32 wsar; - u32 cvwr[3]; -}; - -#define TIMER 0 /* Use TIMER 0 */ -/* Each timer has 3 match registers */ -#define MATCH_CMP(x) ((3 * TIMER) + x) -#define TIMER_LOAD_VAL 0xffffffff -#define COUNT_RD_REQ 0x1 - -DECLARE_GLOBAL_DATA_PTR; -/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */ - -/* - * For preventing risk of instability in reading counter value, - * first set read request to register cvwr and then read same - * register after it captures counter value. - */ -ulong read_timer(void) -{ - struct panthtmr_registers *panthtimers = - (struct panthtmr_registers *) PANTHEON_TIMER_BASE; - volatile int loop=100; - ulong val; - - writel(COUNT_RD_REQ, &panthtimers->cvwr); - while (loop--) - val = readl(&panthtimers->cvwr); - - /* - * This stop gcc complain and prevent loop mistake init to 0 - */ - val = readl(&panthtimers->cvwr); - - return val; -} - -ulong get_timer_masked(void) -{ - ulong now = read_timer(); - - if (now >= gd->arch.tbl) { - /* normal mode */ - gd->arch.tbu += now - gd->arch.tbl; - } else { - /* we have an overflow ... */ - gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl; - } - gd->arch.tbl = now; - - return gd->arch.tbu; -} - -ulong get_timer(ulong base) -{ - return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - - base); -} - -void __udelay(unsigned long usec) -{ - ulong delayticks; - ulong endtime; - - delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000)); - endtime = get_timer_masked() + delayticks; - - while (get_timer_masked() < endtime) - ; -} - -/* - * init the Timer - */ -int timer_init(void) -{ - struct panthapb_registers *apb1clkres = - (struct panthapb_registers *) PANTHEON_APBC_BASE; - struct panthtmr_registers *panthtimers = - (struct panthtmr_registers *) PANTHEON_TIMER_BASE; - - /* Enable Timer clock at 3.25 MHZ */ - writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers); - - /* load value into timer */ - writel(0x0, &panthtimers->clk_ctrl); - /* Use Timer 0 Match Resiger 0 */ - writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]); - /* Preload value is 0 */ - writel(0x0, &panthtimers->preload[TIMER]); - /* Enable match comparator 0 for Timer 0 */ - writel(0x1, &panthtimers->preload_ctrl[TIMER]); - - /* Enable timer 0 */ - writel(0x1, &panthtimers->cer); - /* init the gd->arch.tbu and gd->arch.tbl value */ - gd->arch.tbl = read_timer(); - gd->arch.tbu = 0; - - return 0; -} - -#define MPMU_APRR_WDTR (1<<4) -#define TMR_WFAR 0xbaba /* WDT Register First key */ -#define TMP_WSAR 0xeb10 /* WDT Register Second key */ - -/* - * This function uses internal Watchdog Timer - * based reset mechanism. - * Steps to write watchdog registers (protected access) - * 1. Write key value to TMR_WFAR reg. - * 2. Write key value to TMP_WSAR reg. - * 3. Perform write operation. - */ -void reset_cpu (unsigned long ignored) -{ - struct panthmpmu_registers *mpmu = - (struct panthmpmu_registers *) PANTHEON_MPMU_BASE; - struct panthtmr_registers *panthtimers = - (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE; - u32 val; - - /* negate hardware reset to the WDT after system reset */ - val = readl(&mpmu->aprr); - val = val | MPMU_APRR_WDTR; - writel(val, &mpmu->aprr); - - /* reset/enable WDT clock */ - writel(APBC_APBCLK, &mpmu->wdtpcr); - - /* clear previous WDT status */ - writel(TMR_WFAR, &panthtimers->wfar); - writel(TMP_WSAR, &panthtimers->wsar); - writel(0, &panthtimers->wdt_sts); - - /* set match counter */ - writel(TMR_WFAR, &panthtimers->wfar); - writel(TMP_WSAR, &panthtimers->wsar); - writel(0xf, &panthtimers->wdt_match_r); - - /* enable WDT reset */ - writel(TMR_WFAR, &panthtimers->wfar); - writel(TMP_WSAR, &panthtimers->wsar); - writel(0x3, &panthtimers->wdt_match_en); - - /*enable functional WDT clock */ - writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - return (ulong)CONFIG_SYS_HZ; -} diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 409e6f5651..b228ed6a2e 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -32,7 +32,6 @@ obj-$(CONFIG_IPROC) += iproc-common/ obj-$(CONFIG_KONA) += kona-common/ obj-$(CONFIG_OMAP_COMMON) += omap-common/ obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o -obj-$(CONFIG_TEGRA) += tegra-common/ ifneq (,$(filter s5pc1xx exynos,$(SOC))) obj-y += s5p-common/ @@ -40,13 +39,11 @@ endif obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/ -obj-$(CONFIG_AT91FAMILY) += at91/ +obj-$(CONFIG_BCM2835) += bcm2835/ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/ obj-$(CONFIG_ARCH_EXYNOS) += exynos/ -obj-$(CONFIG_ARCH_HIGHBANK) += highbank/ -obj-$(CONFIG_ARCH_KEYSTONE) += keystone/ obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/ obj-$(if $(filter mx5,$(SOC)),y) += mx5/ obj-$(CONFIG_MX6) += mx6/ @@ -58,7 +55,6 @@ obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/ obj-$(CONFIG_SOCFPGA) += socfpga/ obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ -obj-$(CONFIG_TEGRA20) += tegra20/ obj-$(CONFIG_U8500) += u8500/ obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/ obj-$(CONFIG_VF610) += vf610/ diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index 31188c85bc..529a119514 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -118,4 +118,7 @@ void enable_basic_clocks(void) /* Select the Master osc clk as Timer2 clock source */ writel(0x1, &cmdpll->clktimer2clk); + + /* For OPP100 the mac clock should be /5. */ + writel(0x4, &cmdpll->clkselmacclk); } diff --git a/arch/arm/cpu/armv7/at91/config.mk b/arch/arm/cpu/armv7/at91/config.mk deleted file mode 100644 index db6030880f..0000000000 --- a/arch/arm/cpu/armv7/at91/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2014, Andreas Bießmann <andreas.devel@googlemail.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# -ifndef CONFIG_SPL_BUILD -ALL-y += u-boot.img -endif diff --git a/arch/arm/cpu/armv7/bcm2835/Makefile b/arch/arm/cpu/armv7/bcm2835/Makefile new file mode 100644 index 0000000000..ed1ee4753d --- /dev/null +++ b/arch/arm/cpu/armv7/bcm2835/Makefile @@ -0,0 +1,13 @@ +# +# (C) Copyright 2012 Stephen Warren +# +# SPDX-License-Identifier: GPL-2.0+ +# + +src_dir := ../../arm1176/bcm2835/ + +obj-y := +obj-y += $(src_dir)/init.o +obj-y += $(src_dir)/reset.o +obj-y += $(src_dir)/timer.o +obj-y += $(src_dir)/mbox.o diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 7fcb5d2094..eb86a7fe7d 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -6,7 +6,7 @@ choice config TARGET_SMDKV310 select SUPPORT_SPL bool "Exynos4210 SMDKV310 board" - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_TRATS bool "Exynos4210 Trats board" @@ -33,38 +33,59 @@ config TARGET_ARNDALE select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select SUPPORT_SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_SMDK5250 bool "SMDK5250 board" select SUPPORT_SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_SNOW bool "Snow board" select SUPPORT_SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_SMDK5420 bool "SMDK5420 board" select SUPPORT_SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_PEACH_PI bool "Peach Pi board" select SUPPORT_SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_PEACH_PIT bool "Peach Pit board" select SUPPORT_SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL endchoice config SYS_SOC default "exynos" +config DM + default y + +config DM_SERIAL + default y + +config DM_SPI + default y + +config DM_SPI_FLASH + default y + +config DM_GPIO + default y + +config SYS_MALLOC_F + default y + +config SYS_MALLOC_F_LEN + default 0x400 + source "board/samsung/smdkv310/Kconfig" source "board/samsung/trats/Kconfig" source "board/samsung/universal_c210/Kconfig" diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index b31c13b14b..c6455c2f3c 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -20,42 +20,84 @@ * positions of the peripheral clocks of the src and div registers */ struct clk_bit_info { + enum periph_id id; + int32_t src_mask; + int32_t div_mask; + int32_t prediv_mask; int8_t src_bit; int8_t div_bit; int8_t prediv_bit; }; -/* src_bit div_bit prediv_bit */ -static struct clk_bit_info clk_bit_info[] = { - {0, 0, -1}, - {4, 4, -1}, - {8, 8, -1}, - {12, 12, -1}, - {0, 0, 8}, - {4, 16, 24}, - {8, 0, 8}, - {12, 16, 24}, - {-1, -1, -1}, - {16, 0, 8}, - {20, 16, 24}, - {24, 0, 8}, - {0, 0, 4}, - {4, 12, 16}, - {-1, -1, -1}, - {-1, -1, -1}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {24, 0, -1}, - {24, 0, -1}, - {24, 0, -1}, - {24, 0, -1}, - {24, 0, -1}, +static struct clk_bit_info exynos5_bit_info[] = { + /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */ + {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1}, + {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1}, + {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1}, + {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1}, + {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0}, + {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0}, + {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0}, + {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0}, + {PERIPH_ID_I2C4, -1, 0x7, 0x7, -1, 24, 0}, + {PERIPH_ID_I2C5, -1, 0x7, 0x7, -1, 24, 0}, + {PERIPH_ID_I2C6, -1, 0x7, 0x7, -1, 24, 0}, + {PERIPH_ID_I2C7, -1, 0x7, 0x7, -1, 24, 0}, + {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 16, 0, 8}, + {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 20, 16, 24}, + {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 24, 0, 8}, + {PERIPH_ID_SDMMC0, 0xf, 0xf, 0xff, 0, 0, 8}, + {PERIPH_ID_SDMMC1, 0xf, 0xf, 0xff, 4, 16, 24}, + {PERIPH_ID_SDMMC2, 0xf, 0xf, 0xff, 8, 0, 8}, + {PERIPH_ID_SDMMC3, 0xf, 0xf, 0xff, 12, 16, 24}, + {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4}, + {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16}, + {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 0, 0, 4}, + {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 4, 12, 16}, + {PERIPH_ID_SDMMC4, 0xf, 0xf, 0xff, 16, 0, 8}, + {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 0, -1}, + {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 0, -1}, + {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 0, -1}, + {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 0, -1}, + {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 0, -1}, + + {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1}, +}; + +static struct clk_bit_info exynos542x_bit_info[] = { + /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */ + {PERIPH_ID_UART0, 0xf, 0xf, -1, 4, 8, -1}, + {PERIPH_ID_UART1, 0xf, 0xf, -1, 8, 12, -1}, + {PERIPH_ID_UART2, 0xf, 0xf, -1, 12, 16, -1}, + {PERIPH_ID_UART3, 0xf, 0xf, -1, 16, 20, -1}, + {PERIPH_ID_I2C0, -1, 0x3f, -1, -1, 8, -1}, + {PERIPH_ID_I2C1, -1, 0x3f, -1, -1, 8, -1}, + {PERIPH_ID_I2C2, -1, 0x3f, -1, -1, 8, -1}, + {PERIPH_ID_I2C3, -1, 0x3f, -1, -1, 8, -1}, + {PERIPH_ID_I2C4, -1, 0x3f, -1, -1, 8, -1}, + {PERIPH_ID_I2C5, -1, 0x3f, -1, -1, 8, -1}, + {PERIPH_ID_I2C6, -1, 0x3f, -1, -1, 8, -1}, + {PERIPH_ID_I2C7, -1, 0x3f, -1, -1, 8, -1}, + {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 20, 20, 8}, + {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 24, 24, 16}, + {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 28, 28, 24}, + {PERIPH_ID_SDMMC0, 0x7, 0x3ff, -1, 8, 0, -1}, + {PERIPH_ID_SDMMC1, 0x7, 0x3ff, -1, 12, 10, -1}, + {PERIPH_ID_SDMMC2, 0x7, 0x3ff, -1, 16, 20, -1}, + {PERIPH_ID_I2C8, -1, 0x3f, -1, -1, 8, -1}, + {PERIPH_ID_I2C9, -1, 0x3f, -1, -1, 8, -1}, + {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4}, + {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16}, + {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 12, 16, 0}, + {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 16, 20, 8}, + {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 28, -1}, + {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 28, -1}, + {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 28, -1}, + {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 28, -1}, + {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 28, -1}, + {PERIPH_ID_I2C10, -1, 0x3f, -1, -1, 8, -1}, + + {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1}, }; /* Epll Clock division values to achive different frequency output */ @@ -260,11 +302,72 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return fout; } +/* exynos542x: return pll clock frequency */ +static unsigned long exynos542x_get_pll_clk(int pllreg) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long r, k = 0; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + case BPLL: + r = readl(&clk->bpll_con0); + break; + case RPLL: + r = readl(&clk->rpll_con0); + k = readl(&clk->rpll_con1); + break; + case SPLL: + r = readl(&clk->spll_con0); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + return exynos_get_pll_clk(pllreg, r, k); +} + +static struct clk_bit_info *get_clk_bit_info(int peripheral) +{ + int i; + struct clk_bit_info *info; + + if (proid_is_exynos5420() || proid_is_exynos5800()) + info = exynos542x_bit_info; + else + info = exynos5_bit_info; + + for (i = 0; info[i].id != PERIPH_ID_NONE; i++) { + if (info[i].id == peripheral) + break; + } + + if (info[i].id == PERIPH_ID_NONE) + debug("ERROR: Peripheral ID %d not found\n", peripheral); + + return &info[i]; +} + static unsigned long exynos5_get_periph_rate(int peripheral) { - struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; - unsigned long sclk, sub_clk; - unsigned int src, div, sub_div; + struct clk_bit_info *bit_info = get_clk_bit_info(peripheral); + unsigned long sclk = 0; + unsigned int src = 0, div = 0, sub_div = 0; struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); @@ -286,27 +389,30 @@ static unsigned long exynos5_get_periph_rate(int peripheral) break; case PERIPH_ID_I2S0: src = readl(&clk->src_mau); - div = readl(&clk->div_mau); + div = sub_div = readl(&clk->div_mau); case PERIPH_ID_SPI0: case PERIPH_ID_SPI1: src = readl(&clk->src_peric1); - div = readl(&clk->div_peric1); + div = sub_div = readl(&clk->div_peric1); break; case PERIPH_ID_SPI2: src = readl(&clk->src_peric1); - div = readl(&clk->div_peric2); + div = sub_div = readl(&clk->div_peric2); break; case PERIPH_ID_SPI3: case PERIPH_ID_SPI4: src = readl(&clk->sclk_src_isp); - div = readl(&clk->sclk_div_isp); + div = sub_div = readl(&clk->sclk_div_isp); break; case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC1: + src = readl(&clk->src_fsys); + div = sub_div = readl(&clk->div_fsys1); + break; case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC3: src = readl(&clk->src_fsys); - div = readl(&clk->div_fsys1); + div = sub_div = readl(&clk->div_fsys2); break; case PERIPH_ID_I2C0: case PERIPH_ID_I2C1: @@ -316,18 +422,17 @@ static unsigned long exynos5_get_periph_rate(int peripheral) case PERIPH_ID_I2C5: case PERIPH_ID_I2C6: case PERIPH_ID_I2C7: - sclk = exynos5_get_pll_clk(MPLL); - sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit) - & 0x7) + 1; - div = ((readl(&clk->div_top0) >> bit_info->prediv_bit) - & 0x7) + 1; - return (sclk / sub_div) / div; + src = EXYNOS_SRC_MPLL; + div = readl(&clk->div_top0); + sub_div = readl(&clk->div_top1); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; }; - src = (src >> bit_info->src_bit) & 0xf; + if (bit_info->src_bit >= 0) + src = (src >> bit_info->src_bit) & bit_info->src_mask; switch (src) { case EXYNOS_SRC_MPLL: @@ -340,68 +445,126 @@ static unsigned long exynos5_get_periph_rate(int peripheral) sclk = exynos5_get_pll_clk(VPLL); break; default: + debug("%s: EXYNOS_SRC %d not supported\n", __func__, src); return 0; } - /* Ratio clock division for this peripheral */ - sub_div = (div >> bit_info->div_bit) & 0xf; - sub_clk = sclk / (sub_div + 1); - - /* Pre-ratio clock division for SDMMC0 and 2 */ - if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { - div = (div >> bit_info->prediv_bit) & 0xff; - return sub_clk / (div + 1); - } + /* Clock divider ratio for this peripheral */ + if (bit_info->div_bit >= 0) + div = (div >> bit_info->div_bit) & bit_info->div_mask; - return sub_clk; -} + /* Clock pre-divider ratio for this peripheral */ + if (bit_info->prediv_bit >= 0) + sub_div = (sub_div >> bit_info->prediv_bit) + & bit_info->prediv_mask; -unsigned long clock_get_periph_rate(int peripheral) -{ - if (cpu_is_exynos5()) - return exynos5_get_periph_rate(peripheral); - else - return 0; + /* Calculate and return required clock rate */ + return (sclk / (div + 1)) / (sub_div + 1); } -/* exynos5420: return pll clock frequency */ -static unsigned long exynos5420_get_pll_clk(int pllreg) +static unsigned long exynos542x_get_periph_rate(int peripheral) { + struct clk_bit_info *bit_info = get_clk_bit_info(peripheral); + unsigned long sclk = 0; + unsigned int src = 0, div = 0, sub_div = 0; struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned long r, k = 0; + (struct exynos5420_clock *)samsung_get_base_clock(); - switch (pllreg) { - case APLL: - r = readl(&clk->apll_con0); + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + case PERIPH_ID_PWM4: + src = readl(&clk->src_peric0); + div = readl(&clk->div_peric0); break; - case MPLL: - r = readl(&clk->mpll_con0); + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + src = readl(&clk->src_peric1); + div = readl(&clk->div_peric1); + sub_div = readl(&clk->div_peric4); break; - case EPLL: - r = readl(&clk->epll_con0); - k = readl(&clk->epll_con1); + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + src = readl(&clk->src_isp); + div = readl(&clk->div_isp1); + sub_div = readl(&clk->div_isp1); break; - case VPLL: - r = readl(&clk->vpll_con0); - k = readl(&clk->vpll_con1); + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + src = readl(&clk->src_fsys); + div = readl(&clk->div_fsys1); break; - case BPLL: - r = readl(&clk->bpll_con0); + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + case PERIPH_ID_I2C8: + case PERIPH_ID_I2C9: + case PERIPH_ID_I2C10: + src = EXYNOS542X_SRC_MPLL; + div = readl(&clk->div_top1); break; - case RPLL: - r = readl(&clk->rpll_con0); - k = readl(&clk->rpll_con1); + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + }; + + if (bit_info->src_bit >= 0) + src = (src >> bit_info->src_bit) & bit_info->src_mask; + + switch (src) { + case EXYNOS542X_SRC_MPLL: + sclk = exynos542x_get_pll_clk(MPLL); break; - case SPLL: - r = readl(&clk->spll_con0); + case EXYNOS542X_SRC_SPLL: + sclk = exynos542x_get_pll_clk(SPLL); + break; + case EXYNOS542X_SRC_EPLL: + sclk = exynos542x_get_pll_clk(EPLL); + break; + case EXYNOS542X_SRC_RPLL: + sclk = exynos542x_get_pll_clk(RPLL); break; default: - printf("Unsupported PLL (%d)\n", pllreg); + debug("%s: EXYNOS542X_SRC %d not supported", __func__, src); return 0; } - return exynos_get_pll_clk(pllreg, r, k); + /* Clock divider ratio for this peripheral */ + if (bit_info->div_bit >= 0) + div = (div >> bit_info->div_bit) & bit_info->div_mask; + + /* Clock pre-divider ratio for this peripheral */ + if (bit_info->prediv_bit >= 0) + sub_div = (sub_div >> bit_info->prediv_bit) + & bit_info->prediv_mask; + + /* Calculate and return required clock rate */ + return (sclk / (div + 1)) / (sub_div + 1); +} + +unsigned long clock_get_periph_rate(int peripheral) +{ + if (cpu_is_exynos5()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) + return exynos542x_get_periph_rate(peripheral); + return exynos5_get_periph_rate(peripheral); + } else { + return 0; + } } /* exynos4: return ARM clock frequency */ @@ -527,27 +690,6 @@ static unsigned long exynos4x12_get_pwm_clk(void) return pclk; } -/* exynos5420: return pwm clock frequency */ -static unsigned long exynos5420_get_pwm_clk(void) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned long pclk, sclk; - unsigned int ratio; - - /* - * CLK_DIV_PERIC0 - * PWM_RATIO [31:28] - */ - ratio = readl(&clk->div_peric0); - ratio = (ratio >> 28) & 0xf; - sclk = get_pll_clk(MPLL); - - pclk = sclk / (ratio + 1); - - return pclk; -} - /* exynos4: return uart clock frequency */ static unsigned long exynos4_get_uart_clk(int dev_index) { @@ -640,100 +782,6 @@ static unsigned long exynos4x12_get_uart_clk(int dev_index) return uclk; } -/* exynos5: return uart clock frequency */ -static unsigned long exynos5_get_uart_clk(int dev_index) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long uclk, sclk; - unsigned int sel; - unsigned int ratio; - - /* - * CLK_SRC_PERIC0 - * UART0_SEL [3:0] - * UART1_SEL [7:4] - * UART2_SEL [8:11] - * UART3_SEL [12:15] - * UART4_SEL [16:19] - * UART5_SEL [23:20] - */ - sel = readl(&clk->src_peric0); - sel = (sel >> (dev_index << 2)) & 0xf; - - if (sel == 0x6) - sclk = get_pll_clk(MPLL); - else if (sel == 0x7) - sclk = get_pll_clk(EPLL); - else if (sel == 0x8) - sclk = get_pll_clk(VPLL); - else - return 0; - - /* - * CLK_DIV_PERIC0 - * UART0_RATIO [3:0] - * UART1_RATIO [7:4] - * UART2_RATIO [8:11] - * UART3_RATIO [12:15] - * UART4_RATIO [16:19] - * UART5_RATIO [23:20] - */ - ratio = readl(&clk->div_peric0); - ratio = (ratio >> (dev_index << 2)) & 0xf; - - uclk = sclk / (ratio + 1); - - return uclk; -} - -/* exynos5420: return uart clock frequency */ -static unsigned long exynos5420_get_uart_clk(int dev_index) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned long uclk, sclk; - unsigned int sel; - unsigned int ratio; - - /* - * CLK_SRC_PERIC0 - * UART0_SEL [6:4] - * UART1_SEL [10:8] - * UART2_SEL [14:12] - * UART3_SEL [18:16] - * generalised calculation as follows - * sel = (sel >> ((dev_index * 4) + 4)) & mask; - */ - sel = readl(&clk->src_peric0); - sel = (sel >> ((dev_index * 4) + 4)) & 0x7; - - if (sel == 0x3) - sclk = get_pll_clk(MPLL); - else if (sel == 0x6) - sclk = get_pll_clk(EPLL); - else if (sel == 0x7) - sclk = get_pll_clk(RPLL); - else - return 0; - - /* - * CLK_DIV_PERIC0 - * UART0_RATIO [11:8] - * UART1_RATIO [15:12] - * UART2_RATIO [19:16] - * UART3_RATIO [23:20] - * generalised calculation as follows - * ratio = (ratio >> ((dev_index * 4) + 8)) & mask; - */ - ratio = readl(&clk->div_peric0); - ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf; - - uclk = sclk / (ratio + 1); - - return uclk; -} - static unsigned long exynos4_get_mmc_clk(int dev_index) { struct exynos4_clock *clk = @@ -783,94 +831,6 @@ static unsigned long exynos4_get_mmc_clk(int dev_index) return uclk; } -static unsigned long exynos5_get_mmc_clk(int dev_index) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long uclk, sclk; - unsigned int sel, ratio, pre_ratio; - int shift = 0; - - sel = readl(&clk->src_fsys); - sel = (sel >> (dev_index << 2)) & 0xf; - - if (sel == 0x6) - sclk = get_pll_clk(MPLL); - else if (sel == 0x7) - sclk = get_pll_clk(EPLL); - else if (sel == 0x8) - sclk = get_pll_clk(VPLL); - else - return 0; - - switch (dev_index) { - case 0: - case 1: - ratio = readl(&clk->div_fsys1); - pre_ratio = readl(&clk->div_fsys1); - break; - case 2: - case 3: - ratio = readl(&clk->div_fsys2); - pre_ratio = readl(&clk->div_fsys2); - break; - default: - return 0; - } - - if (dev_index == 1 || dev_index == 3) - shift = 16; - - ratio = (ratio >> shift) & 0xf; - pre_ratio = (pre_ratio >> (shift + 8)) & 0xff; - uclk = (sclk / (ratio + 1)) / (pre_ratio + 1); - - return uclk; -} - -static unsigned long exynos5420_get_mmc_clk(int dev_index) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned long uclk, sclk; - unsigned int sel, ratio; - - /* - * CLK_SRC_FSYS - * MMC0_SEL [10:8] - * MMC1_SEL [14:12] - * MMC2_SEL [18:16] - * generalised calculation as follows - * sel = (sel >> ((dev_index * 4) + 8)) & mask - */ - sel = readl(&clk->src_fsys); - sel = (sel >> ((dev_index * 4) + 8)) & 0x7; - - if (sel == 0x3) - sclk = get_pll_clk(MPLL); - else if (sel == 0x4) - sclk = get_pll_clk(SPLL); - else if (sel == 0x6) - sclk = get_pll_clk(EPLL); - else - return 0; - - /* - * CLK_DIV_FSYS1 - * MMC0_RATIO [9:0] - * MMC1_RATIO [19:10] - * MMC2_RATIO [29:20] - * generalised calculation as follows - * ratio = (ratio >> (dev_index * 10)) & mask - */ - ratio = readl(&clk->div_fsys1); - ratio = (ratio >> (dev_index * 10)) & 0x3ff; - - uclk = (sclk / (ratio + 1)); - - return uclk; -} - /* exynos4: set the mmc clock */ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) { @@ -1249,29 +1209,6 @@ void exynos4_set_mipi_clk(void) clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16); } -/* - * I2C - * - * exynos5: obtaining the I2C clock - */ -static unsigned long exynos5_get_i2c_clk(void) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long aclk_66, aclk_66_pre, sclk; - unsigned int ratio; - - sclk = get_pll_clk(MPLL); - - ratio = (readl(&clk->div_top1)) >> 24; - ratio &= 0x7; - aclk_66_pre = sclk / (ratio + 1); - ratio = readl(&clk->div_top0); - ratio &= 0x7; - aclk_66 = aclk_66_pre / (ratio + 1); - return aclk_66; -} - int exynos5_set_epll_clk(unsigned long rate) { unsigned int epll_con, epll_con_k; @@ -1585,7 +1522,7 @@ unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) { if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos5420_get_pll_clk(pllreg); + return exynos542x_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); } else { if (proid_is_exynos4412()) @@ -1608,7 +1545,7 @@ unsigned long get_arm_clk(void) unsigned long get_i2c_clk(void) { if (cpu_is_exynos5()) { - return exynos5_get_i2c_clk(); + return clock_get_periph_rate(PERIPH_ID_I2C0); } else if (cpu_is_exynos4()) { return exynos4_get_i2c_clk(); } else { @@ -1620,8 +1557,6 @@ unsigned long get_i2c_clk(void) unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos5420_get_pwm_clk(); return clock_get_periph_rate(PERIPH_ID_PWM0); } else { if (proid_is_exynos4412()) @@ -1632,10 +1567,28 @@ unsigned long get_pwm_clk(void) unsigned long get_uart_clk(int dev_index) { + enum periph_id id; + + switch (dev_index) { + case 0: + id = PERIPH_ID_UART0; + break; + case 1: + id = PERIPH_ID_UART1; + break; + case 2: + id = PERIPH_ID_UART2; + break; + case 3: + id = PERIPH_ID_UART3; + break; + default: + debug("%s: invalid UART index %d", __func__, dev_index); + return -1; + } + if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos5420_get_uart_clk(dev_index); - return exynos5_get_uart_clk(dev_index); + return clock_get_periph_rate(id); } else { if (proid_is_exynos4412()) return exynos4x12_get_uart_clk(dev_index); @@ -1645,10 +1598,28 @@ unsigned long get_uart_clk(int dev_index) unsigned long get_mmc_clk(int dev_index) { + enum periph_id id; + + switch (dev_index) { + case 0: + id = PERIPH_ID_SDMMC0; + break; + case 1: + id = PERIPH_ID_SDMMC1; + break; + case 2: + id = PERIPH_ID_SDMMC2; + break; + case 3: + id = PERIPH_ID_SDMMC3; + break; + default: + debug("%s: invalid MMC index %d", __func__, dev_index); + return -1; + } + if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos5420_get_mmc_clk(dev_index); - return exynos5_get_mmc_clk(dev_index); + return clock_get_periph_rate(id); } else { return exynos4_get_mmc_clk(dev_index); } @@ -1656,6 +1627,10 @@ unsigned long get_mmc_clk(int dev_index) void set_mmc_clk(int dev_index, unsigned int div) { + /* If want to set correct value, it needs to substract one from div.*/ + if (div > 0) + div -= 1; + if (cpu_is_exynos5()) { if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_set_mmc_clk(dev_index, div); diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index 1520d642c5..1b12051656 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -102,10 +102,34 @@ static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable) } } +static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable) +{ + struct exynos5420_power *power = + (struct exynos5420_power *)samsung_get_base_power(); + + if (enable) { + /* Enabling USBDEV_PHY */ + setbits_le32(&power->usbdev_phy_control, + POWER_USB_DRD_PHY_CTRL_EN); + setbits_le32(&power->usbdev1_phy_control, + POWER_USB_DRD_PHY_CTRL_EN); + } else { + /* Disabling USBDEV_PHY */ + clrbits_le32(&power->usbdev_phy_control, + POWER_USB_DRD_PHY_CTRL_EN); + clrbits_le32(&power->usbdev1_phy_control, + POWER_USB_DRD_PHY_CTRL_EN); + } +} + void set_usbdrd_phy_ctrl(unsigned int enable) { - if (cpu_is_exynos5()) - exynos5_set_usbdrd_phy_ctrl(enable); + if (cpu_is_exynos5()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) + exynos5420_set_usbdev_phy_ctrl(enable); + else + exynos5_set_usbdrd_phy_ctrl(enable); + } } static void exynos5_dp_phy_control(unsigned int enable) diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c index bc237c969f..c7f943eb6a 100644 --- a/arch/arm/cpu/armv7/exynos/spl_boot.c +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c @@ -309,4 +309,3 @@ void board_init_r(gd_t *id, ulong dest_addr) while (1) ; } -void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {} diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index ce2d92f5a6..1a640bbb9c 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -8,14 +8,214 @@ #include <asm/arch/clock.h> #include <asm/io.h> #include <asm/arch/immap_ls102xa.h> +#include <asm/cache.h> +#include <asm/system.h> #include <tsec.h> #include <netdev.h> #include <fsl_esdhc.h> #include "fsl_epu.h" +#define DCSR_RCPM2_BLOCK_OFFSET 0x223000 +#define DCSR_RCPM2_CPMFSMCR0 0x400 +#define DCSR_RCPM2_CPMFSMSR0 0x404 +#define DCSR_RCPM2_CPMFSMCR1 0x414 +#define DCSR_RCPM2_CPMFSMSR1 0x418 +#define CPMFSMSR_FSM_STATE_MASK 0x7f + DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_SYS_DCACHE_OFF + +/* + * Bit[1] of the descriptor indicates the descriptor type, + * and bit[0] indicates whether the descriptor is valid. + */ +#define PMD_TYPE_TABLE 0x3 +#define PMD_TYPE_SECT 0x1 + +/* AttrIndx[2:0] */ +#define PMD_ATTRINDX(t) ((t) << 2) + +/* Section */ +#define PMD_SECT_AF (1 << 10) + +#define BLOCK_SIZE_L1 (1UL << 30) +#define BLOCK_SIZE_L2 (1UL << 21) + +/* TTBCR flags */ +#define TTBCR_EAE (1 << 31) +#define TTBCR_T0SZ(x) ((x) << 0) +#define TTBCR_T1SZ(x) ((x) << 16) +#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0)) +#define TTBCR_IRGN0_NC (0 << 8) +#define TTBCR_IRGN0_WBWA (1 << 8) +#define TTBCR_IRGN0_WT (2 << 8) +#define TTBCR_IRGN0_WBNWA (3 << 8) +#define TTBCR_IRGN0_MASK (3 << 8) +#define TTBCR_ORGN0_NC (0 << 10) +#define TTBCR_ORGN0_WBWA (1 << 10) +#define TTBCR_ORGN0_WT (2 << 10) +#define TTBCR_ORGN0_WBNWA (3 << 10) +#define TTBCR_ORGN0_MASK (3 << 10) +#define TTBCR_SHARED_NON (0 << 12) +#define TTBCR_SHARED_OUTER (2 << 12) +#define TTBCR_SHARED_INNER (3 << 12) +#define TTBCR_EPD0 (0 << 7) +#define TTBCR (TTBCR_SHARED_NON | \ + TTBCR_ORGN0_NC | \ + TTBCR_IRGN0_NC | \ + TTBCR_USING_TTBR0 | \ + TTBCR_EAE) + +/* + * Memory region attributes for LPAE (defined in pgtable): + * + * n = AttrIndx[2:0] + * + * n MAIR + * UNCACHED 000 00000000 + * BUFFERABLE 001 01000100 + * DEV_WC 001 01000100 + * WRITETHROUGH 010 10101010 + * WRITEBACK 011 11101110 + * DEV_CACHED 011 11101110 + * DEV_SHARED 100 00000100 + * DEV_NONSHARED 100 00000100 + * unused 101 + * unused 110 + * WRITEALLOC 111 11111111 + */ +#define MT_MAIR0 0xeeaa4400 +#define MT_MAIR1 0xff000004 +#define MT_STRONLY_ORDER 0 +#define MT_NORMAL_NC 1 +#define MT_DEVICE_MEM 4 +#define MT_NORMAL 7 + +/* The phy_addr must be aligned to 4KB */ +static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr) +{ + u32 value = phy_addr | PMD_TYPE_TABLE; + + page_table[2 * index] = value; + page_table[2 * index + 1] = 0; +} + +/* The phy_addr must be aligned to 4KB */ +static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, + u32 memory_type) +{ + u64 value; + + value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF; + value |= PMD_ATTRINDX(memory_type); + page_table[2 * index] = value & 0xFFFFFFFF; + page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF; +} + +/* + * Start MMU after DDR is available, we create MMU table in DRAM. + * The base address of TTLB is gd->arch.tlb_addr. We use two + * levels of translation tables here to cover 40-bit address space. + * + * The TTLBs are located at PHY 2G~4G. + * + * VA mapping: + * + * ------- <---- 0GB + * | | + * | | + * |-------| <---- 0x24000000 + * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 + * |-------| <---- 0x300000000 + * | | + * |-------| <---- 0x34000000 + * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 + * |-------| <---- 0x40000000 + * | | + * |-------| <---- 0x80000000 DDR0 space start + * |\\\\\\\| + *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space + * |\\\\\\\| + * ------- <---- 4GB DDR0 space end + */ +static void mmu_setup(void) +{ + u32 *level0_table = (u32 *)gd->arch.tlb_addr; + u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000); + u64 va_start = 0; + u32 reg; + int i; + + /* Level 0 Table 2-3 are used to map DDR */ + set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); + set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); + /* Level 0 Table 1 is used to map device */ + set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); + /* Level 0 Table 0 is used to map device including PCIe MEM */ + set_pgtable(level0_table, 0, (u32)level1_table); + + /* Level 1 has 512 entries */ + for (i = 0; i < 512; i++) { + /* Mapping for PCIe 1 */ + if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR && + va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR + + CONFIG_SYS_PCIE_MMAP_SIZE)) + set_pgsection(level1_table, i, + CONFIG_SYS_PCIE1_PHYS_BASE + va_start, + MT_DEVICE_MEM); + /* Mapping for PCIe 2 */ + else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR && + va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR + + CONFIG_SYS_PCIE_MMAP_SIZE)) + set_pgsection(level1_table, i, + CONFIG_SYS_PCIE2_PHYS_BASE + va_start, + MT_DEVICE_MEM); + else + set_pgsection(level1_table, i, + va_start, + MT_DEVICE_MEM); + va_start += BLOCK_SIZE_L2; + } + + asm volatile("dsb sy;isb"); + asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */ + : : "r" (TTBCR) : "memory"); + asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */ + : : "r" ((u32)level0_table), "r" (0) : "memory"); + asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */ + : : "r" (MT_MAIR0) : "memory"); + asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */ + : : "r" (MT_MAIR1) : "memory"); + + /* Set the access control to all-supervisor */ + asm volatile("mcr p15, 0, %0, c3, c0, 0" + : : "r" (~0)); + + /* Enable the mmu */ + reg = get_cr(); + set_cr(reg | CR_M); +} + +/* + * This function is called from lib/board.c. It recreates MMU + * table in main memory. MMU and i/d-cache are enabled here. + */ +void enable_caches(void) +{ + /* Invalidate all TLB */ + mmu_page_table_flush(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + /* Set up and enable mmu */ + mmu_setup(); + + /* Invalidate & Enable d-cache */ + invalidate_dcache_all(); + set_cr(get_cr() | CR_C); +} +#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { @@ -78,16 +278,6 @@ int print_cpuinfo(void) } #endif -void enable_caches(void) -{ -#ifndef CONFIG_SYS_ICACHE_OFF - icache_enable(); -#endif -#ifndef CONFIG_SYS_DCACHE_OFF - dcache_enable(); -#endif -} - #ifdef CONFIG_FSL_ESDHC int cpu_mmc_init(bd_t *bis) { @@ -107,6 +297,27 @@ int cpu_eth_init(bd_t *bis) int arch_cpu_init(void) { void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *rcpm2_base = + (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); + u32 state; + + /* + * The RCPM FSM state may not be reset after power-on. + * So, reset them. + */ + state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) & + CPMFSMSR_FSM_STATE_MASK; + if (state != 0) { + out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80); + out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0); + } + + state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) & + CPMFSMSR_FSM_STATE_MASK; + if (state != 0) { + out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80); + out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0); + } /* * After wakeup from deep sleep, Clear EPU registers diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index e601ba1886..c01a98f719 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -252,6 +252,8 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); + writel(regs->sdram_config_init, &emif->emif_sdram_config); /* * Set SDRAM_CONFIG and PHY control registers to locked frequency * and RL =7. As the default values of the Mode Registers are not @@ -265,7 +267,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); - writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); /* @@ -274,6 +275,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) */ if (is_dra7xx()) { do_ext_phy_settings(base, regs); + writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); writel(regs->sdram_config_init, &emif->emif_sdram_config); } else { diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 86c0e42174..e19c7aecec 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -19,7 +19,7 @@ ENTRY(save_boot_params) ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS str r0, [r1] - bx lr + b save_boot_params_ret ENDPROC(save_boot_params) ENTRY(set_pl310_ctrl_reg) diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index a029379a4f..4a0ac2c987 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -93,6 +93,21 @@ config TARGET_TWISTER endchoice +config DM + default y + +config DM_GPIO + default y if DM + +config DM_SERIAL + default y if DM + +config SYS_MALLOC_F + default y if DM + +config SYS_MALLOC_F_LEN + default 0x400 if DM + config SYS_SOC default "omap3" diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 78577b1d1c..80cb2639f6 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -23,7 +23,7 @@ ENTRY(save_boot_params) ldr r5, [r0, #0x4] and r5, r5, #0xff str r5, [r4] - bx lr + b save_boot_params_ret ENDPROC(save_boot_params) #endif diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 7d8cec08c2..5f8daa1ee1 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -141,7 +141,8 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_config_init = 0x61851ab2, .sdram_config = 0x61851ab2, .sdram_config2 = 0x08000000, - .ref_ctrl = 0x00001035, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, @@ -151,10 +152,10 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { .emif_ddr_phy_ctlr_1_init = 0x0E24400A, .emif_ddr_phy_ctlr_1 = 0x0E24400A, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB, - .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB, - .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB, - .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, .emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x00000000, .emif_rd_wr_lvl_ctl = 0x00000000, @@ -165,7 +166,8 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { .sdram_config_init = 0x61851B32, .sdram_config = 0x61851B32, .sdram_config2 = 0x08000000, - .ref_ctrl = 0x00001035, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, .sdram_tim3 = 0x027F88A8, @@ -175,10 +177,10 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { .emif_ddr_phy_ctlr_1_init = 0x0E24400A, .emif_ddr_phy_ctlr_1 = 0x0E24400A, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB, - .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB, - .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB, - .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB, + .emif_ddr_ext_phy_ctrl_2 = 0x00910091, + .emif_ddr_ext_phy_ctrl_3 = 0x00950095, + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, .emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x00000000, .emif_rd_wr_lvl_ctl = 0x00000000, @@ -186,18 +188,19 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { }; const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { - .sdram_config_init = 0x61851AB2, - .sdram_config = 0x61851AB2, + .sdram_config_init = 0x61862B32, + .sdram_config = 0x61862B32, .sdram_config2 = 0x08000000, - .ref_ctrl = 0x00001035, - .sdram_tim1 = 0xCCCF36B3, - .sdram_tim2 = 0x308F7FDA, - .sdram_tim3 = 0x027F88A8, + .ref_ctrl = 0x0000493E, + .ref_ctrl_final = 0x0000144A, + .sdram_tim1 = 0xD113781C, + .sdram_tim2 = 0x308F7FE3, + .sdram_tim3 = 0x009F86A8, .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400A, - .emif_ddr_phy_ctlr_1 = 0x0024400A, + .emif_ddr_phy_ctlr_1_init = 0x0E24400D, + .emif_ddr_phy_ctlr_1 = 0x0E24400D, .emif_ddr_ext_phy_ctrl_1 = 0x10040100, .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9, @@ -420,22 +423,22 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = { const u32 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { - 0x00BB00BB, - 0x00440044, - 0x00440044, - 0x00440044, - 0x00440044, - 0x00440044, + 0x00980098, + 0x00340034, + 0x00350035, + 0x00340034, + 0x00310031, + 0x00340034, 0x007F007F, 0x007F007F, 0x007F007F, 0x007F007F, 0x007F007F, - 0x00600060, - 0x00600060, - 0x00600060, - 0x00600060, - 0x00600060, + 0x00480048, + 0x004A004A, + 0x00520052, + 0x00550055, + 0x00500050, 0x00000000, 0x00600020, 0x40010080, @@ -449,22 +452,22 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { const u32 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { - 0x00BB00BB, - 0x00440044, - 0x00440044, - 0x00440044, - 0x00440044, - 0x00440044, + 0x00980098, + 0x00330033, + 0x00330033, + 0x002F002F, + 0x00320032, + 0x00310031, 0x007F007F, 0x007F007F, 0x007F007F, 0x007F007F, 0x007F007F, - 0x00600060, - 0x00600060, - 0x00600060, - 0x00600060, - 0x00600060, + 0x00520052, + 0x00520052, + 0x00470047, + 0x00490049, + 0x00500050, 0x00000000, 0x00600020, 0x40010080, diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig index 6d94199de8..35866508a3 100644 --- a/arch/arm/cpu/armv7/rmobile/Kconfig +++ b/arch/arm/cpu/armv7/rmobile/Kconfig @@ -21,6 +21,9 @@ config TARGET_KZM9G config TARGET_ALT bool "Alt board" +config TARGET_SILK + bool "Silk board" + endchoice config SYS_SOC @@ -28,7 +31,7 @@ config SYS_SOC config RMOBILE_EXTRAM_BOOT bool "Enable boot from RAM" - depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER + depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK default n source "board/atmark-techno/armadillo-800eva/Kconfig" @@ -37,5 +40,6 @@ source "board/renesas/koelsch/Kconfig" source "board/renesas/lager/Kconfig" source "board/kmc/kzm9g/Kconfig" source "board/renesas/alt/Kconfig" +source "board/renesas/silk/Kconfig" endif diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S index d47546a11d..a5dbbea9e1 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -40,7 +40,7 @@ do_lowlevel_init: and r1, r1, #0x7F00 lsrs r1, r1, #8 cmp r1, #0x4C /* 0x4C is ID of r8a7794 */ - beq _exit_init_l2_a15 + beq _enable_actlr_smp /* surpress wfe if ca15 */ tst r4, #4 @@ -64,6 +64,16 @@ do_lowlevel_init: orrne r0, r0, #0x20 /* L2CTLR[5] */ #endif mcrne p15, 1, r0, c9, c0, 2 + + b _exit_init_l2_a15 + +_enable_actlr_smp: /* R8A7794 only (CA7) */ +#ifndef CONFIG_DCACHE_OFF + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 +#endif + _exit_init_l2_a15: ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) sub sp, r3, #4 diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig index 628813423f..bc73813832 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig +++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig @@ -5,11 +5,11 @@ choice config TARGET_S5P_GONI bool "S5P Goni board" - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_SMDKC100 bool "Support smdkc100 board" - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL endchoice diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 70048c10ae..9b49ece2d6 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -31,9 +31,12 @@ *************************************************************************/ .globl reset + .globl save_boot_params_ret reset: - bl save_boot_params + /* Allow the board to save important registers */ + b save_boot_params +save_boot_params_ret: /* * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, * except if in HYP mode already @@ -96,7 +99,7 @@ ENDPROC(c_runtime_cpu_setup) * *************************************************************************/ ENTRY(save_boot_params) - bx lr @ back to my caller + b save_boot_params_ret @ back to my caller ENDPROC(save_boot_params) .weak save_boot_params diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 48db7442f4..4bb12ad8bd 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -11,6 +11,7 @@ obj-y += timer.o obj-y += board.o obj-y += clock.o obj-y += cpu_info.o +obj-y += dram_helpers.o obj-y += pinmux.o obj-y += usbc.o obj-$(CONFIG_MACH_SUN6I) += prcm.o @@ -38,7 +39,5 @@ obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o -ifdef CONFIG_SPL_FEL -obj-y += start.o -endif +obj-y += fel_utils.o endif diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 6e28bcd040..c02c015096 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -27,6 +27,17 @@ #include <linux/compiler.h> +struct fel_stash { + uint32_t sp; + uint32_t lr; + uint32_t cpsr; + uint32_t sctlr; + uint32_t vbar; + uint32_t cr; +}; + +struct fel_stash fel_stash __attribute__((section(".data"))); + static int gpio_init(void) { #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) @@ -65,6 +76,12 @@ static int gpio_init(void) return 0; } +void spl_board_load_image(void) +{ + debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); + return_to_fel(fel_stash.sp, fel_stash.lr); +} + void s_init(void) { #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I @@ -95,7 +112,34 @@ void s_init(void) */ u32 spl_boot_device(void) { - return BOOT_DEVICE_MMC1; +#ifdef CONFIG_SPL_FEL + /* + * This is the legacy compile time configuration for a special FEL + * enabled build. It has many restrictions and can only boot over USB. + */ + return BOOT_DEVICE_BOARD; +#else + /* + * When booting from the SD card, the "eGON.BT0" signature is expected + * to be found in memory at the address 0x0004 (see the "mksunxiboot" + * tool, which generates this header). + * + * When booting in the FEL mode over USB, this signature is patched in + * memory and replaced with something else by the 'fel' tool. This other + * signature is selected in such a way, that it can't be present in a + * valid bootable SD card image (because the BROM would refuse to + * execute the SPL in this case). + * + * This branch is just making a decision at runtime whether to load + * the main u-boot binary from the SD card (if the "eGON.BT0" signature + * is found) or return to the FEL code in the BROM to wait and receive + * the main u-boot binary over USB. + */ + if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */ + return BOOT_DEVICE_MMC1; + else + return BOOT_DEVICE_BOARD; +#endif } /* No confirmation data available in SPL yet. Hardcode bootmode */ diff --git a/arch/arm/cpu/armv7/sunxi/config.mk b/arch/arm/cpu/armv7/sunxi/config.mk index 00f5ffc683..76ffec9df6 100644 --- a/arch/arm/cpu/armv7/sunxi/config.mk +++ b/arch/arm/cpu/armv7/sunxi/config.mk @@ -1,8 +1,6 @@ # Build a combined spl + u-boot image ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD -ifndef CONFIG_SPL_FEL ALL-y += u-boot-sunxi-with-spl.bin endif endif -endif diff --git a/arch/arm/cpu/armv7/sunxi/dram_helpers.c b/arch/arm/cpu/armv7/sunxi/dram_helpers.c new file mode 100644 index 0000000000..9a94e1b679 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/dram_helpers.c @@ -0,0 +1,37 @@ +/* + * DRAM init helper functions + * + * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/dram.h> + +/* + * Wait up to 1s for value to be set in given part of reg. + */ +void mctl_await_completion(u32 *reg, u32 mask, u32 val) +{ + unsigned long tmo = timer_get_us() + 1000000; + + while ((readl(reg) & mask) != val) { + if (timer_get_us() > tmo) + panic("Timeout initialising DRAM\n"); + } +} + +/* + * Test if memory at offset offset matches memory at begin of DRAM + */ +bool mctl_mem_matches(u32 offset) +{ + /* Try to write different values to RAM at two addresses */ + writel(0, CONFIG_SYS_SDRAM_BASE); + writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset); + /* Check if the same value is actually observed when reading back */ + return readl(CONFIG_SYS_SDRAM_BASE) == + readl(CONFIG_SYS_SDRAM_BASE + offset); +} diff --git a/arch/arm/cpu/armv7/sunxi/fel_utils.S b/arch/arm/cpu/armv7/sunxi/fel_utils.S new file mode 100644 index 0000000000..bf0033552d --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/fel_utils.S @@ -0,0 +1,42 @@ +/* + * Utility functions for FEL mode. + * + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> +#include <config.h> +#include <asm/system.h> +#include <linux/linkage.h> + +ENTRY(save_boot_params) + ldr r0, =fel_stash + str sp, [r0, #0] + str lr, [r0, #4] + mrs lr, cpsr @ Read CPSR + str lr, [r0, #8] + mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register + str lr, [r0, #12] + mrc p15, 0, lr, c12, c0, 0 @ Read VBAR + str lr, [r0, #16] + mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register + str lr, [r0, #20] + b save_boot_params_ret +ENDPROC(save_boot_params) + +ENTRY(return_to_fel) + mov sp, r0 + mov lr, r1 + ldr r0, =fel_stash + ldr r1, [r0, #20] + mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register + ldr r1, [r0, #16] + mcr p15, 0, r1, c12, c0, 0 @ Write VBAR + ldr r1, [r0, #12] + mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register + ldr r1, [r0, #8] + msr cpsr, r1 @ Write CPSR + bx lr +ENDPROC(return_to_fel) diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds deleted file mode 100644 index 928b7c19e0..0000000000 --- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2013 - * Henrik Nordstrom <henrik@henriknordstrom.net> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(s_init) -SECTIONS -{ - . = 0x00002000; - - . = ALIGN(4); - .text : - { - *(.text.s_init) - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - . = .; - - . = ALIGN(4); - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - . = ALIGN(4); - .note.gnu.build-id : - { - *(.note.gnu.build-id) - } - _end = .; - - . = ALIGN(4096); - .mmutable : { - *(.mmutable) - } - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } - /DISCARD/ : { *(.note*) } -} diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig deleted file mode 100644 index 1446452c23..0000000000 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ /dev/null @@ -1,28 +0,0 @@ -if TEGRA - -choice - prompt "Tegra SoC select" - -config TEGRA20 - bool "Tegra20 family" - -config TEGRA30 - bool "Tegra30 family" - -config TEGRA114 - bool "Tegra114 family" - -config TEGRA124 - bool "Tegra124 family" - -endchoice - -config USE_PRIVATE_LIBGCC - default y if SPL_BUILD - -source "arch/arm/cpu/armv7/tegra20/Kconfig" -source "arch/arm/cpu/armv7/tegra30/Kconfig" -source "arch/arm/cpu/armv7/tegra114/Kconfig" -source "arch/arm/cpu/armv7/tegra124/Kconfig" - -endif diff --git a/arch/arm/cpu/armv7/tegra-common/Makefile b/arch/arm/cpu/armv7/tegra-common/Makefile deleted file mode 100644 index 463c260f18..0000000000 --- a/arch/arm/cpu/armv7/tegra-common/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2010,2011 Nvidia Corporation. -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o diff --git a/arch/arm/cpu/armv7/tegra20/Makefile b/arch/arm/cpu/armv7/tegra20/Makefile deleted file mode 100644 index 9b4295c72d..0000000000 --- a/arch/arm/cpu/armv7/tegra20/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2010,2011 Nvidia Corporation. -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_PWM_TEGRA) += pwm.o -obj-$(CONFIG_VIDEO_TEGRA) += display.o diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 5c5a84fe56..8335685e32 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -48,6 +48,12 @@ config DCC_MICRO_SUPPORT_CARD endchoice +config SYS_MALLOC_F + default y + +config SYS_MALLOC_F_LEN + default 0x400 + config CMD_PINMON bool "Enable boot mode pins monitor command" default y @@ -58,14 +64,12 @@ config CMD_PINMON config CMD_DDRPHY_DUMP bool "Enable dump command of DDR PHY parameters" - depends on !SPL_BUILD help The command "ddrphy" shows the resulting parameters of DDR PHY training; it is useful for the evaluation of DDR PHY training. choice prompt "DDR3 Frequency select" - depends on SPL_BUILD config DDR_FREQ_1600 bool "DDR3 1600" diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 9c6e8243bb..fa447bce16 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -155,3 +155,9 @@ ENTRY(__asm_invalidate_icache_all) isb sy ret ENDPROC(__asm_invalidate_icache_all) + +ENTRY(__asm_flush_l3_cache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(__asm_flush_l3_cache) + .weak __asm_flush_l3_cache diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 9dbcdf22af..c5ec5297cd 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -73,17 +73,21 @@ void invalidate_dcache_all(void) __asm_invalidate_dcache_all(); } -void __weak flush_l3_cache(void) -{ -} - /* - * Performs a clean & invalidation of the entire data cache at all levels + * Performs a clean & invalidation of the entire data cache at all levels. + * This function needs to be inline to avoid using stack. + * __asm_flush_l3_cache return status of timeout */ -void flush_dcache_all(void) +inline void flush_dcache_all(void) { + int ret; + __asm_flush_dcache_all(); - flush_l3_cache(); + ret = __asm_flush_l3_cache(); + if (ret) + debug("flushing dcache returns 0x%x\n", ret); + else + debug("flushing dcache successfully.\n"); } /* diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 47b947f44f..49974878b9 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -10,10 +10,10 @@ #include <asm/armv8/mmu.h> #include <asm/io.h> #include <asm/arch-fsl-lsch3/immap_lsch3.h> +#include <fsl-mc/fsl_mc.h> #include "cpu.h" #include "mp.h" #include "speed.h" -#include <fsl_mc.h> DECLARE_GLOBAL_DATA_PTR; @@ -150,7 +150,7 @@ static inline void final_mmu_setup(void) * set level 2 table 0 to cache-inhibit, covering 0 to 1GB */ section_l1t0 = 0; - section_l1t1 = BLOCK_SIZE_L0; + section_l1t1 = BLOCK_SIZE_L0 | PMD_SECT_OUTER_SHARE; section_l2 = 0; for (i = 0; i < 512; i++) { set_pgtable_section(level1_table_0, i, section_l1t0, @@ -168,10 +168,10 @@ static inline void final_mmu_setup(void) (u64)level2_table_0 | PMD_TYPE_TABLE; level1_table_0[2] = 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_ATTRINDX(MT_NORMAL); + PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL); level1_table_0[3] = 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_ATTRINDX(MT_NORMAL); + PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL); /* Rewrite table to enable cache */ set_pgtable_section(level2_table_0, @@ -243,59 +243,6 @@ int arch_cpu_init(void) } /* - * flush_l3_cache - * Dickens L3 cache can be flushed by transitioning from FAM to SFONLY power - * state, by writing to HP-F P-state request register. - * Fixme: This function should moved to a common file if other SoCs also use - * the same Dickens. - */ -#define HNF0_PSTATE_REQ 0x04200010 -#define HNF1_PSTATE_REQ 0x04210010 -#define HNF2_PSTATE_REQ 0x04220010 -#define HNF3_PSTATE_REQ 0x04230010 -#define HNF4_PSTATE_REQ 0x04240010 -#define HNF5_PSTATE_REQ 0x04250010 -#define HNF6_PSTATE_REQ 0x04260010 -#define HNF7_PSTATE_REQ 0x04270010 -#define HNFPSTAT_MASK (0xFFFFFFFFFFFFFFFC) -#define HNFPSTAT_FAM 0x3 -#define HNFPSTAT_SFONLY 0x01 - -static void hnf_pstate_req(u64 *ptr, u64 state) -{ - int timeout = 1000; - out_le64(ptr, (in_le64(ptr) & HNFPSTAT_MASK) | (state & 0x3)); - ptr++; - /* checking if the transition is completed */ - while (timeout > 0) { - if (((in_le64(ptr) & 0x0c) >> 2) == (state & 0x3)) - break; - udelay(100); - timeout--; - } -} - -void flush_l3_cache(void) -{ - hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_FAM); -} - -/* * This function is called from lib/board.c. * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. * There is no need to disable d-cache for this operation. @@ -420,6 +367,7 @@ int print_cpuinfo(void) printf("\n Bus: %-4s MHz ", strmhz(buf, sysinfo.freq_systembus)); printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus)); + printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2)); puts("\n"); return 0; diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c index e392eb9149..7eb9b6aa4b 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c @@ -16,7 +16,7 @@ void ft_fixup_cpu(void *blob) __maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr(); fdt32_t *reg; int addr_cells; - u64 val; + u64 val, core_id; size_t *boot_code_size = &(__secondary_boot_code_size); off = fdt_path_offset(blob, "/cpus"); @@ -29,15 +29,20 @@ void ft_fixup_cpu(void *blob) off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0); + core_id = of_read_number(reg, addr_cells); if (reg) { - val = spin_tbl_addr; - val += id_to_core(of_read_number(reg, addr_cells)) - * SPIN_TABLE_ELEM_SIZE; - val = cpu_to_fdt64(val); - fdt_setprop_string(blob, off, "enable-method", - "spin-table"); - fdt_setprop(blob, off, "cpu-release-addr", - &val, sizeof(val)); + if (core_id == 0 || (is_core_online(core_id))) { + val = spin_tbl_addr; + val += id_to_core(core_id) * + SPIN_TABLE_ELEM_SIZE; + val = cpu_to_fdt64(val); + fdt_setprop_string(blob, off, "enable-method", + "spin-table"); + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); + } else { + debug("skipping offline core\n"); + } } else { puts("Warning: found cpu node without reg property\n"); } @@ -55,4 +60,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_MP ft_fixup_cpu(blob); #endif + +#ifdef CONFIG_SYS_NS16550 + do_fixup_by_compat_u32(blob, "ns16550", + "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S index 2a88aab283..886576ef99 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -42,10 +42,142 @@ ENTRY(lowlevel_init) ldr x0, =secondary_boot_func blr x0 2: + +#ifdef CONFIG_FSL_TZPC_BP147 + /* Set Non Secure access for all devices protected via TZPC */ + ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */ + orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */ + str w0, [x1] + + isb + dsb sy +#endif + +#ifdef CONFIG_FSL_TZASC_400 + /* Set TZASC so that: + * a. We use only Region0 whose global secure write/read is EN + * b. We use only Region0 whose NSAID write/read is EN + * + * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just + * placeholders. + */ + ldr x1, =TZASC_GATE_KEEPER(0) + ldr x0, [x1] /* Filter 0 Gate Keeper Register */ + orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */ + str x0, [x1] + + ldr x1, =TZASC_GATE_KEEPER(1) + ldr x0, [x1] /* Filter 0 Gate Keeper Register */ + orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */ + str x0, [x1] + + ldr x1, =TZASC_REGION_ATTRIBUTES_0(0) + ldr x0, [x1] /* Region-0 Attributes Register */ + orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */ + orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */ + str x0, [x1] + + ldr x1, =TZASC_REGION_ATTRIBUTES_0(1) + ldr x0, [x1] /* Region-1 Attributes Register */ + orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */ + orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */ + str x0, [x1] + + ldr x1, =TZASC_REGION_ID_ACCESS_0(0) + ldr w0, [x1] /* Region-0 Access Register */ + mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ + str w0, [x1] + + ldr x1, =TZASC_REGION_ID_ACCESS_0(1) + ldr w0, [x1] /* Region-1 Attributes Register */ + mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ + str w0, [x1] + + isb + dsb sy +#endif mov lr, x29 /* Restore LR */ ret ENDPROC(lowlevel_init) +hnf_pstate_poll: + /* x0 has the desired status, return 0 for success, 1 for timeout + * clobber x1, x2, x3, x4, x6, x7 + */ + mov x1, x0 + mov x7, #0 /* flag for timeout */ + mrs x3, cntpct_el0 /* read timer */ + add x3, x3, #1200 /* timeout after 100 microseconds */ + mov x0, #0x18 + movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */ + mov w6, #8 /* HN-F node count */ +1: + ldr x2, [x0] + cmp x2, x1 /* check status */ + b.eq 2f + mrs x4, cntpct_el0 + cmp x4, x3 + b.ls 1b + mov x7, #1 /* timeout */ + b 3f +2: + add x0, x0, #0x10000 /* move to next node */ + subs w6, w6, #1 + cbnz w6, 1b +3: + mov x0, x7 + ret + +hnf_set_pstate: + /* x0 has the desired state, clobber x1, x2, x6 */ + mov x1, x0 + /* power state to SFONLY */ + mov w6, #8 /* HN-F node count */ + mov x0, #0x10 + movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */ +1: /* set pstate to sfonly */ + ldr x2, [x0] + and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */ + orr x2, x2, x1 + str x2, [x0] + add x0, x0, #0x10000 /* move to next node */ + subs w6, w6, #1 + cbnz w6, 1b + + ret + +ENTRY(__asm_flush_l3_cache) + /* + * Return status in x0 + * success 0 + * tmeout 1 for setting SFONLY, 2 for FAM, 3 for both + */ + mov x29, lr + mov x8, #0 + + dsb sy + mov x0, #0x1 /* HNFPSTAT_SFONLY */ + bl hnf_set_pstate + + mov x0, #0x4 /* SFONLY status */ + bl hnf_pstate_poll + cbz x0, 1f + mov x8, #1 /* timeout */ +1: + dsb sy + mov x0, #0x3 /* HNFPSTAT_FAM */ + bl hnf_set_pstate + + mov x0, #0xc /* FAM status */ + bl hnf_pstate_poll + cbz x0, 1f + add x8, x8, #0x2 +1: + mov x0, x8 + mov lr, x29 + ret +ENDPROC(__asm_flush_l3_cache) + /* Keep literals not used by the secondary boot code outside it */ .ltorg diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-lsch3/mp.c index 94998bf37b..ce9c0c1bdb 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c @@ -83,6 +83,14 @@ int is_core_valid(unsigned int core) return !!((1 << core) & cpu_mask()); } +int is_core_online(u64 cpu_id) +{ + u64 *table; + int pos = id_to_core(cpu_id); + table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY; + return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1; +} + int cpu_reset(int nr) { puts("Feature is not implemented.\n"); diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/cpu/armv8/fsl-lsch3/mp.h index 06ac0bcf36..66144d6101 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h @@ -32,5 +32,6 @@ int fsl_lsch3_wake_seconday_cores(void); void *get_spin_tbl_addr(void); phys_addr_t determine_mp_bootpg(void); void secondary_boot_func(void); +int is_core_online(u64 cpu_id); #endif #endif /* _FSL_CH3_MP_H */ diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c index dc4a34bce5..72cd999c5f 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c @@ -77,8 +77,10 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_systembus = sysclk; #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; + sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ; #else sys_info->freq_ddrbus = sysclk; + sys_info->freq_ddrbus2 = sysclk; #endif sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >> @@ -87,6 +89,9 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; + sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >> + FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & + FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { /* @@ -129,7 +134,7 @@ int get_clocks(void) gd->cpu_clk = sys_info.freq_processor[0]; gd->bus_clk = sys_info.freq_systembus; gd->mem_clk = sys_info.freq_ddrbus; - + gd->arch.mem2_clk = sys_info.freq_ddrbus2; #if defined(CONFIG_FSL_ESDHC) gd->arch.sdhc_clk = gd->bus_clk / 2; #endif /* defined(CONFIG_FSL_ESDHC) */ @@ -156,11 +161,18 @@ ulong get_bus_freq(ulong dummy) * get_ddr_freq * return ddr bus freq in Hz *********************************************/ -ulong get_ddr_freq(ulong dummy) +ulong get_ddr_freq(ulong ctrl_num) { if (!gd->mem_clk) get_clocks(); + /* + * DDR controller 0 & 1 are on memory complex 0 + * DDR controler 2 is on memory complext 1 + */ + if (ctrl_num >= 2) + return gd->arch.mem2_clk; + return gd->mem_clk; } diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts index 00a2917596..582f6e594b 100644 --- a/arch/arm/dts/exynos4412-odroid.dts +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -85,4 +85,9 @@ reg = <0x125B0000 0x100>; }; }; + + emmc-reset { + compatible = "samsung,emmc-reset"; + reset-gpio = <&gpk1 2 0>; + }; }; diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts index 8f4663733c..d0a8621fda 100644 --- a/arch/arm/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -46,4 +46,9 @@ mmc@12220000 { fifoth_val = <0x201f0020>; }; + + emmc-reset { + compatible = "samsung,emmc-reset"; + reset-gpio = <&gpd1 0 0>; + }; }; diff --git a/arch/arm/include/asm/arch-a320/a320.h b/arch/arm/include/asm/arch-a320/a320.h deleted file mode 100644 index f2db8e1061..0000000000 --- a/arch/arm/include/asm/arch-a320/a320.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __A320_H -#define __A320_H - -/* - * Hardware register bases - */ -#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */ -#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */ -#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */ -#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */ -#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */ -#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */ -#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/ - -#endif /* __A320_H */ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index b94b56cba7..523d22eb87 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -400,6 +400,8 @@ struct prm_device_inst { struct cm_dpll { unsigned int resv1; unsigned int clktimer2clk; /* offset 0x04 */ + unsigned int resv2[11]; + unsigned int clkselmacclk; /* offset 0x34 */ }; #endif /* CONFIG_AM43XX */ diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h b/arch/arm/include/asm/arch-bcm2835/gpio.h index db42896201..c8ef8f528a 100644 --- a/arch/arm/include/asm/arch-bcm2835/gpio.h +++ b/arch/arm/include/asm/arch-bcm2835/gpio.h @@ -1,6 +1,7 @@ /* * Copyright (C) 2012 Vikram Narayananan * <vikram186@gmail.com> + * (C) Copyright 2012,2015 Stephen Warren * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,7 +9,11 @@ #ifndef _BCM2835_GPIO_H_ #define _BCM2835_GPIO_H_ +#ifdef CONFIG_BCM2836 +#define BCM2835_GPIO_BASE 0x3f200000 +#else #define BCM2835_GPIO_BASE 0x20200000 +#endif #define BCM2835_GPIO_COUNT 54 #define BCM2835_GPIO_FSEL_MASK 0x7 diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h index 88d2ec11a7..04bf480a54 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2012 Stephen Warren + * (C) Copyright 2012,2015 Stephen Warren * * SPDX-License-Identifier: GPL-2.0+ */ @@ -38,7 +38,11 @@ /* Raw mailbox HW */ +#ifdef CONFIG_BCM2836 +#define BCM2835_MBOX_PHYSADDR 0x3f00b880 +#else #define BCM2835_MBOX_PHYSADDR 0x2000b880 +#endif struct bcm2835_mbox_regs { u32 read; @@ -121,6 +125,9 @@ struct bcm2835_mbox_tag_hdr { #define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002 +#ifdef CONFIG_BCM2836 +#define BCM2836_BOARD_REV_2_B 0x4 +#else /* * 0x2..0xf from: * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/ @@ -141,6 +148,7 @@ struct bcm2835_mbox_tag_hdr { #define BCM2835_BOARD_REV_B_PLUS 0x10 #define BCM2835_BOARD_REV_CM 0x11 #define BCM2835_BOARD_REV_A_PLUS 0x12 +#endif struct bcm2835_mbox_tag_get_board_rev { struct bcm2835_mbox_tag_hdr tag_hdr; diff --git a/arch/arm/include/asm/arch-bcm2835/sdhci.h b/arch/arm/include/asm/arch-bcm2835/sdhci.h index a4f867b2e9..2a21ccbf66 100644 --- a/arch/arm/include/asm/arch-bcm2835/sdhci.h +++ b/arch/arm/include/asm/arch-bcm2835/sdhci.h @@ -1,23 +1,17 @@ /* - * (C) Copyright 2012 Stephen Warren + * (C) Copyright 2012,2015 Stephen Warren * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _BCM2835_SDHCI_H_ #define _BCM2835_SDHCI_H_ +#ifdef CONFIG_BCM2836 +#define BCM2835_SDHCI_BASE 0x3f300000 +#else #define BCM2835_SDHCI_BASE 0x20300000 +#endif int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq); diff --git a/arch/arm/include/asm/arch-bcm2835/timer.h b/arch/arm/include/asm/arch-bcm2835/timer.h index c2001b6f93..fc7aec7b7c 100644 --- a/arch/arm/include/asm/arch-bcm2835/timer.h +++ b/arch/arm/include/asm/arch-bcm2835/timer.h @@ -1,23 +1,17 @@ /* - * (C) Copyright 2012 Stephen Warren + * (C) Copyright 2012,2015 Stephen Warren * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _BCM2835_TIMER_H #define _BCM2835_TIMER_H +#ifdef CONFIG_BCM2836 +#define BCM2835_TIMER_PHYSADDR 0x3f003000 +#else #define BCM2835_TIMER_PHYSADDR 0x20003000 +#endif struct bcm2835_timer_regs { u32 cs; diff --git a/arch/arm/include/asm/arch-bcm2835/wdog.h b/arch/arm/include/asm/arch-bcm2835/wdog.h index 303a65f32e..beb6a08206 100644 --- a/arch/arm/include/asm/arch-bcm2835/wdog.h +++ b/arch/arm/include/asm/arch-bcm2835/wdog.h @@ -1,23 +1,17 @@ /* - * (C) Copyright 2012 Stephen Warren + * (C) Copyright 2012,2015 Stephen Warren * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _BCM2835_TIMER_H #define _BCM2835_TIMER_H +#ifdef CONFIG_BCM2836 +#define BCM2835_WDOG_PHYSADDR 0x3f100000 +#else #define BCM2835_WDOG_PHYSADDR 0x20100000 +#endif struct bcm2835_wdog_regs { u32 unknown0[7]; diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0e89..2a17dfc6de 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -26,6 +26,10 @@ enum pll_src_bit { EXYNOS_SRC_MPLL = 6, EXYNOS_SRC_EPLL, EXYNOS_SRC_VPLL, + EXYNOS542X_SRC_MPLL = 3, + EXYNOS542X_SRC_SPLL, + EXYNOS542X_SRC_EPLL = 6, + EXYNOS542X_SRC_RPLL, }; unsigned long get_pll_clk(int pllreg); diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index da551e8839..b140c1fac2 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -30,11 +30,44 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL +#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL +#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL +#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL + #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +/* TZ Protection Controller Definitions */ +#define TZPC_BASE 0x02200000 +#define TZPCR0SIZE_BASE (TZPC_BASE) +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) + +/* TZ Address Space Controller Definitions */ +#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ +#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ +#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ +#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ +#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) +#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) +#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) +#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) +#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) +#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) +#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) +#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) +#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) + /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 #define GICR_BASE 0x06100000 @@ -68,4 +101,9 @@ #error SoC not defined #endif +#ifdef CONFIG_LS2085A +#define CONFIG_SYS_FSL_ERRATUM_A008336 +#define CONFIG_SYS_FSL_ERRATUM_A008514 +#endif + #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h index ee1d6512d9..dd11ef79c8 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h @@ -15,6 +15,7 @@ struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; unsigned long freq_ddrbus; + unsigned long freq_ddrbus2; unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN @@ -60,6 +61,8 @@ struct ccsr_gur { #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f +#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 +#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f u8 res_180[0x200-0x180]; u32 scratchrw[32]; /* Scratch Read/Write */ u8 res_280[0x300-0x280]; diff --git a/arch/arm/include/asm/arch-ks8695/platform.h b/arch/arm/include/asm/arch-ks8695/platform.h deleted file mode 100644 index 02f6049263..0000000000 --- a/arch/arm/include/asm/arch-ks8695/platform.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __address_h -#define __address_h 1 - -#define KS8695_SDRAM_START 0x00000000 -#define KS8695_SDRAM_SIZE 0x01000000 -#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE -#define KS8695_MEM_START KS8695_SDRAM_START - -#define KS8695_PCMCIA_IO_BASE 0x03800000 -#define KS8695_PCMCIA_IO_SIZE 0x00040000 - -#define KS8695_IO_BASE 0x03FF0000 -#define KS8695_IO_SIZE 0x00010000 - -#define KS8695_SYSTEN_CONFIG 0x00 -#define KS8695_SYSTEN_BUS_CLOCK 0x04 - -#define KS8695_FLASH_START 0x02800000 -#define KS8695_FLASH_SIZE 0x00400000 - -/*i/o control registers offset difinitions*/ -#define KS8695_IO_CTRL0 0x4000 -#define KS8695_IO_CTRL1 0x4004 -#define KS8695_IO_CTRL2 0x4008 -#define KS8695_IO_CTRL3 0x400C - -/*memory control registers offset difinitions*/ -#define KS8695_MEM_CTRL0 0x4010 -#define KS8695_MEM_CTRL1 0x4014 -#define KS8695_MEM_CTRL2 0x4018 -#define KS8695_MEM_CTRL3 0x401C -#define KS8695_MEM_GENERAL 0x4020 -#define KS8695_SDRAM_CTRL0 0x4030 -#define KS8695_SDRAM_CTRL1 0x4034 -#define KS8695_SDRAM_GENERAL 0x4038 -#define KS8695_SDRAM_BUFFER 0x403C -#define KS8695_SDRAM_REFRESH 0x4040 - -/*WAN control registers offset difinitions*/ -#define KS8695_WAN_DMA_TX 0x6000 -#define KS8695_WAN_DMA_RX 0x6004 -#define KS8695_WAN_DMA_TX_START 0x6008 -#define KS8695_WAN_DMA_RX_START 0x600C -#define KS8695_WAN_TX_LIST 0x6010 -#define KS8695_WAN_RX_LIST 0x6014 -#define KS8695_WAN_MAC_LOW 0x6018 -#define KS8695_WAN_MAC_HIGH 0x601C -#define KS8695_WAN_MAC_ELOW 0x6080 -#define KS8695_WAN_MAC_EHIGH 0x6084 - -/*LAN control registers offset difinitions*/ -#define KS8695_LAN_DMA_TX 0x8000 -#define KS8695_LAN_DMA_RX 0x8004 -#define KS8695_LAN_DMA_TX_START 0x8008 -#define KS8695_LAN_DMA_RX_START 0x800C -#define KS8695_LAN_TX_LIST 0x8010 -#define KS8695_LAN_RX_LIST 0x8014 -#define KS8695_LAN_MAC_LOW 0x8018 -#define KS8695_LAN_MAC_HIGH 0x801C -#define KS8695_LAN_MAC_ELOW 0X8080 -#define KS8695_LAN_MAC_EHIGH 0X8084 - -/*HPNA control registers offset difinitions*/ -#define KS8695_HPNA_DMA_TX 0xA000 -#define KS8695_HPNA_DMA_RX 0xA004 -#define KS8695_HPNA_DMA_TX_START 0xA008 -#define KS8695_HPNA_DMA_RX_START 0xA00C -#define KS8695_HPNA_TX_LIST 0xA010 -#define KS8695_HPNA_RX_LIST 0xA014 -#define KS8695_HPNA_MAC_LOW 0xA018 -#define KS8695_HPNA_MAC_HIGH 0xA01C -#define KS8695_HPNA_MAC_ELOW 0xA080 -#define KS8695_HPNA_MAC_EHIGH 0xA084 - -/*UART control registers offset difinitions*/ -#define KS8695_UART_RX_BUFFER 0xE000 -#define KS8695_UART_TX_HOLDING 0xE004 - -#define KS8695_UART_FIFO_CTRL 0xE008 -#define KS8695_UART_FIFO_TRIG01 0x00 -#define KS8695_UART_FIFO_TRIG04 0x80 -#define KS8695_UART_FIFO_TXRST 0x03 -#define KS8695_UART_FIFO_RXRST 0x02 -#define KS8695_UART_FIFO_FEN 0x01 - -#define KS8695_UART_LINE_CTRL 0xE00C -#define KS8695_UART_LINEC_BRK 0x40 -#define KS8695_UART_LINEC_EPS 0x10 -#define KS8695_UART_LINEC_PEN 0x08 -#define KS8695_UART_LINEC_STP2 0x04 -#define KS8695_UART_LINEC_WLEN8 0x03 -#define KS8695_UART_LINEC_WLEN7 0x02 -#define KS8695_UART_LINEC_WLEN6 0x01 -#define KS8695_UART_LINEC_WLEN5 0x00 - -#define KS8695_UART_MODEM_CTRL 0xE010 -#define KS8695_UART_MODEMC_RTS 0x02 -#define KS8695_UART_MODEMC_DTR 0x01 - -#define KS8695_UART_LINE_STATUS 0xE014 -#define KS8695_UART_LINES_TXFE 0x20 -#define KS8695_UART_LINES_BE 0x10 -#define KS8695_UART_LINES_FE 0x08 -#define KS8695_UART_LINES_PE 0x04 -#define KS8695_UART_LINES_OE 0x02 -#define KS8695_UART_LINES_RXFE 0x01 -#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE) - -#define KS8695_UART_MODEM_STATUS 0xE018 -#define KS8695_UART_MODEM_DCD 0x80 -#define KS8695_UART_MODEM_DSR 0x20 -#define KS8695_UART_MODEM_CTS 0x10 -#define KS8695_UART_MODEM_DDCD 0x08 -#define KS8695_UART_MODEM_DDSR 0x02 -#define KS8695_UART_MODEM_DCTS 0x01 -#define UART8695_MODEM_ANY 0xFF - -#define KS8695_UART_DIVISOR 0xE01C -#define KS8695_UART_STATUS 0xE020 - -/*Interrupt controlller registers offset difinitions*/ -#define KS8695_INT_CONTL 0xE200 -#define KS8695_INT_ENABLE 0xE204 -#define KS8695_INT_ENABLE_MODEM 0x0800 -#define KS8695_INT_ENABLE_ERR 0x0400 -#define KS8695_INT_ENABLE_RX 0x0200 -#define KS8695_INT_ENABLE_TX 0x0100 - -#define KS8695_INT_STATUS 0xE208 -#define KS8695_INT_WAN_PRIORITY 0xE20C -#define KS8695_INT_HPNA_PRIORITY 0xE210 -#define KS8695_INT_LAN_PRIORITY 0xE214 -#define KS8695_INT_TIMER_PRIORITY 0xE218 -#define KS8695_INT_UART_PRIORITY 0xE21C -#define KS8695_INT_EXT_PRIORITY 0xE220 -#define KS8695_INT_CHAN_PRIORITY 0xE224 -#define KS8695_INT_BUSERROR_PRO 0xE228 -#define KS8695_INT_MASK_STATUS 0xE22C -#define KS8695_FIQ_PEND_PRIORITY 0xE230 -#define KS8695_IRQ_PEND_PRIORITY 0xE234 - -/*timer registers offset difinitions*/ -#define KS8695_TIMER_CTRL 0xE400 -#define KS8695_TIMER1 0xE404 -#define KS8695_TIMER0 0xE408 -#define KS8695_TIMER1_PCOUNT 0xE40C -#define KS8695_TIMER0_PCOUNT 0xE410 - -/*GPIO registers offset difinitions*/ -#define KS8695_GPIO_MODE 0xE600 -#define KS8695_GPIO_CTRL 0xE604 -#define KS8695_GPIO_DATA 0xE608 - -/*SWITCH registers offset difinitions*/ -#define KS8695_SWITCH_CTRL0 0xE800 -#define KS8695_SWITCH_CTRL1 0xE804 -#define KS8695_SWITCH_PORT1 0xE808 -#define KS8695_SWITCH_PORT2 0xE80C -#define KS8695_SWITCH_PORT3 0xE810 -#define KS8695_SWITCH_PORT4 0xE814 -#define KS8695_SWITCH_PORT5 0xE818 -#define KS8695_SWITCH_AUTO0 0xE81C -#define KS8695_SWITCH_AUTO1 0xE820 -#define KS8695_SWITCH_LUE_CTRL 0xE824 -#define KS8695_SWITCH_LUE_HIGH 0xE828 -#define KS8695_SWITCH_LUE_LOW 0xE82C -#define KS8695_SWITCH_ADVANCED 0xE830 - -#define KS8695_SWITCH_LPPM12 0xE874 -#define KS8695_SWITCH_LPPM34 0xE878 - -/*host communication registers difinitions*/ -#define KS8695_DSCP_HIGH 0xE834 -#define KS8695_DSCP_LOW 0xE838 -#define KS8695_SWITCH_MAC_HIGH 0xE83C -#define KS8695_SWITCH_MAC_LOW 0xE840 - -/*miscellaneours registers difinitions*/ -#define KS8695_MANAGE_COUNTER 0xE844 -#define KS8695_MANAGE_DATA 0xE848 -#define KS8695_LAN12_POWERMAGR 0xE84C -#define KS8695_LAN34_POWERMAGR 0xE850 - -#define KS8695_DEVICE_ID 0xEA00 -#define KS8695_REVISION_ID 0xEA04 - -#define KS8695_MISC_CONTROL 0xEA08 -#define KS8695_WAN_CONTROL 0xEA0C -#define KS8695_WAN_POWERMAGR 0xEA10 -#define KS8695_WAN_PHY_CONTROL 0xEA14 -#define KS8695_WAN_PHY_STATUS 0xEA18 - -/* bus clock definitions*/ -#define KS8695_BUS_CLOCK_125MHZ 0x0 -#define KS8695_BUS_CLOCK_100MHZ 0x1 -#define KS8695_BUS_CLOCK_62MHZ 0x2 -#define KS8695_BUS_CLOCK_50MHZ 0x3 -#define KS8695_BUS_CLOCK_41MHZ 0x4 -#define KS8695_BUS_CLOCK_33MHZ 0x5 -#define KS8695_BUS_CLOCK_31MHZ 0x6 -#define KS8695_BUS_CLOCK_25MHZ 0x7 - -/* ------------------------------------------------------------------------------- - * definations for IRQ - * -------------------------------------------------------------------------------*/ - -#define KS8695_INT_EXT_INT0 2 -#define KS8695_INT_EXT_INT1 3 -#define KS8695_INT_EXT_INT2 4 -#define KS8695_INT_EXT_INT3 5 -#define KS8695_INT_TIMERINT0 6 -#define KS8695_INT_TIMERINT1 7 -#define KS8695_INT_UART_TX 8 -#define KS8695_INT_UART_RX 9 -#define KS8695_INT_UART_LINE_ERR 10 -#define KS8695_INT_UART_MODEMS 11 -#define KS8695_INT_LAN_STOP_RX 12 -#define KS8695_INT_LAN_STOP_TX 13 -#define KS8695_INT_LAN_BUF_RX_STATUS 14 -#define KS8695_INT_LAN_BUF_TX_STATUS 15 -#define KS8695_INT_LAN_RX_STATUS 16 -#define KS8695_INT_LAN_TX_STATUS 17 -#define KS8695_INT_HPAN_STOP_RX 18 -#define KS8695_INT_HPNA_STOP_TX 19 -#define KS8695_INT_HPNA_BUF_RX_STATUS 20 -#define KS8695_INT_HPNA_BUF_TX_STATUS 21 -#define KS8695_INT_HPNA_RX_STATUS 22 -#define KS8695_INT_HPNA_TX_STATUS 23 -#define KS8695_INT_BUS_ERROR 24 -#define KS8695_INT_WAN_STOP_RX 25 -#define KS8695_INT_WAN_STOP_TX 26 -#define KS8695_INT_WAN_BUF_RX_STATUS 27 -#define KS8695_INT_WAN_BUF_TX_STATUS 28 -#define KS8695_INT_WAN_RX_STATUS 29 -#define KS8695_INT_WAN_TX_STATUS 30 - -#define KS8695_INT_UART KS8695_INT_UART_TX - -/* ------------------------------------------------------------------------------- - * Interrupt bit positions - * - * ------------------------------------------------------------------------------- - */ - -#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 ) -#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 ) -#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 ) -#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 ) -#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 ) -#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 ) -#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX ) -#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX ) -#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR ) -#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS ) -#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX ) -#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX ) -#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS ) -#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS ) -#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) -#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) -#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX ) -#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX ) -#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS ) -#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS -#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS ) -#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS ) -#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR ) -#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX ) -#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX ) -#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS ) -#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS ) -#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS ) -#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS ) - -#define KS8695_SC_VALID_INT 0xFFFFFFFF -#define MAXIRQNUM 31 - -/* - * Timer definitions - * - * Use timer 1 & 2 - * (both run at 25MHz). - * - */ -#define TICKS_PER_uSEC 25 -#define mSEC_1 1000 -#define mSEC_10 (mSEC_1 * 10) - -#endif - -/* END */ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 8f6426bc1b..564441cbfa 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -1,7 +1,7 @@ /* * Common definitions for LPC32XX board configurations * - * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> + * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,6 +9,8 @@ #ifndef _LPC32XX_CONFIG_H #define _LPC32XX_CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD + /* Basic CPU architecture */ #define CONFIG_ARCH_CPU_INIT diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 791551841c..3b6a1696d8 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -36,6 +36,7 @@ #define CONFIG_SYS_LS102XA_USB1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET) +#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 #define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 @@ -61,6 +62,20 @@ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL +#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL +#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL +#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ +/* + * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) + * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. + */ +#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ + CONFIG_SYS_PCIE1_VIRT_ADDR) +#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ + CONFIG_SYS_PCIE2_VIRT_ADDR) + #ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index f70d568d46..3a64afce46 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -37,6 +37,43 @@ #define DCFG_DCSR_PORCR1 0 +/* + * Define default values for some CCSR macros to make header files cleaner + * + * To completely disable CCSR relocation in a board header file, define + * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS + * to a value that is the same as CONFIG_SYS_CCSRBAR. + */ + +#ifdef CONFIG_SYS_CCSRBAR_PHYS +#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly." +#endif + +#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#undef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif + +#ifndef CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#else +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR +#endif + +#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CONFIG_SYS_CCSRBAR_PHYS_LOW) + struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; @@ -133,8 +170,7 @@ struct ccsr_scfg { u32 pex1rdmmsgrqsr; u32 pex2rdmmsgrqsr; u32 spimsiclrcr; - u32 pex1mscportsr; - u32 pex2mscportsr; + u32 pexmscportsr[2]; u32 pex2pmwrcr; u32 resv5[24]; u32 mac1_streamid; diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h index abd70fc706..fa571b3a38 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h @@ -7,11 +7,68 @@ #ifndef __FSL_LS102XA_STREAM_ID_H_ #define __FSL_LS102XA_STREAM_ID_H_ +#include <fsl_sec.h> + +#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ + { .compat = name, \ + .id = { idA }, .num_ids = 1, \ + .reg_offset = off + CONFIG_SYS_IMMR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + +#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ + { .compat = name, \ + .id = { idA, idB }, .num_ids = 2, \ + .reg_offset = off + CONFIG_SYS_IMMR, \ + .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + } + +/* + * handle both old and new versioned SEC properties: + * "fsl,secX.Y" became "fsl,sec-vX.Y" during development + */ +#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \ + SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \ + offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \ + SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum) + +/* This is a bit evil since we treat rtic param as both a string & hex value */ +#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ + SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ + SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) + +#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ + SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \ + offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, 0) + +struct liodn_id_table { + const char *compat; + u32 id[2]; + u8 num_ids; + phys_addr_t compat_offset; + unsigned long reg_offset; +}; + struct smmu_stream_id { uint16_t offset; uint16_t stream_id; char dev_name[32]; }; +void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size); void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num); #endif diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h deleted file mode 100644 index 42a52bc36c..0000000000 --- a/arch/arm/include/asm/arch-mb86r0x/hardware.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2007 - * - * Author : Carsten Schneider, mycable GmbH - * <cs@mycable.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <linux/sizes.h> -#include <asm/arch/mb86r0x.h> - -#endif diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h deleted file mode 100644 index 7fec9715b1..0000000000 --- a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h +++ /dev/null @@ -1,599 +0,0 @@ -/* - * (C) Copyright 2007 - * - * mb86r0x definitions - * - * Author : Carsten Schneider, mycable GmbH - * <cs@mycable.de> - * - * (C) Copyright 2010 - * Matthias Weisser <weisserm@arcor.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef MB86R0X_H -#define MB86R0X_H - -#ifndef __ASSEMBLY__ - -/* GPIO registers */ -struct mb86r0x_gpio { - uint32_t gpdr0; - uint32_t gpdr1; - uint32_t gpdr2; - uint32_t res; - uint32_t gpddr0; - uint32_t gpddr1; - uint32_t gpddr2; -}; - -/* PWM registers */ -struct mb86r0x_pwm { - uint32_t bcr; - uint32_t tpr; - uint32_t pr; - uint32_t dr; - uint32_t cr; - uint32_t sr; - uint32_t ccr; - uint32_t ir; -}; - -/* The mb86r0x chip control (CCNT) register set. */ -struct mb86r0x_ccnt { - uint32_t ccid; - uint32_t csrst; - uint32_t pad0[2]; - uint32_t cist; - uint32_t cistm; - uint32_t cgpio_ist; - uint32_t cgpio_istm; - uint32_t cgpio_ip; - uint32_t cgpio_im; - uint32_t caxi_bw; - uint32_t caxi_ps; - uint32_t cmux_md; - uint32_t cex_pin_st; - uint32_t cmlb; - uint32_t pad1[1]; - uint32_t cusb; - uint32_t pad2[41]; - uint32_t cbsc; - uint32_t cdcrc; - uint32_t cmsr0; - uint32_t cmsr1; - uint32_t pad3[2]; -}; - -/* The mb86r0x clock reset generator */ -struct mb86r0x_crg { - uint32_t crpr; - uint32_t pad0; - uint32_t crwr; - uint32_t crsr; - uint32_t crda; - uint32_t crdb; - uint32_t crha; - uint32_t crpa; - uint32_t crpb; - uint32_t crhb; - uint32_t cram; -}; - -/* The mb86r0x timer */ -struct mb86r0x_timer { - uint32_t load; - uint32_t value; - uint32_t control; - uint32_t intclr; - uint32_t ris; - uint32_t mis; - uint32_t bgload; -}; - -/* mb86r0x gdc display controller */ -struct mb86r0x_gdc_dsp { - /* Display settings */ - uint32_t dcm0; - uint16_t pad00; - uint16_t htp; - uint16_t hdp; - uint16_t hdb; - uint16_t hsp; - uint8_t hsw; - uint8_t vsw; - uint16_t pad01; - uint16_t vtr; - uint16_t vsp; - uint16_t vdp; - uint16_t wx; - uint16_t wy; - uint16_t ww; - uint16_t wh; - - /* Layer 0 */ - uint32_t l0m; - uint32_t l0oa; - uint32_t l0da; - uint16_t l0dx; - uint16_t l0dy; - - /* Layer 1 */ - uint32_t l1m; - uint32_t cbda0; - uint32_t cbda1; - uint32_t pad02; - - /* Layer 2 */ - uint32_t l2m; - uint32_t l2oa0; - uint32_t l2da0; - uint32_t l2oa1; - uint32_t l2da1; - uint16_t l2dx; - uint16_t l2dy; - - /* Layer 3 */ - uint32_t l3m; - uint32_t l3oa0; - uint32_t l3da0; - uint32_t l3oa1; - uint32_t l3da1; - uint16_t l3dx; - uint16_t l3dy; - - /* Layer 4 */ - uint32_t l4m; - uint32_t l4oa0; - uint32_t l4da0; - uint32_t l4oa1; - uint32_t l4da1; - uint16_t l4dx; - uint16_t l4dy; - - /* Layer 5 */ - uint32_t l5m; - uint32_t l5oa0; - uint32_t l5da0; - uint32_t l5oa1; - uint32_t l5da1; - uint16_t l5dx; - uint16_t l5dy; - - /* Cursor */ - uint16_t cutc; - uint8_t cpm; - uint8_t csize; - uint32_t cuoa0; - uint16_t cux0; - uint16_t cuy0; - uint32_t cuoa1; - uint16_t cux1; - uint16_t cuy1; - - /* Layer blending */ - uint32_t l0bld; - uint32_t pad03; - uint32_t l0tc; - uint16_t l3tc; - uint16_t l2tc; - uint32_t pad04[15]; - - /* Display settings */ - uint32_t dcm1; - uint32_t dcm2; - uint32_t dcm3; - uint32_t pad05; - - /* Layer 0 extended */ - uint32_t l0em; - uint16_t l0wx; - uint16_t l0wy; - uint16_t l0ww; - uint16_t l0wh; - uint32_t pad06; - - /* Layer 1 extended */ - uint32_t l1em; - uint16_t l1wx; - uint16_t l1wy; - uint16_t l1ww; - uint16_t l1wh; - uint32_t pad07; - - /* Layer 2 extended */ - uint32_t l2em; - uint16_t l2wx; - uint16_t l2wy; - uint16_t l2ww; - uint16_t l2wh; - uint32_t pad08; - - /* Layer 3 extended */ - uint32_t l3em; - uint16_t l3wx; - uint16_t l3wy; - uint16_t l3ww; - uint16_t l3wh; - uint32_t pad09; - - /* Layer 4 extended */ - uint32_t l4em; - uint16_t l4wx; - uint16_t l4wy; - uint16_t l4ww; - uint16_t l4wh; - uint32_t pad10; - - /* Layer 5 extended */ - uint32_t l5em; - uint16_t l5wx; - uint16_t l5wy; - uint16_t l5ww; - uint16_t l5wh; - uint32_t pad11; - - /* Multi screen control */ - uint32_t msc; - uint32_t pad12[3]; - uint32_t dls; - uint32_t dbgc; - - /* Layer blending */ - uint32_t l1bld; - uint32_t l2bld; - uint32_t l3bld; - uint32_t l4bld; - uint32_t l5bld; - uint32_t pad13; - - /* Extended transparency control */ - uint32_t l0etc; - uint32_t l1etc; - uint32_t l2etc; - uint32_t l3etc; - uint32_t l4etc; - uint32_t l5etc; - uint32_t pad14[10]; - - /* YUV coefficients */ - uint32_t l1ycr0; - uint32_t l1ycr1; - uint32_t l1ycg0; - uint32_t l1ycg1; - uint32_t l1ycb0; - uint32_t l1ycb1; - uint32_t pad15[130]; - - /* Layer palletes */ - uint32_t l0pal[256]; - uint32_t l1pal[256]; - uint32_t pad16[256]; - uint32_t l2pal[256]; - uint32_t l3pal[256]; - uint32_t pad17[256]; - - /* PWM settings */ - uint32_t vpwmm; - uint16_t vpwms; - uint16_t vpwme; - uint32_t vpwmc; - uint32_t pad18[253]; -}; - -/* mb86r0x gdc capture controller */ -struct mb86r0x_gdc_cap { - uint32_t vcm; - uint32_t csc; - uint32_t vcs; - uint32_t pad01; - - uint32_t cbm; - uint32_t cboa; - uint32_t cbla; - uint16_t cihstr; - uint16_t civstr; - uint16_t cihend; - uint16_t civend; - uint32_t pad02; - - uint32_t chp; - uint32_t cvp; - uint32_t pad03[4]; - - uint32_t clpf; - uint32_t pad04; - uint32_t cmss; - uint32_t cmds; - uint32_t pad05[12]; - - uint32_t rgbhc; - uint32_t rgbhen; - uint32_t rgbven; - uint32_t pad06; - uint32_t rgbs; - uint32_t pad07[11]; - - uint32_t rgbcmy; - uint32_t rgbcmcb; - uint32_t rgbcmcr; - uint32_t rgbcmb; - uint32_t pad08[12 + 1984]; -}; - -/* mb86r0x gdc draw */ -struct mb86r0x_gdc_draw { - uint32_t ys; - uint32_t xs; - uint32_t dxdy; - uint32_t xus; - uint32_t dxudy; - uint32_t xls; - uint32_t dxldy; - uint32_t usn; - uint32_t lsn; - uint32_t pad01[7]; - uint32_t rs; - uint32_t drdx; - uint32_t drdy; - uint32_t gs; - uint32_t dgdx; - uint32_t dgdy; - uint32_t bs; - uint32_t dbdx; - uint32_t dbdy; - uint32_t pad02[7]; - uint32_t zs; - uint32_t dzdx; - uint32_t dzdy; - uint32_t pad03[13]; - uint32_t ss; - uint32_t dsdx; - uint32_t dsdy; - uint32_t ts; - uint32_t dtdx; - uint32_t dtdy; - uint32_t qs; - uint32_t dqdx; - uint32_t dqdy; - uint32_t pad04[23]; - uint32_t lpn; - uint32_t lxs; - uint32_t lxde; - uint32_t lys; - uint32_t lyde; - uint32_t lzs; - uint32_t lzde; - uint32_t pad05[13]; - uint32_t pxdc; - uint32_t pydc; - uint32_t pzdc; - uint32_t pad06[25]; - uint32_t rxs; - uint32_t rys; - uint32_t rsizex; - uint32_t rsizey; - uint32_t pad07[12]; - uint32_t saddr; - uint32_t sstride; - uint32_t srx; - uint32_t sry; - uint32_t daddr; - uint32_t dstride; - uint32_t drx; - uint32_t dry; - uint32_t brsizex; - uint32_t brsizey; - uint32_t tcolor; - uint32_t pad08[93]; - uint32_t blpo; - uint32_t pad09[7]; - uint32_t ctr; - uint32_t ifsr; - uint32_t ifcnt; - uint32_t sst; - uint32_t ds; - uint32_t pst; - uint32_t est; - uint32_t pad10; - uint32_t mdr0; - uint32_t mdr1; - uint32_t mdr2; - uint32_t mdr3; - uint32_t mdr4; - uint32_t pad14[2]; - uint32_t mdr7; - uint32_t fbr; - uint32_t xres; - uint32_t zbr; - uint32_t tbr; - uint32_t pfbr; - uint32_t cxmin; - uint32_t cxmax; - uint32_t cymin; - uint32_t cymax; - uint32_t txs; - uint32_t tis; - uint32_t toa; - uint32_t sho; - uint32_t abr; - uint32_t pad15[2]; - uint32_t fc; - uint32_t bc; - uint32_t alf; - uint32_t blp; - uint32_t pad16; - uint32_t tbc; - uint32_t pad11[42]; - uint32_t lx0dc; - uint32_t ly0dc; - uint32_t lx1dc; - uint32_t ly1dc; - uint32_t pad12[12]; - uint32_t x0dc; - uint32_t y0dc; - uint32_t x1dc; - uint32_t y1dc; - uint32_t x2dc; - uint32_t y2dc; - uint32_t pad13[666]; -}; - -/* mb86r0x gdc geometry engine */ -struct mb86r0x_gdc_geom { - uint32_t gctr; - uint32_t pad00[15]; - uint32_t gmdr0; - uint32_t gmdr1; - uint32_t gmdr2; - uint32_t pad01[237]; - uint32_t dfifog; - uint32_t pad02[767]; -}; - -/* mb86r0x gdc */ -struct mb86r0x_gdc { - uint32_t pad00[2]; - uint32_t lts; - uint32_t pad01; - uint32_t lsta; - uint32_t pad02[3]; - uint32_t ist; - uint32_t imask; - uint32_t pad03[6]; - uint32_t lsa; - uint32_t lco; - uint32_t lreq; - - uint32_t pad04[16*1024 - 19]; - struct mb86r0x_gdc_dsp dsp0; - struct mb86r0x_gdc_dsp dsp1; - uint32_t pad05[4*1024 - 2]; - uint32_t vccc; - uint32_t vcsr; - struct mb86r0x_gdc_cap cap0; - struct mb86r0x_gdc_cap cap1; - uint32_t pad06[4*1024]; - uint32_t texture_base[16*1024]; - struct mb86r0x_gdc_draw draw; - uint32_t pad07[7*1024]; - struct mb86r0x_gdc_geom geom; - uint32_t pad08[7*1024]; -}; - -/* mb86r0x ddr2c */ -struct mb86r0x_ddr2c { - uint16_t dric; - uint16_t dric1; - uint16_t dric2; - uint16_t drca; - uint16_t drcm; - uint16_t drcst1; - uint16_t drcst2; - uint16_t drcr; - uint16_t pad00[8]; - uint16_t drcf; - uint16_t pad01[7]; - uint16_t drasr; - uint16_t pad02[15]; - uint16_t drims; - uint16_t pad03[7]; - uint16_t dros; - uint16_t pad04; - uint16_t dribsodt1; - uint16_t dribsocd; - uint16_t dribsocd2; - uint16_t pad05[3]; - uint16_t droaba; - uint16_t pad06[9]; - uint16_t drobs; - uint16_t pad07[5]; - uint16_t drimr1; - uint16_t drimr2; - uint16_t drimr3; - uint16_t drimr4; - uint16_t droisr1; - uint16_t droisr2; -}; - -/* mb86r0x memc */ -struct mb86r0x_memc { - uint32_t mcfmode[8]; - uint32_t mcftim[8]; - uint32_t mcfarea[8]; -}; - -#endif /* __ASSEMBLY__ */ - -/* - * Physical Address Defines - */ -#define MB86R0x_DDR2_BASE 0xf3000000 -#define MB86R0x_GDC_BASE 0xf1fc0000 -#define MB86R0x_CCNT_BASE 0xfff42000 -#define MB86R0x_CAN0_BASE 0xfff54000 -#define MB86R0x_CAN1_BASE 0xfff55000 -#define MB86R0x_I2C0_BASE 0xfff56000 -#define MB86R0x_I2C1_BASE 0xfff57000 -#define MB86R0x_EHCI_BASE 0xfff80000 -#define MB86R0x_OHCI_BASE 0xfff81000 -#define MB86R0x_IRC1_BASE 0xfffb0000 -#define MB86R0x_MEMC_BASE 0xfffc0000 -#define MB86R0x_TIMER_BASE 0xfffe0000 -#define MB86R0x_UART0_BASE 0xfffe1000 -#define MB86R0x_UART1_BASE 0xfffe2000 -#define MB86R0x_IRCE_BASE 0xfffe4000 -#define MB86R0x_CRG_BASE 0xfffe7000 -#define MB86R0x_IRC0_BASE 0xfffe8000 -#define MB86R0x_GPIO_BASE 0xfffe9000 -#define MB86R0x_PWM0_BASE 0xfff41000 -#define MB86R0x_PWM1_BASE 0xfff41100 - -#define MB86R0x_CRSR_SWRSTREQ (1 << 1) - -/* - * Timer register bits - */ -#define MB86R0x_TIMER_ENABLE (1 << 7) -#define MB86R0x_TIMER_MODE_MSK (1 << 6) -#define MB86R0x_TIMER_MODE_FR (0 << 6) -#define MB86R0x_TIMER_MODE_PD (1 << 6) - -#define MB86R0x_TIMER_INT_EN (1 << 5) -#define MB86R0x_TIMER_PRS_MSK (3 << 2) -#define MB86R0x_TIMER_PRS_4S (1 << 2) -#define MB86R0x_TIMER_PRS_8S (1 << 3) -#define MB86R0x_TIMER_SIZE_32 (1 << 1) -#define MB86R0x_TIMER_ONE_SHT (1 << 0) - -/* - * Clock reset generator bits - */ -#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8) -#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0) -/* - * DDR2 controller bits - */ -#define MB86R0x_DDR2_DRCI_DRINI (1 << 15) -#define MB86R0x_DDR2_DRCI_CKEN (1 << 14) -#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0) -#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \ - MB86R0x_DDR2_DRCI_CKEN | \ - MB86R0x_DDR2_DRCI_DRCMD) -#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \ - MB86R0x_DDR2_DRCI_CKEN) -#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN -#endif /* MB86R0X_H */ diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h deleted file mode 100644 index 1eed7b1d56..0000000000 --- a/arch/arm/include/asm/arch-pantheon/config.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PANTHEON_CONFIG_H -#define _PANTHEON_CONFIG_H - -#include <asm/arch/pantheon.h> - -/* default Dcache Line length for pantheon */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ -#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ -#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ -#define MV_MFPR_BASE PANTHEON_MFPR_BASE -#define MV_UART_CONSOLE_BASE PANTHEON_UART1_BASE -#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register - represents UART Unit Enable */ -/* - * I2C definition - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MV 1 -#define CONFIG_MV_I2C_REG 0xd4011000 -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 0 -#define CONFIG_SYS_I2C_SLAVE 0xfe -#endif - -/* - * MMC definition - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_CMD_FAT 1 -#define CONFIG_MMC 1 -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_SDHCI 1 -#define CONFIG_MMC_SDHCI_IO_ACCESSORS 1 -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000 -#define CONFIG_MMC_SDMA 1 -#define CONFIG_MV_SDHCI 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_EFI_PARTITION 1 -#define CONFIG_SYS_MMC_NUM 2 -#define CONFIG_SYS_MMC_BASE {0xD4280000, 0xd4281000} -#endif - -#endif /* _PANTHEON_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h deleted file mode 100644 index 3ccdf8a359..0000000000 --- a/arch/arm/include/asm/arch-pantheon/cpu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PANTHEON_CPU_H -#define _PANTHEON_CPU_H - -#include <asm/io.h> -#include <asm/system.h> - -/* - * Main Power Management (MPMU) Registers - * Refer Register Datasheet 9.1 - */ -struct panthmpmu_registers { - u8 pad0[0x0024]; - u32 ccgr; /*0x0024*/ - u8 pad1[0x0200 - 0x024 - 4]; - u32 wdtpcr; /*0x0200*/ - u8 pad2[0x1020 - 0x200 - 4]; - u32 aprr; /*0x1020*/ - u32 acgr; /*0x1024*/ -}; - -/* - * Application Power Management (APMU) Registers - * Refer Register Datasheet 9.2 - */ -struct panthapmu_registers { - u8 pad0[0x0054]; - u32 sd1; /*0x0054*/ - u8 pad1[0x00e0 - 0x054 - 4]; - u32 sd3; /*0x00e0*/ -}; - -/* - * APB Clock Reset/Control Registers - * Refer Register Datasheet 6.14 - */ -struct panthapb_registers { - u32 uart0; /*0x000*/ - u32 uart1; /*0x004*/ - u32 gpio; /*0x008*/ - u8 pad0[0x02c - 0x08 - 4]; - u32 twsi; /*0x02c*/ - u8 pad1[0x034 - 0x2c - 4]; - u32 timers; /*0x034*/ -}; - -/* - * CPU Interface Registers - * Refer Register Datasheet 4.3 - */ -struct panthcpu_registers { - u32 chip_id; /* Chip Id Reg */ - u32 pad; - u32 cpu_conf; /* CPU Conf Reg */ - u32 pad1; - u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ - u32 pad2; - u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ - u32 mcb_conf; /* MCB Conf Reg */ - u32 sys_boot_ctl; /* Sytem Boot Control */ -}; - -/* - * Functions - */ -u32 panth_sdram_base(int); -u32 panth_sdram_size(int); -int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); - -#endif /* _PANTHEON_CPU_H */ diff --git a/arch/arm/include/asm/arch-pantheon/gpio.h b/arch/arm/include/asm/arch-pantheon/gpio.h deleted file mode 100644 index e69de29bb2..0000000000 --- a/arch/arm/include/asm/arch-pantheon/gpio.h +++ /dev/null diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h deleted file mode 100644 index 7909d53d46..0000000000 --- a/arch/arm/include/asm/arch-pantheon/mfp.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Based on arch/arm/include/asm/arch-armada100/mfp.h - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PANTHEON_MFP_H -#define __PANTHEON_MFP_H - -/* - * Frequently used MFP Configuration macros for all PANTHEON family of SoCs - * - * offset, pull,pF, drv,dF, edge,eF ,afn,aF - */ -/* UART2 */ -#define MFP47_UART2_RXD (MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP48_UART2_TXD (MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP53_CI2C_SCL (MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* More macros can be defined here... */ -#define MFP_MMC1_DAT7 (MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_DAT6 (MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_DAT5 (MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_DAT4 (MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_DAT3 (MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_DAT2 (MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_DAT1 (MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_DAT0 (MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_CMD (MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_CLK (MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_CD (MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_WP (MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM) - -#define MFP_PIN_MAX 117 -#endif diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h deleted file mode 100644 index c3a71bfce4..0000000000 --- a/arch/arm/include/asm/arch-pantheon/pantheon.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Lei Wen <leiwen@marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PANTHEON_H -#define _PANTHEON_H - -/* Common APB clock register bit definitions */ -#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ -#define APBC_FNCLK (1<<1) /* Functional Clock Enable */ -#define APBC_RST (1<<2) /* Reset Generation */ -/* Functional Clock Selection Mask */ -#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) - -/* Common APMU register bit definitions */ -#define APMU_PERI_CLK (1<<4) /* Peripheral Clock Enable */ -#define APMU_AXI_CLK (1<<3) /* AXI Clock Enable*/ -#define APMU_PERI_RST (1<<1) /* Peripheral Reset */ -#define APMU_AXI_RST (1<<0) /* AXI Reset */ - -/* Register Base Addresses */ -#define PANTHEON_DRAM_BASE 0xB0000000 -#define PANTHEON_TIMER_BASE 0xD4014000 -#define PANTHEON_WD_TIMER_BASE 0xD4080000 -#define PANTHEON_APBC_BASE 0xD4015000 -#define PANTHEON_UART1_BASE 0xD4017000 -#define PANTHEON_UART2_BASE 0xD4018000 -#define PANTHEON_GPIO_BASE 0xD4019000 -#define PANTHEON_MFPR_BASE 0xD401E000 -#define PANTHEON_MPMU_BASE 0xD4050000 -#define PANTHEON_APMU_BASE 0xD4282800 -#define PANTHEON_CPU_BASE 0xD4282C00 - -#endif /* _PANTHEON_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index d297ed0f73..c28ee0528f 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -144,7 +144,16 @@ struct sunxi_ccm_reg { #define PLL1_CFG_DEFAULT 0xa1005000 +#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I +/* + * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz, + * halving the mbus frequency, so set it to 300 MHz ourselves and base the + * mbus divider on that. + */ +#define PLL6_CFG_DEFAULT 0xa1009900 +#else #define PLL6_CFG_DEFAULT 0xa1009911 +#endif /* nand clock */ #define NAND_CLK_SRC_OSC24 0 diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index 7ff43e6d3a..aedd1941d5 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -25,31 +25,7 @@ #endif unsigned long sunxi_dram_init(void); - -/* - * Wait up to 1s for value to be set in given part of reg. - */ -static inline void mctl_await_completion(u32 *reg, u32 mask, u32 val) -{ - unsigned long tmo = timer_get_us() + 1000000; - - while ((readl(reg) & mask) != val) { - if (timer_get_us() > tmo) - panic("Timeout initialising DRAM\n"); - } -} - -/* - * Test if memory at offset offset matches memory at begin of DRAM - */ -static inline bool mctl_mem_matches(u32 offset) -{ - /* Try to write different values to RAM at two addresses */ - writel(0, CONFIG_SYS_SDRAM_BASE); - writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset); - /* Check if the same value is actually observed when reading back */ - return readl(CONFIG_SYS_SDRAM_BASE) == - readl(CONFIG_SYS_SDRAM_BASE + offset); -} +void mctl_await_completion(u32 *reg, u32 mask, u32 val); +bool mctl_mem_matches(u32 offset); #endif /* _SUNXI_DRAM_H */ diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h index c3e636e1d9..60a5bd8c85 100644 --- a/arch/arm/include/asm/arch-sunxi/sys_proto.h +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h @@ -13,4 +13,14 @@ void sdelay(unsigned long); +/* return_to_fel() - Return to BROM from SPL + * + * This returns back into the BROM after U-Boot SPL has performed its initial + * init. It uses the provided lr and sp to do so. + * + * @lr: BROM link register value (return address) + * @sp: BROM stack pointer + */ +void return_to_fel(uint32_t lr, uint32_t sp); + #endif diff --git a/arch/arm/include/asm/arch-tnetv107x/clock.h b/arch/arm/include/asm/arch-tnetv107x/clock.h deleted file mode 100644 index dfc3b1bfa5..0000000000 --- a/arch/arm/include/asm/arch-tnetv107x/clock.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * TNETV107X: Clock APIs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#define PSC_MDCTL_NEXT_SWRSTDISABLE 0x0 -#define PSC_MDCTL_NEXT_SYNCRST 0x1 -#define PSC_MDCTL_NEXT_DISABLE 0x2 -#define PSC_MDCTL_NEXT_ENABLE 0x3 - -#define CONFIG_SYS_INT_OSC_FREQ 24000000 - -#ifndef __ASSEMBLY__ - -/* PLL identifiers */ -enum pll_type_e { - SYS_PLL, - TDM_PLL, - ETH_PLL -}; - -/* PLL configuration data */ -struct pll_init_data { - int pll; - int internal_osc; - unsigned long pll_freq; - unsigned long div_freq[10]; -}; - -void init_plls(int num_pll, struct pll_init_data *config); -int lpsc_status(unsigned int mod); -void lpsc_control(int mod, unsigned long state, int lrstz); -unsigned long clk_get_rate(unsigned int clk); -unsigned long clk_round_rate(unsigned int clk, unsigned long hz); -int clk_set_rate(unsigned int clk, unsigned long hz); - -static inline void clk_enable(unsigned int mod) -{ - lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1); -} - -static inline void clk_disable(unsigned int mod) -{ - lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1); -} - -#endif - -#endif diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h deleted file mode 100644 index d458e0bdf0..0000000000 --- a/arch/arm/include/asm/arch-tnetv107x/hardware.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * TNETV107X: Hardware information - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#ifndef __ASSEMBLY__ - -#include <linux/sizes.h> - -#define ASYNC_EMIF_NUM_CS 4 -#define ASYNC_EMIF_MODE_NOR 0 -#define ASYNC_EMIF_MODE_NAND 1 -#define ASYNC_EMIF_MODE_ONENAND 2 -#define ASYNC_EMIF_PRESERVE -1 - -struct async_emif_config { - unsigned mode; - unsigned select_strobe; - unsigned extend_wait; - unsigned wr_setup; - unsigned wr_strobe; - unsigned wr_hold; - unsigned rd_setup; - unsigned rd_strobe; - unsigned rd_hold; - unsigned turn_around; - enum { - ASYNC_EMIF_8 = 0, - ASYNC_EMIF_16 = 1, - ASYNC_EMIF_32 = 2, - } width; -}; - -void init_async_emif(int num_cs, struct async_emif_config *config); - -int wdt_start(unsigned long msecs); -int wdt_stop(void); -int wdt_kick(void); - -#endif - -/* Chip configuration unlock codes and registers */ -#define TNETV107X_KICK0 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38) -#define TNETV107X_KICK1 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c) -#define TNETV107X_PINMUX(n) (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4) -#define TNETV107X_KICK0_MAGIC 0x83e70b13 -#define TNETV107X_KICK1_MAGIC 0x95a4f1e0 - -/* Module base addresses */ -#define TNETV107X_TPCC_BASE 0x01C00000 -#define TNETV107X_TPTC0_BASE 0x01C10000 -#define TNETV107X_TPTC1_BASE 0x01C10400 -#define TNETV107X_INTC_BASE 0x03000000 -#define TNETV107X_LCD_CONTROLLER_BASE 0x08030000 -#define TNETV107X_INTD_BASE 0x08038000 -#define TNETV107X_INTD_IPC_BASE 0x08038000 -#define TNETV107X_INTD_FAST_BASE 0x08039000 -#define TNETV107X_INTD_ASYNC_BASE 0x0803A000 -#define TNETV107X_INTD_SLOW_BASE 0x0803B000 -#define TNETV107X_PKA_BASE 0x08040000 -#define TNETV107X_RNG_BASE 0x08044000 -#define TNETV107X_TIMER0_BASE 0x08086500 -#define TNETV107X_TIMER1_BASE 0x08086600 -#define TNETV107X_WDT0_ARM_BASE 0x08086700 -#define TNETV107X_WDT1_DSP_BASE 0x08086800 -#define TNETV107X_CHIP_CONFIG_SYS_BASE 0x08087000 -#define TNETV107X_GPIO_BASE 0x08088000 -#define TNETV107X_UART1_BASE 0x08088400 -#define TNETV107X_TOUCHSCREEN_BASE 0x08088500 -#define TNETV107X_SDIO0_BASE 0x08088700 -#define TNETV107X_SDIO1_BASE 0x08088800 -#define TNETV107X_MDIO_BASE 0x08088900 -#define TNETV107X_KEYPAD_BASE 0x08088A00 -#define TNETV107X_SSP_BASE 0x08088C00 -#define TNETV107X_CLOCK_CONTROL_BASE 0x0808A000 -#define TNETV107X_PSC_BASE 0x0808B000 -#define TNETV107X_TDM0_BASE 0x08100000 -#define TNETV107X_TDM1_BASE 0x08100100 -#define TNETV107X_MCDMA_BASE 0x08108000 -#define TNETV107X_UART0_DMA_BASE 0x08108200 -#define TNETV107X_USBSS_BASE 0x08120000 -#define TNETV107X_VLYNQ_CONTROL_BASE 0x0810D000 -#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000 -#define TNETV107X_VLYNQ_MEM_MAP_BASE 0x0C000000 -#define TNETV107X_IMCOP_BASE 0x01CC0000 -#define TNETV107X_MBX_LITE_BASE 0x07000000 -#define TNETV107X_ETHSS_BASE 0x0803C000 -#define TNETV107X_CPSW_BASE 0x0803C000 -#define TNETV107X_SPF_BASE 0x0803C800 -#define TNETV107X_IOPU_ETHSS_BASE 0x0803D000 -#define TNETV107X_VTP_CNTRL_0 0x0803D800 -#define TNETV107X_VTP_CNTRL_1 0x0803D900 -#define TNETV107X_UART2_DMA_BASE 0x08108400 -#define TNETV107X_INTERNAL_MEMORY 0x20000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 -#define TNETV107X_DDR_EMIF_DATA_BASE 0x80000000 -#define TNETV107X_DDR_EMIF_CONTROL_BASE 0x90000000 - -/* LPSC module definitions */ -#define TNETV107X_LPSC_ARM 0 -#define TNETV107X_LPSC_GEM 1 -#define TNETV107X_LPSC_DDR2_PHY 2 -#define TNETV107X_LPSC_TPCC 3 -#define TNETV107X_LPSC_TPTC0 4 -#define TNETV107X_LPSC_TPTC1 5 -#define TNETV107X_LPSC_RAM 6 -#define TNETV107X_LPSC_MBX_LITE 7 -#define TNETV107X_LPSC_LCD 8 -#define TNETV107X_LPSC_ETHSS 9 -#define TNETV107X_LPSC_AEMIF 10 -#define TNETV107X_LPSC_CHIP_CFG 11 -#define TNETV107X_LPSC_TSC 12 -#define TNETV107X_LPSC_ROM 13 -#define TNETV107X_LPSC_UART2 14 -#define TNETV107X_LPSC_PKTSEC 15 -#define TNETV107X_LPSC_SECCTL 16 -#define TNETV107X_LPSC_KEYMGR 17 -#define TNETV107X_LPSC_KEYPAD 18 -#define TNETV107X_LPSC_GPIO 19 -#define TNETV107X_LPSC_MDIO 20 -#define TNETV107X_LPSC_SDIO0 21 -#define TNETV107X_LPSC_UART0 22 -#define TNETV107X_LPSC_UART1 23 -#define TNETV107X_LPSC_TIMER0 24 -#define TNETV107X_LPSC_TIMER1 25 -#define TNETV107X_LPSC_WDT_ARM 26 -#define TNETV107X_LPSC_WDT_DSP 27 -#define TNETV107X_LPSC_SSP 28 -#define TNETV107X_LPSC_TDM0 29 -#define TNETV107X_LPSC_VLYNQ 30 -#define TNETV107X_LPSC_MCDMA 31 -#define TNETV107X_LPSC_USB0 32 -#define TNETV107X_LPSC_TDM1 33 -#define TNETV107X_LPSC_DEBUGSS 34 -#define TNETV107X_LPSC_ETHSS_RGMII 35 -#define TNETV107X_LPSC_SYSTEM 36 -#define TNETV107X_LPSC_IMCOP 37 -#define TNETV107X_LPSC_SPARE 38 -#define TNETV107X_LPSC_SDIO1 39 -#define TNETV107X_LPSC_USB1 40 -#define TNETV107X_LPSC_USBSS 41 -#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42 -#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43 -#define TNETV107X_LPSC_MAX 44 - -/* Interrupt controller */ -#define INTC_GLB_EN (TNETV107X_INTC_BASE + 0x10) -#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500) -#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380) - -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-tnetv107x/mux.h b/arch/arm/include/asm/arch-tnetv107x/mux.h deleted file mode 100644 index 3f832c4147..0000000000 --- a/arch/arm/include/asm/arch-tnetv107x/mux.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * TNETV107X: Pinmux APIs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MUX_H -#define __ASM_ARCH_MUX_H - -struct pin_config { - unsigned char reg_index; - unsigned char mask_offset; - unsigned char mode; -}; - -#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \ - { reg, offset, mux_mode } - -int mux_select_pin(short index); -int mux_select_pins(const short *pins); - -enum tnetv107x_pin_mux_index { - TNETV107X_PIN_ASR_A00, - TNETV107X_PIN_GPIO32, - TNETV107X_PIN_ASR_A01, - TNETV107X_PIN_GPIO33, - TNETV107X_PIN_ASR_A02, - TNETV107X_PIN_GPIO34, - TNETV107X_PIN_ASR_A03, - TNETV107X_PIN_GPIO35, - TNETV107X_PIN_ASR_A04, - TNETV107X_PIN_GPIO36, - TNETV107X_PIN_ASR_A05, - TNETV107X_PIN_GPIO37, - TNETV107X_PIN_ASR_A06, - TNETV107X_PIN_GPIO38, - TNETV107X_PIN_ASR_A07, - TNETV107X_PIN_GPIO39, - TNETV107X_PIN_ASR_A08, - TNETV107X_PIN_GPIO40, - TNETV107X_PIN_ASR_A09, - TNETV107X_PIN_GPIO41, - TNETV107X_PIN_ASR_A10, - TNETV107X_PIN_GPIO42, - TNETV107X_PIN_ASR_A11, - TNETV107X_PIN_BOOT_STRP_0, - TNETV107X_PIN_ASR_A12, - TNETV107X_PIN_BOOT_STRP_1, - TNETV107X_PIN_ASR_A13, - TNETV107X_PIN_GPIO43, - TNETV107X_PIN_ASR_A14, - TNETV107X_PIN_GPIO44, - TNETV107X_PIN_ASR_A15, - TNETV107X_PIN_GPIO45, - TNETV107X_PIN_ASR_A16, - TNETV107X_PIN_GPIO46, - TNETV107X_PIN_ASR_A17, - TNETV107X_PIN_GPIO47, - TNETV107X_PIN_ASR_A18, - TNETV107X_PIN_GPIO48, - TNETV107X_PIN_SDIO1_DATA3_0, - TNETV107X_PIN_ASR_A19, - TNETV107X_PIN_GPIO49, - TNETV107X_PIN_SDIO1_DATA2_0, - TNETV107X_PIN_ASR_A20, - TNETV107X_PIN_GPIO50, - TNETV107X_PIN_SDIO1_DATA1_0, - TNETV107X_PIN_ASR_A21, - TNETV107X_PIN_GPIO51, - TNETV107X_PIN_SDIO1_DATA0_0, - TNETV107X_PIN_ASR_A22, - TNETV107X_PIN_GPIO52, - TNETV107X_PIN_SDIO1_CMD_0, - TNETV107X_PIN_ASR_A23, - TNETV107X_PIN_GPIO53, - TNETV107X_PIN_SDIO1_CLK_0, - TNETV107X_PIN_ASR_BA_1, - TNETV107X_PIN_GPIO54, - TNETV107X_PIN_SYS_PLL_CLK, - TNETV107X_PIN_ASR_CS0, - TNETV107X_PIN_ASR_CS1, - TNETV107X_PIN_ASR_CS2, - TNETV107X_PIN_TDM_PLL_CLK, - TNETV107X_PIN_ASR_CS3, - TNETV107X_PIN_ETH_PHY_CLK, - TNETV107X_PIN_ASR_D00, - TNETV107X_PIN_GPIO55, - TNETV107X_PIN_ASR_D01, - TNETV107X_PIN_GPIO56, - TNETV107X_PIN_ASR_D02, - TNETV107X_PIN_GPIO57, - TNETV107X_PIN_ASR_D03, - TNETV107X_PIN_GPIO58, - TNETV107X_PIN_ASR_D04, - TNETV107X_PIN_GPIO59_0, - TNETV107X_PIN_ASR_D05, - TNETV107X_PIN_GPIO60_0, - TNETV107X_PIN_ASR_D06, - TNETV107X_PIN_GPIO61_0, - TNETV107X_PIN_ASR_D07, - TNETV107X_PIN_GPIO62_0, - TNETV107X_PIN_ASR_D08, - TNETV107X_PIN_GPIO63_0, - TNETV107X_PIN_ASR_D09, - TNETV107X_PIN_GPIO64_0, - TNETV107X_PIN_ASR_D10, - TNETV107X_PIN_SDIO1_DATA3_1, - TNETV107X_PIN_ASR_D11, - TNETV107X_PIN_SDIO1_DATA2_1, - TNETV107X_PIN_ASR_D12, - TNETV107X_PIN_SDIO1_DATA1_1, - TNETV107X_PIN_ASR_D13, - TNETV107X_PIN_SDIO1_DATA0_1, - TNETV107X_PIN_ASR_D14, - TNETV107X_PIN_SDIO1_CMD_1, - TNETV107X_PIN_ASR_D15, - TNETV107X_PIN_SDIO1_CLK_1, - TNETV107X_PIN_ASR_OE, - TNETV107X_PIN_BOOT_STRP_2, - TNETV107X_PIN_ASR_RNW, - TNETV107X_PIN_GPIO29_0, - TNETV107X_PIN_ASR_WAIT, - TNETV107X_PIN_GPIO30_0, - TNETV107X_PIN_ASR_WE, - TNETV107X_PIN_BOOT_STRP_3, - TNETV107X_PIN_ASR_WE_DQM0, - TNETV107X_PIN_GPIO31, - TNETV107X_PIN_LCD_PD17_0, - TNETV107X_PIN_ASR_WE_DQM1, - TNETV107X_PIN_ASR_BA0_0, - TNETV107X_PIN_VLYNQ_CLK, - TNETV107X_PIN_GPIO14, - TNETV107X_PIN_LCD_PD19_0, - TNETV107X_PIN_VLYNQ_RXD0, - TNETV107X_PIN_GPIO15, - TNETV107X_PIN_LCD_PD20_0, - TNETV107X_PIN_VLYNQ_RXD1, - TNETV107X_PIN_GPIO16, - TNETV107X_PIN_LCD_PD21_0, - TNETV107X_PIN_VLYNQ_TXD0, - TNETV107X_PIN_GPIO17, - TNETV107X_PIN_LCD_PD22_0, - TNETV107X_PIN_VLYNQ_TXD1, - TNETV107X_PIN_GPIO18, - TNETV107X_PIN_LCD_PD23_0, - TNETV107X_PIN_SDIO0_CLK, - TNETV107X_PIN_GPIO19, - TNETV107X_PIN_SDIO0_CMD, - TNETV107X_PIN_GPIO20, - TNETV107X_PIN_SDIO0_DATA0, - TNETV107X_PIN_GPIO21, - TNETV107X_PIN_SDIO0_DATA1, - TNETV107X_PIN_GPIO22, - TNETV107X_PIN_SDIO0_DATA2, - TNETV107X_PIN_GPIO23, - TNETV107X_PIN_SDIO0_DATA3, - TNETV107X_PIN_GPIO24, - TNETV107X_PIN_EMU0, - TNETV107X_PIN_EMU1, - TNETV107X_PIN_RTCK, - TNETV107X_PIN_TRST_N, - TNETV107X_PIN_TCK, - TNETV107X_PIN_TDI, - TNETV107X_PIN_TDO, - TNETV107X_PIN_TMS, - TNETV107X_PIN_TDM1_CLK, - TNETV107X_PIN_TDM1_RX, - TNETV107X_PIN_TDM1_TX, - TNETV107X_PIN_TDM1_FS, - TNETV107X_PIN_KEYPAD_R0, - TNETV107X_PIN_KEYPAD_R1, - TNETV107X_PIN_KEYPAD_R2, - TNETV107X_PIN_KEYPAD_R3, - TNETV107X_PIN_KEYPAD_R4, - TNETV107X_PIN_KEYPAD_R5, - TNETV107X_PIN_KEYPAD_R6, - TNETV107X_PIN_GPIO12, - TNETV107X_PIN_KEYPAD_R7, - TNETV107X_PIN_GPIO10, - TNETV107X_PIN_KEYPAD_C0, - TNETV107X_PIN_KEYPAD_C1, - TNETV107X_PIN_KEYPAD_C2, - TNETV107X_PIN_KEYPAD_C3, - TNETV107X_PIN_KEYPAD_C4, - TNETV107X_PIN_KEYPAD_C5, - TNETV107X_PIN_KEYPAD_C6, - TNETV107X_PIN_GPIO13, - TNETV107X_PIN_TEST_CLK_IN, - TNETV107X_PIN_KEYPAD_C7, - TNETV107X_PIN_GPIO11, - TNETV107X_PIN_SSP0_0, - TNETV107X_PIN_SCC_DCLK, - TNETV107X_PIN_LCD_PD20_1, - TNETV107X_PIN_SSP0_1, - TNETV107X_PIN_SCC_CS_N, - TNETV107X_PIN_LCD_PD21_1, - TNETV107X_PIN_SSP0_2, - TNETV107X_PIN_SCC_D, - TNETV107X_PIN_LCD_PD22_1, - TNETV107X_PIN_SSP0_3, - TNETV107X_PIN_SCC_RESETN, - TNETV107X_PIN_LCD_PD23_1, - TNETV107X_PIN_SSP1_0, - TNETV107X_PIN_GPIO25, - TNETV107X_PIN_UART2_CTS, - TNETV107X_PIN_SSP1_1, - TNETV107X_PIN_GPIO26, - TNETV107X_PIN_UART2_RD, - TNETV107X_PIN_SSP1_2, - TNETV107X_PIN_GPIO27, - TNETV107X_PIN_UART2_RTS, - TNETV107X_PIN_SSP1_3, - TNETV107X_PIN_GPIO28, - TNETV107X_PIN_UART2_TD, - TNETV107X_PIN_UART0_CTS, - TNETV107X_PIN_UART0_RD, - TNETV107X_PIN_UART0_RTS, - TNETV107X_PIN_UART0_TD, - TNETV107X_PIN_UART1_RD, - TNETV107X_PIN_UART1_TD, - TNETV107X_PIN_LCD_AC_NCS, - TNETV107X_PIN_LCD_HSYNC_RNW, - TNETV107X_PIN_LCD_VSYNC_A0, - TNETV107X_PIN_LCD_MCLK, - TNETV107X_PIN_LCD_PD16_0, - TNETV107X_PIN_LCD_PCLK_E, - TNETV107X_PIN_LCD_PD00, - TNETV107X_PIN_LCD_PD01, - TNETV107X_PIN_LCD_PD02, - TNETV107X_PIN_LCD_PD03, - TNETV107X_PIN_LCD_PD04, - TNETV107X_PIN_LCD_PD05, - TNETV107X_PIN_LCD_PD06, - TNETV107X_PIN_LCD_PD07, - TNETV107X_PIN_LCD_PD08, - TNETV107X_PIN_GPIO59_1, - TNETV107X_PIN_LCD_PD09, - TNETV107X_PIN_GPIO60_1, - TNETV107X_PIN_LCD_PD10, - TNETV107X_PIN_ASR_BA0_1, - TNETV107X_PIN_GPIO61_1, - TNETV107X_PIN_LCD_PD11, - TNETV107X_PIN_GPIO62_1, - TNETV107X_PIN_LCD_PD12, - TNETV107X_PIN_GPIO63_1, - TNETV107X_PIN_LCD_PD13, - TNETV107X_PIN_GPIO64_1, - TNETV107X_PIN_LCD_PD14, - TNETV107X_PIN_GPIO29_1, - TNETV107X_PIN_LCD_PD15, - TNETV107X_PIN_GPIO30_1, - TNETV107X_PIN_EINT0, - TNETV107X_PIN_GPIO08, - TNETV107X_PIN_EINT1, - TNETV107X_PIN_GPIO09, - TNETV107X_PIN_GPIO00, - TNETV107X_PIN_LCD_PD20_2, - TNETV107X_PIN_TDM_CLK_IN_2, - TNETV107X_PIN_GPIO01, - TNETV107X_PIN_LCD_PD21_2, - TNETV107X_PIN_24M_CLK_OUT_1, - TNETV107X_PIN_GPIO02, - TNETV107X_PIN_LCD_PD22_2, - TNETV107X_PIN_GPIO03, - TNETV107X_PIN_LCD_PD23_2, - TNETV107X_PIN_GPIO04, - TNETV107X_PIN_LCD_PD16_1, - TNETV107X_PIN_USB0_RXERR, - TNETV107X_PIN_GPIO05, - TNETV107X_PIN_LCD_PD17_1, - TNETV107X_PIN_TDM_CLK_IN_1, - TNETV107X_PIN_GPIO06, - TNETV107X_PIN_LCD_PD18, - TNETV107X_PIN_24M_CLK_OUT_2, - TNETV107X_PIN_GPIO07, - TNETV107X_PIN_LCD_PD19_1, - TNETV107X_PIN_USB1_RXERR, - TNETV107X_PIN_ETH_PLL_CLK, - TNETV107X_PIN_MDIO, - TNETV107X_PIN_MDC, - TNETV107X_PIN_AIC_MUTE_STAT_N, - TNETV107X_PIN_TDM0_CLK, - TNETV107X_PIN_AIC_HNS_EN_N, - TNETV107X_PIN_TDM0_FS, - TNETV107X_PIN_AIC_HDS_EN_STAT_N, - TNETV107X_PIN_TDM0_TX, - TNETV107X_PIN_AIC_HNF_EN_STAT_N, - TNETV107X_PIN_TDM0_RX, -}; - -#endif diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 4b7b67b643..4b9cb52965 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -65,7 +65,8 @@ /* * Section */ -#define PMD_SECT_S (3 << 8) +#define PMD_SECT_OUTER_SHARE (2 << 8) +#define PMD_SECT_INNER_SHARE (3 << 8) #define PMD_SECT_AF (1 << 10) #define PMD_SECT_NG (1 << 11) #define PMD_SECT_PXN (UL(1) << 53) diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 342f045f41..7a545ea01a 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -1149,6 +1149,7 @@ struct emif_regs { u32 sdram_config; u32 sdram_config2; u32 ref_ctrl; + u32 ref_ctrl_final; u32 sdram_tim1; u32 sdram_tim2; u32 sdram_tim3; diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 438f128326..bb24f33d0d 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -48,6 +48,9 @@ struct arch_global_data { #ifdef CONFIG_OMAP struct omap_boot_parameters omap_boot_params; #endif +#ifdef CONFIG_FSL_LSCH3 + unsigned long mem2_clk; +#endif }; #include <asm-generic/global_data.h> diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 8acd7cd1bd..17b6f544da 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -26,10 +26,14 @@ enum { BOOT_DEVICE_SPI, BOOT_DEVICE_SATA, BOOT_DEVICE_I2C, + BOOT_DEVICE_BOARD, BOOT_DEVICE_NONE }; #endif +/* Board-specific load method */ +void spl_board_load_image(void); + /* Linker symbols. */ extern char __bss_start[], __bss_end[]; diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 89f2294689..2a5bed2e46 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -70,6 +70,7 @@ void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end); void __asm_invalidate_tlb_all(void); void __asm_invalidate_icache_all(void); +int __asm_flush_l3_cache(void); void armv8_switch_to_el2(void); void armv8_switch_to_el1(void); @@ -142,6 +143,21 @@ void flush_l3_cache(void); #ifndef __ASSEMBLY__ +/** + * save_boot_params() - Save boot parameters before starting reset sequence + * + * If you provide this function it will be called immediately U-Boot starts, + * both for SPL and U-Boot proper. + * + * All registers are unchanged from U-Boot entry. No registers need be + * preserved. + * + * This is not a normal C function. There is no stack. Return by branching to + * save_boot_params_ret. + * + * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3); + */ + #define isb() __asm__ __volatile__ ("" : : : "memory") #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index d74e4b8415..da8ed72a11 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -35,6 +35,7 @@ endif obj-$(CONFIG_SEMIHOSTING) += semihosting.o obj-y += sections.o +obj-y += stack.o ifdef CONFIG_ARM64 obj-y += gic_64.o obj-y += interrupts_64.o diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c index b0c26e5d68..e5bcaea1ae 100644 --- a/arch/arm/lib/asm-offsets.c +++ b/arch/arm/lib/asm-offsets.c @@ -15,9 +15,6 @@ #include <common.h> #include <linux/kbuild.h> -#if defined(CONFIG_MB86R0x) -#include <asm/arch/mb86r0x.h> -#endif #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \ || defined(CONFIG_MX51) || defined(CONFIG_MX53) #include <asm/arch/imx-regs.h> @@ -27,8 +24,6 @@ int main(void) { /* * TODO : Check if each entry in this file is really necessary. - * - struct mb86r0x_ddr2 - * - struct mb86r0x_memc * - struct esdramc_regs * - struct max_regs * - struct aips_regs @@ -40,47 +35,6 @@ int main(void) * code. Is it better to define the macros directly in headers? */ -#if defined(CONFIG_MB86R0x) - /* ddr2 controller */ - DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric)); - DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1)); - DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2)); - DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca)); - DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm)); - DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1)); - DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2)); - DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr)); - DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf)); - DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr)); - DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims)); - DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros)); - DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1)); - DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba)); - DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs)); - - /* clock reset generator */ - DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr)); - DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha)); - DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa)); - DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb)); - DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb)); - DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram)); - - /* chip control module */ - DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc)); - - /* external bus interface */ - DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0])); - DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2])); - DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4])); - DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0])); - DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2])); - DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4])); - DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0])); - DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2])); - DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4])); -#endif - #if defined(CONFIG_MX25) /* Clock Control Module */ DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 0c1298a31e..2d6b676154 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -191,7 +191,7 @@ __weak void setup_board_tags(struct tag **in_params) {} static void do_nonsec_virt_switch(void) { smp_kick_all_cpus(); - flush_dcache_all(); /* flush cache before swtiching to EL2 */ + dcache_disable(); /* flush cache before swtiching to EL2 */ armv8_switch_to_el2(); #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 armv8_switch_to_el1(); diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c new file mode 100644 index 0000000000..cf10a53ec6 --- /dev/null +++ b/arch/arm/lib/stack.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com> + * + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2002-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int arch_reserve_stacks(void) +{ +#ifdef CONFIG_SPL_BUILD + gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */ + gd->irq_sp = gd->start_addr_sp; +#else + /* setup stack pointer for exceptions */ + gd->irq_sp = gd->start_addr_sp; + +# if !defined(CONFIG_ARM64) +# ifdef CONFIG_USE_IRQ + gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ); + debug("Reserving %zu Bytes for IRQ stack at: %08lx\n", + CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp); + + /* 8-byte alignment for ARM ABI compliance */ + gd->start_addr_sp &= ~0x07; +# endif + /* leave 3 words for abort-stack, plus 1 for alignment */ + gd->start_addr_sp -= 16; +# endif +#endif + + return 0; +} diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig new file mode 100644 index 0000000000..30945c101b --- /dev/null +++ b/arch/arm/mach-at91/Kconfig @@ -0,0 +1,168 @@ +if ARCH_AT91 + +choice + prompt "Atmel AT91 board select" + +config TARGET_AT91RM9200EK + bool "Atmel AT91RM9200 evaluation kit" + select CPU_ARM920T + +config TARGET_EB_CPUX9K2 + bool "Support eb_cpux9k2" + select CPU_ARM920T + +config TARGET_CPUAT91 + bool "Support cpuat91" + select CPU_ARM920T + +config TARGET_AT91SAM9260EK + bool "Atmel at91sam9260 reference board" + select CPU_ARM926EJS + +config TARGET_ETHERNUT5 + bool "Ethernut5 board" + select CPU_ARM926EJS + +config TARGET_TNY_A9260 + bool "Caloa TNY A9260 board" + select CPU_ARM926EJS + +config TARGET_SNAPPER9260 + bool "Support snapper9260" + select CPU_ARM926EJS + +config TARGET_AFEB9260 + bool "Support afeb9260" + select CPU_ARM926EJS + +config TARGET_AT91SAM9261EK + bool "Atmel at91sam9261 reference board" + select CPU_ARM926EJS + +config TARGET_PM9261 + bool "Ronetix pm9261 board" + select CPU_ARM926EJS + +config TARGET_AT91SAM9263EK + bool "Atmel at91sam9263 reference board" + select CPU_ARM926EJS + +config TARGET_USB_A9263 + bool "Caloa USB A9260 board" + select CPU_ARM926EJS + +config TARGET_PM9263 + bool "Ronetix pm9263 board" + select CPU_ARM926EJS + +config TARGET_SBC35_A9G20 + bool "Support sbc35_a9g20" + select CPU_ARM926EJS + +config TARGET_STAMP9G20 + bool "Support stamp9g20" + select CPU_ARM926EJS + +config TARGET_AT91SAM9M10G45EK + bool "Atmel AT91SAM9M10G45-EK board" + select CPU_ARM926EJS + +config TARGET_PM9G45 + bool "Ronetix pm9g45 board" + select CPU_ARM926EJS + +config TARGET_AT91SAM9N12EK + bool "Atmel AT91SAM9N12-EK board" + select CPU_ARM926EJS + +config TARGET_AT91SAM9RLEK + bool "Atmel at91sam9rl reference board" + select CPU_ARM926EJS + +config TARGET_AT91SAM9X5EK + bool "Atmel AT91SAM9X5-EK board" + select CPU_ARM926EJS + +config TARGET_SAMA5D3_XPLAINED + bool "SAMA5D3 Xplained board" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_SAMA5D3XEK + bool "SAMA5D3X-EK board" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_SAMA5D4_XPLAINED + bool "SAMA5D4 Xplained board" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_SAMA5D4EK + bool "SAMA5D4 Evaluation Kit" + select CPU_V7 + select SUPPORT_SPL + +config TARGET_VL_MA2SC + bool "Support vl_ma2sc" + select CPU_ARM926EJS + +config TARGET_MEESC + bool "Support meesc" + select CPU_ARM926EJS + +config TARGET_OTC570 + bool "Support otc570" + select CPU_ARM926EJS + +config TARGET_CPU9260 + bool "Support cpu9260" + select CPU_ARM926EJS + +config TARGET_CORVUS + bool "Support corvus" + select CPU_ARM926EJS + select SUPPORT_SPL + +config TARGET_TAURUS + bool "Support taurus" + select CPU_ARM926EJS + select SUPPORT_SPL + +endchoice + +config SYS_SOC + default "at91" + +source "board/atmel/at91rm9200ek/Kconfig" +source "board/atmel/at91sam9260ek/Kconfig" +source "board/atmel/at91sam9261ek/Kconfig" +source "board/atmel/at91sam9263ek/Kconfig" +source "board/atmel/at91sam9m10g45ek/Kconfig" +source "board/atmel/at91sam9n12ek/Kconfig" +source "board/atmel/at91sam9rlek/Kconfig" +source "board/atmel/at91sam9x5ek/Kconfig" +source "board/atmel/sama5d3_xplained/Kconfig" +source "board/atmel/sama5d3xek/Kconfig" +source "board/atmel/sama5d4_xplained/Kconfig" +source "board/atmel/sama5d4ek/Kconfig" +source "board/BuS/eb_cpux9k2/Kconfig" +source "board/eukrea/cpuat91/Kconfig" +source "board/afeb9260/Kconfig" +source "board/bluewater/snapper9260/Kconfig" +source "board/BuS/vl_ma2sc/Kconfig" +source "board/calao/sbc35_a9g20/Kconfig" +source "board/calao/tny_a9260/Kconfig" +source "board/calao/usb_a9263/Kconfig" +source "board/egnite/ethernut5/Kconfig" +source "board/esd/meesc/Kconfig" +source "board/esd/otc570/Kconfig" +source "board/eukrea/cpu9260/Kconfig" +source "board/ronetix/pm9261/Kconfig" +source "board/ronetix/pm9263/Kconfig" +source "board/ronetix/pm9g45/Kconfig" +source "board/siemens/corvus/Kconfig" +source "board/siemens/taurus/Kconfig" +source "board/taskit/stamp9g20/Kconfig" + +endif diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/mach-at91/Makefile index 03614d4140..e596ba6ce8 100644 --- a/arch/arm/cpu/at91-common/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,13 +1,3 @@ -# -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2013 Atmel Corporation -# Bo Shen <voice.shen@atmel.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o ifneq ($(CONFIG_SPL_BUILD),) obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o @@ -16,3 +6,7 @@ obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o obj-y += spl.o endif + +obj-$(CONFIG_CPU_ARM920T) += arm920t/ +obj-$(CONFIG_CPU_ARM926EJS) += arm926ejs/ +obj-$(CONFIG_CPU_V7) += armv7/ diff --git a/arch/arm/cpu/arm920t/at91/Makefile b/arch/arm/mach-at91/arm920t/Makefile index 561b4b4cbb..561b4b4cbb 100644 --- a/arch/arm/cpu/arm920t/at91/Makefile +++ b/arch/arm/mach-at91/arm920t/Makefile diff --git a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c index fc54327c0d..fc54327c0d 100644 --- a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c diff --git a/arch/arm/cpu/arm920t/at91/clock.c b/arch/arm/mach-at91/arm920t/clock.c index 2813bf7821..2813bf7821 100644 --- a/arch/arm/cpu/arm920t/at91/clock.c +++ b/arch/arm/mach-at91/arm920t/clock.c diff --git a/arch/arm/cpu/arm920t/at91/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c index b0f411b1c3..b0f411b1c3 100644 --- a/arch/arm/cpu/arm920t/at91/cpu.c +++ b/arch/arm/mach-at91/arm920t/cpu.c diff --git a/arch/arm/cpu/arm920t/at91/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S index d2934a3525..d2934a3525 100644 --- a/arch/arm/cpu/arm920t/at91/lowlevel_init.S +++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S diff --git a/arch/arm/cpu/arm920t/at91/reset.c b/arch/arm/mach-at91/arm920t/reset.c index d47777a367..d47777a367 100644 --- a/arch/arm/cpu/arm920t/at91/reset.c +++ b/arch/arm/mach-at91/arm920t/reset.c diff --git a/arch/arm/cpu/arm920t/at91/timer.c b/arch/arm/mach-at91/arm920t/timer.c index 6aa2994723..6aa2994723 100644 --- a/arch/arm/cpu/arm920t/at91/timer.c +++ b/arch/arm/mach-at91/arm920t/timer.c diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index ddc323f641..ddc323f641 100644 --- a/arch/arm/cpu/arm926ejs/at91/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c index efb53d673f..efb53d673f 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c index a445c7507e..a445c7507e 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c index 6b51d5f355..6b51d5f355 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c index 0e6c0da1bd..0e6c0da1bd 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c index 39f17a1e11..39f17a1e11 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c index 0ec32c3ab9..0ec32c3ab9 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c index 6d94572237..6d94572237 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c +++ b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index f363982d03..f363982d03 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c index da1d35907e..da1d35907e 100644 --- a/arch/arm/cpu/arm926ejs/at91/cpu.c +++ b/arch/arm/mach-at91/arm926ejs/cpu.c diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/mach-at91/arm926ejs/eflash.c index 3f39264289..3f39264289 100644 --- a/arch/arm/cpu/arm926ejs/at91/eflash.c +++ b/arch/arm/mach-at91/arm926ejs/eflash.c diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/mach-at91/arm926ejs/led.c index b8d5c785df..b8d5c785df 100644 --- a/arch/arm/cpu/arm926ejs/at91/led.c +++ b/arch/arm/mach-at91/arm926ejs/led.c diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S index a9ec81a75c..a9ec81a75c 100644 --- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S +++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/mach-at91/arm926ejs/reset.c index e67f47bd04..e67f47bd04 100644 --- a/arch/arm/cpu/arm926ejs/at91/reset.c +++ b/arch/arm/mach-at91/arm926ejs/reset.c diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/mach-at91/arm926ejs/timer.c index b0b7fb93fb..b0b7fb93fb 100644 --- a/arch/arm/cpu/arm926ejs/at91/timer.c +++ b/arch/arm/mach-at91/arm926ejs/timer.c diff --git a/arch/arm/cpu/armv7/at91/Makefile b/arch/arm/mach-at91/armv7/Makefile index f4f35a4bc1..f4f35a4bc1 100644 --- a/arch/arm/cpu/armv7/at91/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/mach-at91/armv7/clock.c index 0bf453eff5..0bf453eff5 100644 --- a/arch/arm/cpu/armv7/at91/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index 8d86f97e3d..8d86f97e3d 100644 --- a/arch/arm/cpu/armv7/at91/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c diff --git a/arch/arm/cpu/armv7/at91/reset.c b/arch/arm/mach-at91/armv7/reset.c index b30e79b60a..b30e79b60a 100644 --- a/arch/arm/cpu/armv7/at91/reset.c +++ b/arch/arm/mach-at91/armv7/reset.c diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/mach-at91/armv7/sama5d3_devices.c index 78ecfc882a..78ecfc882a 100644 --- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d3_devices.c diff --git a/arch/arm/cpu/armv7/at91/sama5d4_devices.c b/arch/arm/mach-at91/armv7/sama5d4_devices.c index ef39cb7e08..ef39cb7e08 100644 --- a/arch/arm/cpu/armv7/at91/sama5d4_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/mach-at91/armv7/timer.c index 19bf80ba7e..19bf80ba7e 100644 --- a/arch/arm/cpu/armv7/at91/timer.c +++ b/arch/arm/mach-at91/armv7/timer.c diff --git a/arch/arm/mach-at91/config.mk b/arch/arm/mach-at91/config.mk new file mode 100644 index 0000000000..7168abbd58 --- /dev/null +++ b/arch/arm/mach-at91/config.mk @@ -0,0 +1,9 @@ +ifeq ($(CONFIG_CPU_ARM926EJS),y) +PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,) +endif + +ifeq ($(CONFIG_CPU_V7),y) +ifndef CONFIG_SPL_BUILD +ALL-y += u-boot.img +endif +endif diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h index efcd74ed90..efcd74ed90 100644 --- a/arch/arm/include/asm/arch-at91/at91_common.h +++ b/arch/arm/mach-at91/include/mach/at91_common.h diff --git a/arch/arm/include/asm/arch-at91/at91_dbu.h b/arch/arm/mach-at91/include/mach/at91_dbu.h index 7346fc0569..7346fc0569 100644 --- a/arch/arm/include/asm/arch-at91/at91_dbu.h +++ b/arch/arm/mach-at91/include/mach/at91_dbu.h diff --git a/arch/arm/include/asm/arch-at91/at91_eefc.h b/arch/arm/mach-at91/include/mach/at91_eefc.h index 7ffbaee27d..7ffbaee27d 100644 --- a/arch/arm/include/asm/arch-at91/at91_eefc.h +++ b/arch/arm/mach-at91/include/mach/at91_eefc.h diff --git a/arch/arm/include/asm/arch-at91/at91_emac.h b/arch/arm/mach-at91/include/mach/at91_emac.h index a0d74ab660..a0d74ab660 100644 --- a/arch/arm/include/asm/arch-at91/at91_emac.h +++ b/arch/arm/mach-at91/include/mach/at91_emac.h diff --git a/arch/arm/include/asm/arch-at91/at91_gpbr.h b/arch/arm/mach-at91/include/mach/at91_gpbr.h index e781481e88..e781481e88 100644 --- a/arch/arm/include/asm/arch-at91/at91_gpbr.h +++ b/arch/arm/mach-at91/include/mach/at91_gpbr.h diff --git a/arch/arm/include/asm/arch-at91/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h index 2379dd40f8..2379dd40f8 100644 --- a/arch/arm/include/asm/arch-at91/at91_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91_matrix.h diff --git a/arch/arm/include/asm/arch-at91/at91_mc.h b/arch/arm/mach-at91/include/mach/at91_mc.h index 2ace77931d..2ace77931d 100644 --- a/arch/arm/include/asm/arch-at91/at91_mc.h +++ b/arch/arm/mach-at91/include/mach/at91_mc.h diff --git a/arch/arm/include/asm/arch-at91/at91_pdc.h b/arch/arm/mach-at91/include/mach/at91_pdc.h index 832ebb51c1..832ebb51c1 100644 --- a/arch/arm/include/asm/arch-at91/at91_pdc.h +++ b/arch/arm/mach-at91/include/mach/at91_pdc.h diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h index 50464ffe8e..301227880a 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/mach-at91/include/mach/at91_pio.h @@ -114,14 +114,10 @@ typedef union at91_pio { at91_port_t pioa; at91_port_t piob; at91_port_t pioc; - #if (ATMEL_PIO_PORTS > 3) - at91_port_t piod; - #endif - #if (ATMEL_PIO_PORTS > 4) - at91_port_t pioe; - #endif - } ; - at91_port_t port[ATMEL_PIO_PORTS]; + at91_port_t piod; /* not present in all hardware */ + at91_port_t pioe;/* not present in all hardware */ + }; + at91_port_t port[5]; } at91_pio_t; #ifdef CONFIG_AT91_GPIO diff --git a/arch/arm/include/asm/arch-at91/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h index 56724f15e7..56724f15e7 100644 --- a/arch/arm/include/asm/arch-at91/at91_pit.h +++ b/arch/arm/mach-at91/include/mach/at91_pit.h diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 65691aba01..65691aba01 100644 --- a/arch/arm/include/asm/arch-at91/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h index e4eb3da03f..e4eb3da03f 100644 --- a/arch/arm/include/asm/arch-at91/at91_rstc.h +++ b/arch/arm/mach-at91/include/mach/at91_rstc.h diff --git a/arch/arm/include/asm/arch-at91/at91_rtt.h b/arch/arm/mach-at91/include/mach/at91_rtt.h index fe7619a932..fe7619a932 100644 --- a/arch/arm/include/asm/arch-at91/at91_rtt.h +++ b/arch/arm/mach-at91/include/mach/at91_rtt.h diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/mach-at91/include/mach/at91_spi.h index b18665b62c..b18665b62c 100644 --- a/arch/arm/include/asm/arch-at91/at91_spi.h +++ b/arch/arm/mach-at91/include/mach/at91_spi.h diff --git a/arch/arm/include/asm/arch-at91/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h index b1ee1472e5..b1ee1472e5 100644 --- a/arch/arm/include/asm/arch-at91/at91_st.h +++ b/arch/arm/mach-at91/include/mach/at91_st.h diff --git a/arch/arm/include/asm/arch-at91/at91_tc.h b/arch/arm/mach-at91/include/mach/at91_tc.h index de0e266565..de0e266565 100644 --- a/arch/arm/include/asm/arch-at91/at91_tc.h +++ b/arch/arm/mach-at91/include/mach/at91_tc.h diff --git a/arch/arm/include/asm/arch-at91/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h index 0644bbf3c6..0644bbf3c6 100644 --- a/arch/arm/include/asm/arch-at91/at91_wdt.h +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h diff --git a/arch/arm/include/asm/arch-at91/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h index d177bdcae5..d177bdcae5 100644 --- a/arch/arm/include/asm/arch-at91/at91rm9200.h +++ b/arch/arm/mach-at91/include/mach/at91rm9200.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 8950d67409..8950d67409 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h index dc61f48f52..dc61f48f52 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9260_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index 6dfcf4c0c8..6dfcf4c0c8 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h index fc5f0831b8..fc5f0831b8 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index 64a3888e22..64a3888e22 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h index 54d862287b..54d862287b 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9_matrix.h index d0bf0c2e2b..d0bf0c2e2b 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_matrix.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h index 3a076c6b80..3a076c6b80 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h index d29e98e711..d29e98e711 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9_smc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index 6df8cdb56d..6df8cdb56d 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h index 80e49e3430..80e49e3430 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index 3a8e6d62ce..3a8e6d62ce 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h index 295f768b55..295f768b55 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index 36a5cdf476..36a5cdf476 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h index bd0b25adc9..bd0b25adc9 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h diff --git a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h index 130a85abee..130a85abee 100644 --- a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h +++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h diff --git a/arch/arm/include/asm/arch-at91/atmel_serial.h b/arch/arm/mach-at91/include/mach/atmel_serial.h index 5bc094b355..5bc094b355 100644 --- a/arch/arm/include/asm/arch-at91/atmel_serial.h +++ b/arch/arm/mach-at91/include/mach/atmel_serial.h diff --git a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h index 38b5012fce..38b5012fce 100644 --- a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h +++ b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/mach-at91/include/mach/clk.h index 1d45e2dc11..1d45e2dc11 100644 --- a/arch/arm/include/asm/arch-at91/clk.h +++ b/arch/arm/mach-at91/include/mach/clk.h diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index 6d2a7b72ff..6d2a7b72ff 100644 --- a/arch/arm/include/asm/arch-at91/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index ff6b71b135..ff6b71b135 100644 --- a/arch/arm/include/asm/arch-at91/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h diff --git a/arch/arm/include/asm/arch-at91/sama5_matrix.h b/arch/arm/mach-at91/include/mach/sama5_matrix.h index e324766733..e324766733 100644 --- a/arch/arm/include/asm/arch-at91/sama5_matrix.h +++ b/arch/arm/mach-at91/include/mach/sama5_matrix.h diff --git a/arch/arm/include/asm/arch-at91/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h index 3081d37571..3081d37571 100644 --- a/arch/arm/include/asm/arch-at91/sama5_sfr.h +++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 227ba80825..227ba80825 100644 --- a/arch/arm/include/asm/arch-at91/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h diff --git a/arch/arm/include/asm/arch-at91/sama5d3_smc.h b/arch/arm/mach-at91/include/mach/sama5d3_smc.h index a859b6db9b..a859b6db9b 100644 --- a/arch/arm/include/asm/arch-at91/sama5d3_smc.h +++ b/arch/arm/mach-at91/include/mach/sama5d3_smc.h diff --git a/arch/arm/include/asm/arch-at91/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h index f30cb5fed1..f30cb5fed1 100644 --- a/arch/arm/include/asm/arch-at91/sama5d4.h +++ b/arch/arm/mach-at91/include/mach/sama5d4.h diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index beec13db8c..beec13db8c 100644 --- a/arch/arm/cpu/at91-common/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/mach-at91/phy.c index 2cba7169e4..2cba7169e4 100644 --- a/arch/arm/cpu/at91-common/phy.c +++ b/arch/arm/mach-at91/phy.c diff --git a/arch/arm/cpu/at91-common/sdram.c b/arch/arm/mach-at91/sdram.c index 5758b066e4..5758b066e4 100644 --- a/arch/arm/cpu/at91-common/sdram.c +++ b/arch/arm/mach-at91/sdram.c diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/mach-at91/spl.c index aaa5eec2e6..aaa5eec2e6 100644 --- a/arch/arm/cpu/at91-common/spl.c +++ b/arch/arm/mach-at91/spl.c diff --git a/arch/arm/cpu/at91-common/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index 89f588be45..89f588be45 100644 --- a/arch/arm/cpu/at91-common/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c diff --git a/arch/arm/cpu/at91-common/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 9cc1111234..9cc1111234 100644 --- a/arch/arm/cpu/at91-common/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c diff --git a/arch/arm/cpu/at91-common/u-boot-spl.lds b/arch/arm/mach-at91/u-boot-spl.lds index eccca43a42..eccca43a42 100644 --- a/arch/arm/cpu/at91-common/u-boot-spl.lds +++ b/arch/arm/mach-at91/u-boot-spl.lds diff --git a/arch/arm/cpu/arm926ejs/davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 613f04d8b0..68277217bf 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -21,10 +21,6 @@ config TARGET_CAM_ENC_4XX bool "CAM ENC 4xx board" select SUPPORT_SPL -config TARGET_HAWKBOARD - bool "Hawkboard" - select SUPPORT_SPL - config TARGET_DAVINCI_DM355EVM bool "DM355 EVM board" diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/mach-davinci/Makefile index 7d67191de8..7d67191de8 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile diff --git a/arch/arm/cpu/arm926ejs/davinci/config.mk b/arch/arm/mach-davinci/config.mk index 69e9d5ab21..69e9d5ab21 100644 --- a/arch/arm/cpu/arm926ejs/davinci/config.mk +++ b/arch/arm/mach-davinci/config.mk diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/mach-davinci/cpu.c index ff61147757..ff61147757 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/mach-davinci/cpu.c diff --git a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c b/arch/arm/mach-davinci/da830_pinmux.c index edaab45327..edaab45327 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c +++ b/arch/arm/mach-davinci/da830_pinmux.c diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 19730cef8c..19730cef8c 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/mach-davinci/da850_pinmux.c index 6105f6390c..6105f6390c 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c +++ b/arch/arm/mach-davinci/da850_pinmux.c diff --git a/arch/arm/cpu/arm926ejs/davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index f9550a16d3..f9550a16d3 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index f6ca527e74..f6ca527e74 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/mach-davinci/dm365_lowlevel.c index c8b44988d3..c8b44988d3 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c +++ b/arch/arm/mach-davinci/dm365_lowlevel.c diff --git a/arch/arm/cpu/arm926ejs/davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index c58e271e28..c58e271e28 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c diff --git a/arch/arm/cpu/arm926ejs/davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index cfea8300de..cfea8300de 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c diff --git a/arch/arm/cpu/arm926ejs/davinci/dp83848.c b/arch/arm/mach-davinci/dp83848.c index 603d507c70..6387e956b2 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dp83848.c +++ b/arch/arm/mach-davinci/dp83848.c @@ -13,7 +13,7 @@ #include <net.h> #include <dp83848.h> #include <asm/arch/emac_defs.h> -#include "../../../../../drivers/net/davinci_emac.h" +#include "../../../drivers/net/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/cpu/arm926ejs/davinci/et1011c.c b/arch/arm/mach-davinci/et1011c.c index 9d53875b93..151020d45a 100644 --- a/arch/arm/cpu/arm926ejs/davinci/et1011c.c +++ b/arch/arm/mach-davinci/et1011c.c @@ -10,7 +10,7 @@ #include <net.h> #include <miiphy.h> #include <asm/arch/emac_defs.h> -#include "../../../../../drivers/net/davinci_emac.h" +#include "../../../drivers/net/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/include/asm/arch-davinci/aintc_defs.h b/arch/arm/mach-davinci/include/mach/aintc_defs.h index 5063e3964c..5063e3964c 100644 --- a/arch/arm/include/asm/arch-davinci/aintc_defs.h +++ b/arch/arm/mach-davinci/include/mach/aintc_defs.h diff --git a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h b/arch/arm/mach-davinci/include/mach/da850_lowlevel.h index 45a325c123..45a325c123 100644 --- a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h +++ b/arch/arm/mach-davinci/include/mach/da850_lowlevel.h diff --git a/arch/arm/include/asm/arch-davinci/da8xx-usb.h b/arch/arm/mach-davinci/include/mach/da8xx-usb.h index f091e49899..f091e49899 100644 --- a/arch/arm/include/asm/arch-davinci/da8xx-usb.h +++ b/arch/arm/mach-davinci/include/mach/da8xx-usb.h diff --git a/arch/arm/include/asm/arch-davinci/davinci_misc.h b/arch/arm/mach-davinci/include/mach/davinci_misc.h index 03be3882f8..03be3882f8 100644 --- a/arch/arm/include/asm/arch-davinci/davinci_misc.h +++ b/arch/arm/mach-davinci/include/mach/davinci_misc.h diff --git a/arch/arm/include/asm/arch-davinci/ddr2_defs.h b/arch/arm/mach-davinci/include/mach/ddr2_defs.h index 24afd9d526..24afd9d526 100644 --- a/arch/arm/include/asm/arch-davinci/ddr2_defs.h +++ b/arch/arm/mach-davinci/include/mach/ddr2_defs.h diff --git a/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h b/arch/arm/mach-davinci/include/mach/dm365_lowlevel.h index 6c0275efa7..6c0275efa7 100644 --- a/arch/arm/include/asm/arch-davinci/dm365_lowlevel.h +++ b/arch/arm/mach-davinci/include/mach/dm365_lowlevel.h diff --git a/arch/arm/include/asm/arch-davinci/emac_defs.h b/arch/arm/mach-davinci/include/mach/emac_defs.h index c3f046efa8..c3f046efa8 100644 --- a/arch/arm/include/asm/arch-davinci/emac_defs.h +++ b/arch/arm/mach-davinci/include/mach/emac_defs.h diff --git a/arch/arm/include/asm/arch-davinci/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index 7da0060cd4..7da0060cd4 100644 --- a/arch/arm/include/asm/arch-davinci/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h index a4eb0bd89b..a4eb0bd89b 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/mach-davinci/include/mach/hardware.h diff --git a/arch/arm/include/asm/arch-davinci/i2c_defs.h b/arch/arm/mach-davinci/include/mach/i2c_defs.h index 06da8947b4..06da8947b4 100644 --- a/arch/arm/include/asm/arch-davinci/i2c_defs.h +++ b/arch/arm/mach-davinci/include/mach/i2c_defs.h diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/mach-davinci/include/mach/pinmux_defs.h index 2d82af554b..2d82af554b 100644 --- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h +++ b/arch/arm/mach-davinci/include/mach/pinmux_defs.h diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/mach-davinci/include/mach/pll_defs.h index d083cccadb..d083cccadb 100644 --- a/arch/arm/include/asm/arch-davinci/pll_defs.h +++ b/arch/arm/mach-davinci/include/mach/pll_defs.h diff --git a/arch/arm/include/asm/arch-davinci/psc_defs.h b/arch/arm/mach-davinci/include/mach/psc_defs.h index bcb5580499..bcb5580499 100644 --- a/arch/arm/include/asm/arch-davinci/psc_defs.h +++ b/arch/arm/mach-davinci/include/mach/psc_defs.h diff --git a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h b/arch/arm/mach-davinci/include/mach/sdmmc_defs.h index 9aa3f4ab27..9aa3f4ab27 100644 --- a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h +++ b/arch/arm/mach-davinci/include/mach/sdmmc_defs.h diff --git a/arch/arm/include/asm/arch-davinci/syscfg_defs.h b/arch/arm/mach-davinci/include/mach/syscfg_defs.h index 812088f379..812088f379 100644 --- a/arch/arm/include/asm/arch-davinci/syscfg_defs.h +++ b/arch/arm/mach-davinci/include/mach/syscfg_defs.h diff --git a/arch/arm/include/asm/arch-davinci/timer_defs.h b/arch/arm/mach-davinci/include/mach/timer_defs.h index 94d18320d9..94d18320d9 100644 --- a/arch/arm/include/asm/arch-davinci/timer_defs.h +++ b/arch/arm/mach-davinci/include/mach/timer_defs.h diff --git a/arch/arm/cpu/arm926ejs/davinci/ksz8873.c b/arch/arm/mach-davinci/ksz8873.c index 4af5dd2135..75af13538d 100644 --- a/arch/arm/cpu/arm926ejs/davinci/ksz8873.c +++ b/arch/arm/mach-davinci/ksz8873.c @@ -20,7 +20,7 @@ #include <net.h> #include <asm/arch/emac_defs.h> #include <asm/io.h> -#include "../../../../../drivers/net/davinci_emac.h" +#include "../../../drivers/net/davinci_emac.h" int ksz8873_is_phy_connected(int phy_addr) { diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/mach-davinci/lowlevel_init.S index e91623497c..e91623497c 100644 --- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S +++ b/arch/arm/mach-davinci/lowlevel_init.S diff --git a/arch/arm/cpu/arm926ejs/davinci/lxt972.c b/arch/arm/mach-davinci/lxt972.c index c482fd9378..a7356f9672 100644 --- a/arch/arm/cpu/arm926ejs/davinci/lxt972.c +++ b/arch/arm/mach-davinci/lxt972.c @@ -14,7 +14,7 @@ #include <miiphy.h> #include <lxt971a.h> #include <asm/arch/emac_defs.h> -#include "../../../../../drivers/net/davinci_emac.h" +#include "../../../drivers/net/davinci_emac.h" #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/arch/arm/cpu/arm926ejs/davinci/misc.c b/arch/arm/mach-davinci/misc.c index e18bdfc729..e18bdfc729 100644 --- a/arch/arm/cpu/arm926ejs/davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c diff --git a/arch/arm/cpu/arm926ejs/davinci/pinmux.c b/arch/arm/mach-davinci/pinmux.c index e9d8c87cc8..e9d8c87cc8 100644 --- a/arch/arm/cpu/arm926ejs/davinci/pinmux.c +++ b/arch/arm/mach-davinci/pinmux.c diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/mach-davinci/psc.c index 8d99e2e997..8d99e2e997 100644 --- a/arch/arm/cpu/arm926ejs/davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.c b/arch/arm/mach-davinci/reset.c index 6b0f15428a..6b0f15428a 100644 --- a/arch/arm/cpu/arm926ejs/davinci/reset.c +++ b/arch/arm/mach-davinci/reset.c diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/mach-davinci/spl.c index 49349da179..49349da179 100644 --- a/arch/arm/cpu/arm926ejs/davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/mach-davinci/timer.c index c7d0652e83..c7d0652e83 100644 --- a/arch/arm/cpu/arm926ejs/davinci/timer.c +++ b/arch/arm/mach-davinci/timer.c diff --git a/arch/arm/cpu/armv7/highbank/Kconfig b/arch/arm/mach-highbank/Kconfig index 0e73c04142..0e73c04142 100644 --- a/arch/arm/cpu/armv7/highbank/Kconfig +++ b/arch/arm/mach-highbank/Kconfig diff --git a/arch/arm/cpu/armv7/highbank/Makefile b/arch/arm/mach-highbank/Makefile index 876099d9a1..876099d9a1 100644 --- a/arch/arm/cpu/armv7/highbank/Makefile +++ b/arch/arm/mach-highbank/Makefile diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/mach-highbank/timer.c index d56bf21133..d56bf21133 100644 --- a/arch/arm/cpu/armv7/highbank/timer.c +++ b/arch/arm/mach-highbank/timer.c diff --git a/arch/arm/cpu/armv7/keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index 134ae87fe1..134ae87fe1 100644 --- a/arch/arm/cpu/armv7/keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/mach-keystone/Makefile index ed030db2c8..ed030db2c8 100644 --- a/arch/arm/cpu/armv7/keystone/Makefile +++ b/arch/arm/mach-keystone/Makefile diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c index 31f66613ef..31f66613ef 100644 --- a/arch/arm/cpu/armv7/keystone/clock-k2e.c +++ b/arch/arm/mach-keystone/clock-k2e.c diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/mach-keystone/clock-k2hk.c index 1591960795..1591960795 100644 --- a/arch/arm/cpu/armv7/keystone/clock-k2hk.c +++ b/arch/arm/mach-keystone/clock-k2hk.c diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c index 1c5e4d54d8..1c5e4d54d8 100644 --- a/arch/arm/cpu/armv7/keystone/clock-k2l.c +++ b/arch/arm/mach-keystone/clock-k2l.c diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/mach-keystone/clock.c index d13fbc1a4b..d13fbc1a4b 100644 --- a/arch/arm/cpu/armv7/keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/mach-keystone/cmd_clock.c index af1b701e82..af1b701e82 100644 --- a/arch/arm/cpu/armv7/keystone/cmd_clock.c +++ b/arch/arm/mach-keystone/cmd_clock.c diff --git a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c b/arch/arm/mach-keystone/cmd_ddr3.c index ea78ad8fd5..ea78ad8fd5 100644 --- a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c +++ b/arch/arm/mach-keystone/cmd_ddr3.c diff --git a/arch/arm/cpu/armv7/keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c index f9f58a37df..f9f58a37df 100644 --- a/arch/arm/cpu/armv7/keystone/cmd_mon.c +++ b/arch/arm/mach-keystone/cmd_mon.c diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 923906afb5..dfb27b5ba2 100644 --- a/arch/arm/cpu/armv7/keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -263,17 +263,14 @@ static void ddr3_map_ecc_cic2_irq(u32 base) } #endif -void ddr3_init_ecc(u32 base) +void ddr3_init_ecc(u32 base, u32 ddr3_size) { - u32 ddr3_size; - if (!ddr3_ecc_support_rmw(base)) { ddr3_disable_ecc(base); return; } ddr3_ecc_init_range(base); - ddr3_size = ddr3_get_size(); ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size); /* mapping DDR3 ECC system interrupt from CIC2 to GIC */ diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h index d013b830ed..d013b830ed 100644 --- a/arch/arm/include/asm/arch-keystone/clock-k2e.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h index f28d5f0c4e..f28d5f0c4e 100644 --- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h index bb9a5c4dcf..bb9a5c4dcf 100644 --- a/arch/arm/include/asm/arch-keystone/clock-k2l.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index 9f6cfb265f..9f6cfb265f 100644 --- a/arch/arm/include/asm/arch-keystone/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h index 85a046b89a..85a046b89a 100644 --- a/arch/arm/include/asm/arch-keystone/clock_defs.h +++ b/arch/arm/mach-keystone/include/mach/clock_defs.h diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/mach-keystone/include/mach/ddr3.h index b044d6f18f..a22c237c80 100644 --- a/arch/arm/include/asm/arch-keystone/ddr3.h +++ b/arch/arm/mach-keystone/include/mach/ddr3.h @@ -48,10 +48,9 @@ struct ddr3_emif_config { unsigned int sdrfc; }; -void ddr3_init(void); -int ddr3_get_size(void); +u32 ddr3_init(void); void ddr3_reset_ddrphy(void); -void ddr3_init_ecc(u32 base); +void ddr3_init_ecc(u32 base, u32 ddr3_size); void ddr3_disable_ecc(u32 base); void ddr3_check_ecc_int(u32 base); int ddr3_ecc_support_rmw(u32 base); diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/mach-keystone/include/mach/hardware-k2e.h index df499957e5..df499957e5 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2e.h diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h index 195c0d3003..195c0d3003 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/mach-keystone/include/mach/hardware-k2l.h index 4f1197ea92..4f1197ea92 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2l.h diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index 16cbcee12b..16cbcee12b 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h diff --git a/arch/arm/include/asm/arch-keystone/i2c_defs.h b/arch/arm/mach-keystone/include/mach/i2c_defs.h index d4256526cc..d4256526cc 100644 --- a/arch/arm/include/asm/arch-keystone/i2c_defs.h +++ b/arch/arm/mach-keystone/include/mach/i2c_defs.h diff --git a/arch/arm/include/asm/arch-keystone/mon.h b/arch/arm/mach-keystone/include/mach/mon.h index 33a28764bc..33a28764bc 100644 --- a/arch/arm/include/asm/arch-keystone/mon.h +++ b/arch/arm/mach-keystone/include/mach/mon.h diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/mach-keystone/include/mach/msmc.h index 083f5ba052..083f5ba052 100644 --- a/arch/arm/include/asm/arch-keystone/msmc.h +++ b/arch/arm/mach-keystone/include/mach/msmc.h diff --git a/arch/arm/include/asm/arch-keystone/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h index 70d22cf217..70d22cf217 100644 --- a/arch/arm/include/asm/arch-keystone/psc_defs.h +++ b/arch/arm/mach-keystone/include/mach/psc_defs.h diff --git a/arch/arm/include/asm/arch-keystone/xhci-keystone.h b/arch/arm/mach-keystone/include/mach/xhci-keystone.h index 3aab4e045f..3aab4e045f 100644 --- a/arch/arm/include/asm/arch-keystone/xhci-keystone.h +++ b/arch/arm/mach-keystone/include/mach/xhci-keystone.h diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/mach-keystone/init.c index c96845c4e2..c96845c4e2 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/mach-keystone/init.c diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/mach-keystone/keystone.c index 11a9357db4..11a9357db4 100644 --- a/arch/arm/cpu/armv7/keystone/keystone.c +++ b/arch/arm/mach-keystone/keystone.c diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/mach-keystone/msmc.c index 7899141d54..7899141d54 100644 --- a/arch/arm/cpu/armv7/keystone/msmc.c +++ b/arch/arm/mach-keystone/msmc.c diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/mach-keystone/psc.c index 237e776e87..237e776e87 100644 --- a/arch/arm/cpu/armv7/keystone/psc.c +++ b/arch/arm/mach-keystone/psc.c diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 45c6687d0b..45c6687d0b 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index df4756e4bd..df4756e4bd 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cache.c b/arch/arm/mach-kirkwood/cache.c index e18a3097dc..e18a3097dc 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cache.c +++ b/arch/arm/mach-kirkwood/cache.c diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 4c9d3fde47..4c9d3fde47 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index e77ac400d8..e77ac400d8 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index 926d347110..926d347110 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h b/arch/arm/mach-kirkwood/include/mach/gpio.h index aa8c5da36d..aa8c5da36d 100644 --- a/arch/arm/include/asm/arch-kirkwood/gpio.h +++ b/arch/arm/mach-kirkwood/include/mach/gpio.h diff --git a/arch/arm/include/asm/arch-kirkwood/kw88f6192.h b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h index de220d57d4..de220d57d4 100644 --- a/arch/arm/include/asm/arch-kirkwood/kw88f6192.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h diff --git a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h index ca88a300e0..ca88a300e0 100644 --- a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/mach-kirkwood/include/mach/mpp.h index 7c8f6eba97..7c8f6eba97 100644 --- a/arch/arm/include/asm/arch-kirkwood/mpp.h +++ b/arch/arm/mach-kirkwood/include/mach/mpp.h diff --git a/arch/arm/include/asm/arch-kirkwood/soc.h b/arch/arm/mach-kirkwood/include/mach/soc.h index 58ed71b186..58ed71b186 100644 --- a/arch/arm/include/asm/arch-kirkwood/soc.h +++ b/arch/arm/mach-kirkwood/include/mach/soc.h diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 7222504ed3..7222504ed3 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c diff --git a/arch/arm/cpu/arm926ejs/nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig index 265f336469..265f336469 100644 --- a/arch/arm/cpu/arm926ejs/nomadik/Kconfig +++ b/arch/arm/mach-nomadik/Kconfig diff --git a/arch/arm/cpu/arm926ejs/nomadik/Makefile b/arch/arm/mach-nomadik/Makefile index cdf1345d58..cdf1345d58 100644 --- a/arch/arm/cpu/arm926ejs/nomadik/Makefile +++ b/arch/arm/mach-nomadik/Makefile diff --git a/arch/arm/cpu/arm926ejs/nomadik/gpio.c b/arch/arm/mach-nomadik/gpio.c index eff5b2b75e..eff5b2b75e 100644 --- a/arch/arm/cpu/arm926ejs/nomadik/gpio.c +++ b/arch/arm/mach-nomadik/gpio.c diff --git a/arch/arm/include/asm/arch-nomadik/gpio.h b/arch/arm/mach-nomadik/include/mach/gpio.h index 311758ae1a..311758ae1a 100644 --- a/arch/arm/include/asm/arch-nomadik/gpio.h +++ b/arch/arm/mach-nomadik/include/mach/gpio.h diff --git a/arch/arm/include/asm/arch-nomadik/mtu.h b/arch/arm/mach-nomadik/include/mach/mtu.h index f89f242247..f89f242247 100644 --- a/arch/arm/include/asm/arch-nomadik/mtu.h +++ b/arch/arm/mach-nomadik/include/mach/mtu.h diff --git a/arch/arm/cpu/arm926ejs/nomadik/reset.S b/arch/arm/mach-nomadik/reset.S index ec954726ae..ec954726ae 100644 --- a/arch/arm/cpu/arm926ejs/nomadik/reset.S +++ b/arch/arm/mach-nomadik/reset.S diff --git a/arch/arm/cpu/arm926ejs/nomadik/timer.c b/arch/arm/mach-nomadik/timer.c index 775d0b7488..775d0b7488 100644 --- a/arch/arm/cpu/arm926ejs/nomadik/timer.c +++ b/arch/arm/mach-nomadik/timer.c diff --git a/arch/arm/cpu/arm926ejs/orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 5a542629c7..5a542629c7 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 546ebcb52e..546ebcb52e 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/mach-orion5x/cpu.c index f88db3b1f9..f88db3b1f9 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/mach-orion5x/cpu.c diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/mach-orion5x/dram.c index 9ed93d25bc..9ed93d25bc 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/dram.c +++ b/arch/arm/mach-orion5x/dram.c diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/mach-orion5x/include/mach/cpu.h index 08a450f1f3..08a450f1f3 100644 --- a/arch/arm/include/asm/arch-orion5x/cpu.h +++ b/arch/arm/mach-orion5x/include/mach/cpu.h diff --git a/arch/arm/include/asm/arch-orion5x/mv88f5182.h b/arch/arm/mach-orion5x/include/mach/mv88f5182.h index e6c71ae1b3..e6c71ae1b3 100644 --- a/arch/arm/include/asm/arch-orion5x/mv88f5182.h +++ b/arch/arm/mach-orion5x/include/mach/mv88f5182.h diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index fbb1de8c0d..fbb1de8c0d 100644 --- a/arch/arm/include/asm/arch-orion5x/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h diff --git a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S index 4dacc296e4..4dacc296e4 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S +++ b/arch/arm/mach-orion5x/lowlevel_init.S diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/mach-orion5x/timer.c index ec4f6bee8e..ec4f6bee8e 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/timer.c +++ b/arch/arm/mach-orion5x/timer.c diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig new file mode 100644 index 0000000000..8615248377 --- /dev/null +++ b/arch/arm/mach-tegra/Kconfig @@ -0,0 +1,52 @@ +if TEGRA + +choice + prompt "Tegra SoC select" + +config TEGRA20 + bool "Tegra20 family" + +config TEGRA30 + bool "Tegra30 family" + +config TEGRA114 + bool "Tegra114 family" + +config TEGRA124 + bool "Tegra124 family" + +endchoice + +config SYS_MALLOC_F + default y + +config SYS_MALLOC_F_LEN + default 0x1800 + +config USE_PRIVATE_LIBGCC + default y + +config DM + default y + +config DM_SERIAL + default y + +config DM_SPI + default y + +config DM_SPI_FLASH + default y + +config DM_I2C + default y + +config DM_GPIO + default y + +source "arch/arm/mach-tegra/tegra20/Kconfig" +source "arch/arm/mach-tegra/tegra30/Kconfig" +source "arch/arm/mach-tegra/tegra114/Kconfig" +source "arch/arm/mach-tegra/tegra124/Kconfig" + +endif diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/mach-tegra/Makefile index a78869ee23..04cef0a252 100644 --- a/arch/arm/cpu/tegra-common/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -7,6 +7,13 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += cpu.o +else +obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o +endif + obj-y += ap.o obj-y += board.o obj-y += cache.o @@ -17,3 +24,8 @@ obj-y += powergate.o obj-y += xusb-padctl.o obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-$(CONFIG_TEGRA124) += vpr.o + +obj-$(CONFIG_TEGRA20) += tegra20/ +obj-$(CONFIG_TEGRA30) += tegra30/ +obj-$(CONFIG_TEGRA114) += tegra114/ +obj-$(CONFIG_TEGRA124) += tegra124/ diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/mach-tegra/ap.c index a17dfd1e22..a17dfd1e22 100644 --- a/arch/arm/cpu/tegra-common/ap.c +++ b/arch/arm/mach-tegra/ap.c diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/mach-tegra/board.c index b6a84a5774..b6a84a5774 100644 --- a/arch/arm/cpu/tegra-common/board.c +++ b/arch/arm/mach-tegra/board.c diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/mach-tegra/cache.c index 94f5bce90e..94f5bce90e 100644 --- a/arch/arm/cpu/tegra-common/cache.c +++ b/arch/arm/mach-tegra/cache.c diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/mach-tegra/clock.c index 11c7435505..11c7435505 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/mach-tegra/clock.c diff --git a/arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c b/arch/arm/mach-tegra/cmd_enterrcm.c index a94ec93e7b..a94ec93e7b 100644 --- a/arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c +++ b/arch/arm/mach-tegra/cmd_enterrcm.c diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/mach-tegra/cpu.c index c6f3b029a1..c6f3b029a1 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/mach-tegra/cpu.c diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/mach-tegra/cpu.h index b4ca44fce1..b4ca44fce1 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.h +++ b/arch/arm/mach-tegra/cpu.h diff --git a/arch/arm/cpu/tegra-common/lowlevel_init.S b/arch/arm/mach-tegra/lowlevel_init.S index a211bb3b1a..a211bb3b1a 100644 --- a/arch/arm/cpu/tegra-common/lowlevel_init.S +++ b/arch/arm/mach-tegra/lowlevel_init.S diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 6e3ab0c14c..6e3ab0c14c 100644 --- a/arch/arm/cpu/tegra-common/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c diff --git a/arch/arm/cpu/tegra-common/powergate.c b/arch/arm/mach-tegra/powergate.c index 439cff36b9..439cff36b9 100644 --- a/arch/arm/cpu/tegra-common/powergate.c +++ b/arch/arm/mach-tegra/powergate.c diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/mach-tegra/spl.c index e0f9d5b6b4..e0f9d5b6b4 100644 --- a/arch/arm/cpu/arm720t/tegra-common/spl.c +++ b/arch/arm/mach-tegra/spl.c diff --git a/arch/arm/cpu/tegra-common/sys_info.c b/arch/arm/mach-tegra/sys_info.c index 5933c35ddd..5933c35ddd 100644 --- a/arch/arm/cpu/tegra-common/sys_info.c +++ b/arch/arm/mach-tegra/sys_info.c diff --git a/arch/arm/cpu/armv7/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig index 31012bc770..31012bc770 100644 --- a/arch/arm/cpu/armv7/tegra114/Kconfig +++ b/arch/arm/mach-tegra/tegra114/Kconfig diff --git a/arch/arm/cpu/tegra114-common/Makefile b/arch/arm/mach-tegra/tegra114/Makefile index d959b575ce..7489f5f146 100644 --- a/arch/arm/cpu/tegra114-common/Makefile +++ b/arch/arm/mach-tegra/tegra114/Makefile @@ -1,9 +1,6 @@ # # Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. # -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # This program is free software; you can redistribute it and/or modify it # under the terms and conditions of the GNU General Public License, # version 2, as published by the Free Software Foundation. @@ -17,4 +14,6 @@ # along with this program. If not, see <http://www.gnu.org/licenses/>. # +obj-$(CONFIG_SPL_BUILD) += cpu.o + obj-y += clock.o funcmux.o pinmux.o diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index d5194e11b5..d5194e11b5 100644 --- a/arch/arm/cpu/tegra114-common/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c index 5ed3bb9d9a..18dc1af1b4 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/mach-tegra/tegra114/cpu.c @@ -22,7 +22,7 @@ #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> -#include "../tegra-common/cpu.h" +#include "../cpu.h" /* Tegra114-specific CPU init code */ static void enable_cpu_power_rail(void) diff --git a/arch/arm/cpu/tegra114-common/funcmux.c b/arch/arm/mach-tegra/tegra114/funcmux.c index 52441c71e6..52441c71e6 100644 --- a/arch/arm/cpu/tegra114-common/funcmux.c +++ b/arch/arm/mach-tegra/tegra114/funcmux.c diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/mach-tegra/tegra114/pinmux.c index 3e5acb93ce..3e5acb93ce 100644 --- a/arch/arm/cpu/tegra114-common/pinmux.c +++ b/arch/arm/mach-tegra/tegra114/pinmux.c diff --git a/arch/arm/cpu/armv7/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig index 88f627c932..88f627c932 100644 --- a/arch/arm/cpu/armv7/tegra124/Kconfig +++ b/arch/arm/mach-tegra/tegra124/Kconfig diff --git a/arch/arm/cpu/tegra124-common/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index 7b59fb1216..ef2da29f30 100644 --- a/arch/arm/cpu/tegra124-common/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -5,6 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_SPL_BUILD) += cpu.o + obj-y += clock.o obj-y += funcmux.o obj-y += pinmux.o diff --git a/arch/arm/cpu/tegra124-common/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index fc8bd194dd..fc8bd194dd 100644 --- a/arch/arm/cpu/tegra124-common/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index 6ff6aeb546..974f203f12 100644 --- a/arch/arm/cpu/arm720t/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -15,7 +15,7 @@ #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/ap.h> -#include "../tegra-common/cpu.h" +#include "../cpu.h" /* Tegra124-specific CPU init code */ diff --git a/arch/arm/cpu/tegra124-common/funcmux.c b/arch/arm/mach-tegra/tegra124/funcmux.c index cced787e6b..cced787e6b 100644 --- a/arch/arm/cpu/tegra124-common/funcmux.c +++ b/arch/arm/mach-tegra/tegra124/funcmux.c diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/mach-tegra/tegra124/pinmux.c index c6685eaae1..c6685eaae1 100644 --- a/arch/arm/cpu/tegra124-common/pinmux.c +++ b/arch/arm/mach-tegra/tegra124/pinmux.c diff --git a/arch/arm/cpu/tegra124-common/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c index 43af883f2c..43af883f2c 100644 --- a/arch/arm/cpu/tegra124-common/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c diff --git a/arch/arm/cpu/armv7/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index a354e2ad1f..a354e2ad1f 100644 --- a/arch/arm/cpu/armv7/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index 0e4b3fc1dd..d48f9bb325 100644 --- a/arch/arm/cpu/tegra20-common/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -1,12 +1,16 @@ # # (C) Copyright 2010,2011 Nvidia Corporation. # -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += cpu.o +else +obj-$(CONFIG_PWM_TEGRA) += pwm.o +obj-$(CONFIG_VIDEO_TEGRA) += display.o +endif + # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. CFLAGS_warmboot_avp.o += -march=armv4t diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index 7b9e10cd93..7b9e10cd93 100644 --- a/arch/arm/cpu/tegra20-common/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c b/arch/arm/mach-tegra/tegra20/cpu.c index 253389955f..67f49d7756 100644 --- a/arch/arm/cpu/arm720t/tegra20/cpu.c +++ b/arch/arm/mach-tegra/tegra20/cpu.c @@ -18,7 +18,7 @@ #include <asm/io.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/pmc.h> -#include "../tegra-common/cpu.h" +#include "../cpu.h" static void enable_cpu_power_rail(void) { diff --git a/arch/arm/cpu/tegra20-common/crypto.c b/arch/arm/mach-tegra/tegra20/crypto.c index ec95d7ceb1..ec95d7ceb1 100644 --- a/arch/arm/cpu/tegra20-common/crypto.c +++ b/arch/arm/mach-tegra/tegra20/crypto.c diff --git a/arch/arm/cpu/tegra20-common/crypto.h b/arch/arm/mach-tegra/tegra20/crypto.h index f59b92768a..f59b92768a 100644 --- a/arch/arm/cpu/tegra20-common/crypto.h +++ b/arch/arm/mach-tegra/tegra20/crypto.h diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/mach-tegra/tegra20/display.c index 61efed6464..61efed6464 100644 --- a/arch/arm/cpu/armv7/tegra20/display.c +++ b/arch/arm/mach-tegra/tegra20/display.c diff --git a/arch/arm/cpu/tegra20-common/emc.c b/arch/arm/mach-tegra/tegra20/emc.c index ed2462ab0f..ed2462ab0f 100644 --- a/arch/arm/cpu/tegra20-common/emc.c +++ b/arch/arm/mach-tegra/tegra20/emc.c diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/mach-tegra/tegra20/funcmux.c index 0df4a0738d..0df4a0738d 100644 --- a/arch/arm/cpu/tegra20-common/funcmux.c +++ b/arch/arm/mach-tegra/tegra20/funcmux.c diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/mach-tegra/tegra20/pinmux.c index e484f991bf..e484f991bf 100644 --- a/arch/arm/cpu/tegra20-common/pinmux.c +++ b/arch/arm/mach-tegra/tegra20/pinmux.c diff --git a/arch/arm/cpu/tegra20-common/pmu.c b/arch/arm/mach-tegra/tegra20/pmu.c index a774246a27..a774246a27 100644 --- a/arch/arm/cpu/tegra20-common/pmu.c +++ b/arch/arm/mach-tegra/tegra20/pmu.c diff --git a/arch/arm/cpu/armv7/tegra20/pwm.c b/arch/arm/mach-tegra/tegra20/pwm.c index 5b886363f8..5b886363f8 100644 --- a/arch/arm/cpu/armv7/tegra20/pwm.c +++ b/arch/arm/mach-tegra/tegra20/pwm.c diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 5fdc4bbb50..5fdc4bbb50 100644 --- a/arch/arm/cpu/tegra20-common/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 27ce5f480f..27ce5f480f 100644 --- a/arch/arm/cpu/tegra20-common/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.h b/arch/arm/mach-tegra/tegra20/warmboot_avp.h index 7b86acb156..7b86acb156 100644 --- a/arch/arm/cpu/tegra20-common/warmboot_avp.h +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.h diff --git a/arch/arm/cpu/armv7/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index 3abdc7ba17..3abdc7ba17 100644 --- a/arch/arm/cpu/armv7/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig diff --git a/arch/arm/cpu/tegra30-common/Makefile b/arch/arm/mach-tegra/tegra30/Makefile index d2d616e8a4..bc250deba8 100644 --- a/arch/arm/cpu/tegra30-common/Makefile +++ b/arch/arm/mach-tegra/tegra30/Makefile @@ -1,9 +1,6 @@ # # Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. # -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # This program is free software; you can redistribute it and/or modify it # under the terms and conditions of the GNU General Public License, # version 2, as published by the Free Software Foundation. @@ -17,4 +14,6 @@ # along with this program. If not, see <http://www.gnu.org/licenses/>. # +obj-$(CONFIG_SPL_BUILD) += cpu.o + obj-y += clock.o funcmux.o pinmux.o diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 0eb0f0ade3..0eb0f0ade3 100644 --- a/arch/arm/cpu/tegra30-common/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c index 9003902e3f..c76e74c65f 100644 --- a/arch/arm/cpu/arm720t/tegra30/cpu.c +++ b/arch/arm/mach-tegra/tegra30/cpu.c @@ -22,7 +22,7 @@ #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/tegra_i2c.h> -#include "../tegra-common/cpu.h" +#include "../cpu.h" /* Tegra30-specific CPU init code */ void tegra_i2c_ll_write_addr(uint addr, uint config) diff --git a/arch/arm/cpu/tegra30-common/funcmux.c b/arch/arm/mach-tegra/tegra30/funcmux.c index 409335ce1d..409335ce1d 100644 --- a/arch/arm/cpu/tegra30-common/funcmux.c +++ b/arch/arm/mach-tegra/tegra30/funcmux.c diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/mach-tegra/tegra30/pinmux.c index 7eb05743b4..7eb05743b4 100644 --- a/arch/arm/cpu/tegra30-common/pinmux.c +++ b/arch/arm/mach-tegra/tegra30/pinmux.c diff --git a/arch/arm/cpu/tegra-common/vpr.c b/arch/arm/mach-tegra/vpr.c index f695811c9b..f695811c9b 100644 --- a/arch/arm/cpu/tegra-common/vpr.c +++ b/arch/arm/mach-tegra/vpr.c diff --git a/arch/arm/cpu/tegra-common/xusb-padctl.c b/arch/arm/mach-tegra/xusb-padctl.c index 65f8d2ea96..65f8d2ea96 100644 --- a/arch/arm/cpu/tegra-common/xusb-padctl.c +++ b/arch/arm/mach-tegra/xusb-padctl.c diff --git a/arch/arm/cpu/arm926ejs/versatile/Kconfig b/arch/arm/mach-versatile/Kconfig index d2e76f4afc..d2e76f4afc 100644 --- a/arch/arm/cpu/arm926ejs/versatile/Kconfig +++ b/arch/arm/mach-versatile/Kconfig diff --git a/arch/arm/cpu/arm926ejs/versatile/Makefile b/arch/arm/mach-versatile/Makefile index 907f5161a8..907f5161a8 100644 --- a/arch/arm/cpu/arm926ejs/versatile/Makefile +++ b/arch/arm/mach-versatile/Makefile diff --git a/arch/arm/cpu/arm926ejs/versatile/reset.S b/arch/arm/mach-versatile/reset.S index 1c557b0d91..1c557b0d91 100644 --- a/arch/arm/cpu/arm926ejs/versatile/reset.S +++ b/arch/arm/mach-versatile/reset.S diff --git a/arch/arm/cpu/arm926ejs/versatile/timer.c b/arch/arm/mach-versatile/timer.c index 5d694d85ef..5d694d85ef 100644 --- a/arch/arm/cpu/arm926ejs/versatile/timer.c +++ b/arch/arm/mach-versatile/timer.c diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk index 469185e8b4..8252f598c3 100644 --- a/arch/avr32/config.mk +++ b/arch/avr32/config.mk @@ -9,6 +9,9 @@ ifeq ($(CROSS_COMPILE),) CROSS_COMPILE := avr32-linux- endif +# avr32 has generic board support +__HAVE_ARCH_GENERIC_BOARD := y + CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax diff --git a/arch/avr32/cpu/Makefile b/arch/avr32/cpu/Makefile index 00cede3fd9..e111db3e75 100644 --- a/arch/avr32/cpu/Makefile +++ b/arch/avr32/cpu/Makefile @@ -16,5 +16,6 @@ obj-y += cache.o obj-y += interrupts.o obj-$(CONFIG_PORTMUX_PIO) += portmux-pio.o obj-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o +obj-y += mmc.o obj-$(if $(filter at32ap700x,$(SOC)),y) += at32ap700x/ diff --git a/arch/avr32/cpu/at32ap700x/mmu.c b/arch/avr32/cpu/at32ap700x/mmu.c index 0e28b21eef..f5e62f27eb 100644 --- a/arch/avr32/cpu/at32ap700x/mmu.c +++ b/arch/avr32/cpu/at32ap700x/mmu.c @@ -7,7 +7,7 @@ void mmu_init_r(unsigned long dest_addr) uintptr_t vmr_table_addr; /* Round monitor address down to the nearest page boundary */ - dest_addr &= PAGE_ADDR_MASK; + dest_addr &= MMU_PAGE_ADDR_MASK; /* Initialize TLB entry 0 to cover the monitor, and lock it */ sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V)); @@ -36,7 +36,7 @@ int mmu_handle_tlb_miss(void) unsigned int fault_pgno; int first, last; - fault_pgno = sysreg_read(TLBEAR) >> PAGE_SHIFT; + fault_pgno = sysreg_read(TLBEAR) >> MMU_PAGE_SHIFT; vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR); /* Do a binary search through the VM ranges */ @@ -60,8 +60,8 @@ int mmu_handle_tlb_miss(void) /* Got it; let's slam it into the TLB */ uint32_t tlbelo; - tlbelo = vmr->phys & ~PAGE_ADDR_MASK; - tlbelo |= fault_pgno << PAGE_SHIFT; + tlbelo = vmr->phys & ~MMU_PAGE_ADDR_MASK; + tlbelo |= fault_pgno << MMU_PAGE_SHIFT; sysreg_write(TLBELO, tlbelo); __builtin_tlbw(); diff --git a/arch/avr32/cpu/cpu.c b/arch/avr32/cpu/cpu.c index cef630ed45..cd226a6f71 100644 --- a/arch/avr32/cpu/cpu.c +++ b/arch/avr32/cpu/cpu.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; -int cpu_init(void) +int arch_cpu_init(void) { extern void _evba(void); diff --git a/arch/avr32/cpu/exception.c b/arch/avr32/cpu/exception.c index 5d1bc689f8..d6991f6668 100644 --- a/arch/avr32/cpu/exception.c +++ b/arch/avr32/cpu/exception.c @@ -96,11 +96,11 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs) printf("CPU Mode: %s\n", cpu_modes[mode]); /* Avoid exception loops */ - if (regs->sp < (gd->arch.stack_end - CONFIG_STACKSIZE) - || regs->sp >= gd->arch.stack_end) + if (regs->sp < (gd->start_addr_sp - CONFIG_STACKSIZE) || + regs->sp >= gd->start_addr_sp) printf("\nStack pointer seems bogus, won't do stack dump\n"); else - dump_mem("\nStack: ", regs->sp, gd->arch.stack_end); + dump_mem("\nStack: ", regs->sp, gd->start_addr_sp); panic("Unhandled exception\n"); } diff --git a/arch/avr32/cpu/mmc.c b/arch/avr32/cpu/mmc.c new file mode 100644 index 0000000000..b7213e4e7a --- /dev/null +++ b/arch/avr32/cpu/mmc.c @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2004-2006 Atmel Corporation + * Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <atmel_mci.h> +#include <asm/arch/hardware.h> + +/* provide cpu_mmc_init, to overwrite provide board_mmc_init */ +int cpu_mmc_init(bd_t *bd) +{ + /* This calls the atmel_mci_init in gen_atmel_mci.c */ + return atmel_mci_init((void *)ATMEL_BASE_MMCI); +} diff --git a/arch/avr32/cpu/u-boot.lds b/arch/avr32/cpu/u-boot.lds index cb29a22b1e..b0180e3534 100644 --- a/arch/avr32/cpu/u-boot.lds +++ b/arch/avr32/cpu/u-boot.lds @@ -48,9 +48,11 @@ SECTIONS _edata = .; .bss (NOLOAD) : { + __bss_start = .; *(.bss) *(.bss.*) } . = ALIGN(8); __bss_end = .; + __init_end = .; } diff --git a/arch/avr32/include/asm/arch-at32ap700x/mmu.h b/arch/avr32/include/asm/arch-at32ap700x/mmu.h index fcd9a05609..4736312f5d 100644 --- a/arch/avr32/include/asm/arch-at32ap700x/mmu.h +++ b/arch/avr32/include/asm/arch-at32ap700x/mmu.h @@ -13,9 +13,9 @@ #include <asm/sysreg.h> -#define PAGE_SHIFT 20 -#define PAGE_SIZE (1UL << PAGE_SHIFT) -#define PAGE_ADDR_MASK (~(PAGE_SIZE - 1)) +#define MMU_PAGE_SHIFT 20 +#define MMU_PAGE_SIZE (1UL << MMU_PAGE_SHIFT) +#define MMU_PAGE_ADDR_MASK (~(MMU_PAGE_SIZE - 1)) #define MMU_VMR_CACHE_NONE \ (SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D)) diff --git a/arch/avr32/include/asm/config.h b/arch/avr32/include/asm/config.h index 63056a4dfa..529fe227a6 100644 --- a/arch/avr32/include/asm/config.h +++ b/arch/avr32/include/asm/config.h @@ -8,5 +8,6 @@ #define _ASM_CONFIG_H_ #define CONFIG_NEEDS_MANUAL_RELOC +#define CONFIG_SYS_GENERIC_GLOBAL_DATA #endif diff --git a/arch/avr32/include/asm/dma-mapping.h b/arch/avr32/include/asm/dma-mapping.h index dbdd2fee38..1cde8275f4 100644 --- a/arch/avr32/include/asm/dma-mapping.h +++ b/arch/avr32/include/asm/dma-mapping.h @@ -14,7 +14,12 @@ enum dma_data_direction { DMA_TO_DEVICE = 1, DMA_FROM_DEVICE = 2, }; -extern void *dma_alloc_coherent(size_t len, unsigned long *handle); + +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); + return (void *)*handle; +} static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, enum dma_data_direction dir) diff --git a/arch/avr32/include/asm/global_data.h b/arch/avr32/include/asm/global_data.h index d82fb7cc6d..60abd00782 100644 --- a/arch/avr32/include/asm/global_data.h +++ b/arch/avr32/include/asm/global_data.h @@ -8,7 +8,6 @@ /* Architecture-specific global data */ struct arch_global_data { - unsigned long stack_end; /* highest stack address */ unsigned long cpu_hz; /* cpu core clock frequency */ }; diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h index 6aef808749..8b047ec7c8 100644 --- a/arch/avr32/include/asm/u-boot.h +++ b/arch/avr32/include/asm/u-boot.h @@ -6,6 +6,11 @@ #ifndef __ASM_U_BOOT_H__ #define __ASM_U_BOOT_H__ 1 +#ifdef CONFIG_SYS_GENERIC_BOARD +/* Use the generic board which requires a unified bd_info */ +#include <asm-generic/u-boot.h> +#else + typedef struct bd_info { unsigned char bi_phy_id[4]; unsigned long bi_board_number; @@ -22,7 +27,12 @@ typedef struct bd_info { #define bi_memstart bi_dram[0].start #define bi_memsize bi_dram[0].size +#endif + /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_AVR32 +int arch_cpu_init(void); +int dram_init(void); + #endif /* __ASM_U_BOOT_H__ */ diff --git a/arch/avr32/lib/Makefile b/arch/avr32/lib/Makefile index bb45cbe153..6750913630 100644 --- a/arch/avr32/lib/Makefile +++ b/arch/avr32/lib/Makefile @@ -8,6 +8,9 @@ # obj-y += memset.o +ifndef CONFIG_SYS_GENERIC_BOARD obj-y += board.o +endif obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += interrupts.o +obj-y += dram_init.o diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index bf0997f98d..99aa96e23f 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -9,7 +9,6 @@ #include <stdio_dev.h> #include <version.h> #include <net.h> -#include <atmel_mci.h> #ifdef CONFIG_BITBANGMII #include <miiphy.h> @@ -30,6 +29,12 @@ DECLARE_GLOBAL_DATA_PTR; unsigned long monitor_flash_len; +__weak void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + /* Weak aliases for optional board functions */ static int __do_nothing(void) { @@ -38,57 +43,6 @@ static int __do_nothing(void) int board_postclk_init(void) __attribute__((weak, alias("__do_nothing"))); int board_early_init_r(void) __attribute__((weak, alias("__do_nothing"))); -/* provide cpu_mmc_init, to overwrite provide board_mmc_init */ -int cpu_mmc_init(bd_t *bd) -{ - /* This calls the atmel_mci_init in gen_atmel_mci.c */ - return atmel_mci_init((void *)ATMEL_BASE_MMCI); -} - -#ifdef CONFIG_SYS_DMA_ALLOC_LEN -#include <asm/arch/cacheflush.h> -#include <asm/io.h> - -static unsigned long dma_alloc_start; -static unsigned long dma_alloc_end; -static unsigned long dma_alloc_brk; - -static void dma_alloc_init(void) -{ - unsigned long monitor_addr; - - monitor_addr = CONFIG_SYS_MONITOR_BASE + gd->reloc_off; - dma_alloc_end = monitor_addr - CONFIG_SYS_MALLOC_LEN; - dma_alloc_start = dma_alloc_end - CONFIG_SYS_DMA_ALLOC_LEN; - dma_alloc_brk = dma_alloc_start; - - printf("DMA: Using memory from 0x%08lx to 0x%08lx\n", - dma_alloc_start, dma_alloc_end); - - invalidate_dcache_range((unsigned long)cached(dma_alloc_start), - dma_alloc_end); -} - -void *dma_alloc_coherent(size_t len, unsigned long *handle) -{ - unsigned long paddr = dma_alloc_brk; - - if (dma_alloc_brk + len > dma_alloc_end) - return NULL; - - dma_alloc_brk = ((paddr + len + CONFIG_SYS_DCACHE_LINESZ - 1) - & ~(CONFIG_SYS_DCACHE_LINESZ - 1)); - - *handle = paddr; - return uncached(paddr); -} -#else -static inline void dma_alloc_init(void) -{ - -} -#endif - static int init_baudrate(void) { gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); @@ -134,7 +88,6 @@ void board_init_f(ulong board_type) unsigned long monitor_len; unsigned long monitor_addr; unsigned long addr; - long sdram_size; /* Initialize the global data pointer */ memset(&gd_data, 0, sizeof(gd_data)); @@ -142,17 +95,17 @@ void board_init_f(ulong board_type) /* Perform initialization sequence */ board_early_init_f(); - cpu_init(); + arch_cpu_init(); board_postclk_init(); env_init(); init_baudrate(); serial_init(); console_init_f(); display_banner(); - sdram_size = initdram(board_type); + dram_init(); /* If we have no SDRAM, we can't go on */ - if (sdram_size <= 0) + if (gd->ram_size <= 0) panic("No working SDRAM available\n"); /* @@ -166,7 +119,7 @@ void board_init_f(ulong board_type) * - global data struct * - stack */ - addr = CONFIG_SYS_SDRAM_BASE + sdram_size; + addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; monitor_len = (char *)(&__bss_end) - _text; /* @@ -180,12 +133,6 @@ void board_init_f(ulong board_type) /* Reserve memory for malloc() */ addr -= CONFIG_SYS_MALLOC_LEN; -#ifdef CONFIG_SYS_DMA_ALLOC_LEN - /* Reserve DMA memory (must be cache aligned) */ - addr &= ~(CONFIG_SYS_DCACHE_LINESZ - 1); - addr -= CONFIG_SYS_DMA_ALLOC_LEN; -#endif - #ifdef CONFIG_LCD #ifdef CONFIG_FB_ADDR printf("LCD: Frame buffer allocated at preset 0x%08x\n", @@ -210,16 +157,11 @@ void board_init_f(ulong board_type) /* And finally, a new, bigger stack. */ new_sp = (unsigned long *)addr; - gd->arch.stack_end = addr; + gd->start_addr_sp = addr; *(--new_sp) = 0; *(--new_sp) = 0; - /* - * Initialize the board information struct with the - * information we have. - */ - bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - bd->bi_dram[0].size = sdram_size; + dram_init_banksize(); memcpy(new_gd, gd, sizeof(gd_t)); @@ -264,7 +206,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) /* The malloc area is right below the monitor image in RAM */ mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off - CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN); - dma_alloc_init(); enable_interrupts(); diff --git a/arch/avr32/lib/dram_init.c b/arch/avr32/lib/dram_init.c new file mode 100644 index 0000000000..5078e77f17 --- /dev/null +++ b/arch/avr32/lib/dram_init.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2015 Andreas Bießmann <andreas.devel@googlemail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + /* check for the maximum amount of memory possible on AP7000 devices */ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + (256<<20)); + return 0; +} diff --git a/arch/avr32/lib/interrupts.c b/arch/avr32/lib/interrupts.c index bacb2d186a..5f3a49e152 100644 --- a/arch/avr32/lib/interrupts.c +++ b/arch/avr32/lib/interrupts.c @@ -7,6 +7,11 @@ #include <asm/sysreg.h> +int interrupt_init(void) +{ + return 0; +} + void enable_interrupts(void) { asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET)); diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index 71bb9d776f..7202c3fc46 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -424,6 +424,14 @@ phys_size_t initdram(int board_type) int write_recovery; phys_size_t dram_size = 0; + if (IS_ENABLED(CONFIG_SYS_RAMBOOT)) { + /* + * Reduce RAM size to avoid overwriting memory used by + * current stack? Not sure what is happening. + */ + return sdram_memsize() / 2; + } + num_dimm_banks = sizeof(iic0_dimm_addr); /*------------------------------------------------------------------ diff --git a/arch/powerpc/cpu/ppc4xx/config.mk b/arch/powerpc/cpu/ppc4xx/config.mk index f87c9dc49b..9cb41bb3b5 100644 --- a/arch/powerpc/cpu/ppc4xx/config.mk +++ b/arch/powerpc/cpu/ppc4xx/config.mk @@ -7,10 +7,7 @@ PLATFORM_CPPFLAGS += -mstring -msoft-float -cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h -is440:=$(shell grep CONFIG_440 $(cfg)) - -ifneq (,$(findstring CONFIG_440,$(is440))) +ifneq (,$(CONFIG_440)) PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440 else PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405 diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index e5a0e21e36..5f5c72002e 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -450,10 +450,12 @@ cpu_init_f (void) PLB4Ax_ACR_RDP_4DEEP); #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ +#ifndef CONFIG_SYS_GENERIC_BOARD gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset((void *)gd, 0, sizeof(gd_t)); +#endif } /* diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 09a02d771c..7a0f0d25d1 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -760,6 +760,15 @@ _start: #endif bl cpu_init_f /* run low-level CPU init code (from Flash) */ +#ifdef CONFIG_SYS_GENERIC_BOARD + mr r3, r1 + bl board_init_f_mem + mr r1, r3 + li r0,0 + stwu r0, -4(r1) + stwu r0, -4(r1) +#endif + li r3, 0 bl board_init_f /* NOTREACHED - board_init_f() does not return */ @@ -1027,7 +1036,14 @@ _start: GET_GOT /* initialize GOT access */ bl cpu_init_f /* run low-level CPU init code (from Flash) */ - +#ifdef CONFIG_SYS_GENERIC_BOARD + mr r3, r1 + bl board_init_f_mem + mr r1, r3 + stwu r0, -4(r1) + stwu r0, -4(r1) +#endif + li r3, 0 bl board_init_f /* run first part of init code (from Flash) */ /* NOTREACHED - board_init_f() does not return */ diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds index 87731785ec..198050853a 100644 --- a/arch/powerpc/cpu/ppc4xx/u-boot.lds +++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds @@ -76,9 +76,13 @@ SECTIONS . = ALIGN(256); __init_begin = .; .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); + .data.init : { + *(.data.init) + . = ALIGN(256); + LONG(0) LONG(0) /* Extend u-boot.bin to here */ + } __init_end = .; + _end = .; #ifndef CONFIG_SPL #ifdef CONFIG_440 diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile new file mode 100644 index 0000000000..ad104b9315 --- /dev/null +++ b/arch/powerpc/dts/Makefile @@ -0,0 +1,11 @@ +dtb-$(CONFIG_TARGET_CANYONLANDS) += arches.dtb canyonlands.dtb glacier.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/powerpc/dts/arches.dts b/arch/powerpc/dts/arches.dts new file mode 100644 index 0000000000..bd5ebfde2b --- /dev/null +++ b/arch/powerpc/dts/arches.dts @@ -0,0 +1,339 @@ +/* + * Device Tree Source for AMCC Arches (dual 460GT board) + * + * (C) Copyright 2008 Applied Micro Circuits Corporation + * Victor Gallardo <vgallardo@amcc.com> + * Adam Graham <agraham@amcc.com> + * + * Based on the glacier.dts file + * Stefan Roese <sr@denx.de> + * Copyright 2008 DENX Software Engineering + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "amcc,arches"; + compatible = "amcc,arches"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + ethernet2 = &EMAC2; + serial0 = &UART0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,460GT"; + reg = <0x00000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + timebase-frequency = <0>; /* Filled in by U-Boot */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + next-level-cache = <&L2C0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ + }; + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0x0c0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0x0d0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC2: interrupt-controller2 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <2>; + dcr-reg = <0x0e0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC3: interrupt-controller3 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <3>; + dcr-reg = <0x0f0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + SDR0: sdr { + compatible = "ibm,sdr-460gt"; + dcr-reg = <0x00e 0x002>; + }; + + CPR0: cpr { + compatible = "ibm,cpr-460gt"; + dcr-reg = <0x00c 0x002>; + }; + + L2C0: l2c { + compatible = "ibm,l2-cache-460gt", "ibm,l2-cache"; + dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ + 0x030 0x008>; /* L2 cache DCR's */ + cache-line-size = <32>; /* 32 bytes */ + cache-size = <262144>; /* L2, 256K */ + interrupt-parent = <&UIC1>; + interrupts = <11 1>; + }; + + plb { + compatible = "ibm,plb-460gt", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by U-Boot */ + + SDRAM0: sdram { + compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; + dcr-reg = <0x010 0x002>; + }; + + CRYPTO: crypto@180000 { + compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto"; + reg = <4 0x00180000 0x80400>; + interrupt-parent = <&UIC0>; + interrupts = <0x1d 0x4>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; + dcr-reg = <0x180 0x062>; + num-tx-chans = <3>; + num-rx-chans = <24>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-parent = <&UIC2>; + interrupts = < /*TXEOB*/ 0x6 0x4 + /*RXEOB*/ 0x7 0x4 + /*SERR*/ 0x3 0x4 + /*TXDE*/ 0x4 0x4 + /*RXDE*/ 0x5 0x4>; + desc-base-addr-high = <0x8>; + }; + + POB0: opb { + compatible = "ibm,opb-460gt", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + + EBC0: ebc { + compatible = "ibm,ebc-460gt", "ibm,ebc"; + dcr-reg = <0x012 0x002>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by U-Boot */ + /* ranges property is supplied by U-Boot */ + interrupts = <0x6 0x4>; + interrupt-parent = <&UIC1>; + + nor_flash@0,0 { + compatible = "amd,s29gl256n", "cfi-flash"; + bank-width = <2>; + reg = <0x00000000 0x00000000 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x001e0000>; + }; + partition@1e0000 { + label = "dtb"; + reg = <0x001e0000 0x00020000>; + }; + partition@200000 { + label = "root"; + reg = <0x00200000 0x00200000>; + }; + partition@400000 { + label = "user"; + reg = <0x00400000 0x01b60000>; + }; + partition@1f60000 { + label = "env"; + reg = <0x01f60000 0x00040000>; + }; + partition@1fa0000 { + label = "u-boot"; + reg = <0x01fa0000 0x00060000>; + }; + }; + }; + + UART0: serial@ef600300 { + device_type = "serial"; + compatible = "ns16550"; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC1>; + interrupts = <0x1 0x4>; + }; + + IIC0: i2c@ef600700 { + compatible = "ibm,iic-460gt", "ibm,iic"; + reg = <0xef600700 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x2 0x4>; + #address-cells = <1>; + #size-cells = <0>; + sttm@4a { + compatible = "ad,ad7414"; + reg = <0x4a>; + interrupt-parent = <&UIC1>; + interrupts = <0x0 0x8>; + }; + }; + + IIC1: i2c@ef600800 { + compatible = "ibm,iic-460gt", "ibm,iic"; + reg = <0xef600800 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x3 0x4>; + }; + + TAH0: emac-tah@ef601350 { + compatible = "ibm,tah-460gt", "ibm,tah"; + reg = <0xef601350 0x00000030>; + }; + + TAH1: emac-tah@ef601450 { + compatible = "ibm,tah-460gt", "ibm,tah"; + reg = <0xef601450 0x00000030>; + }; + + EMAC0: ethernet@ef600e00 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC0>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 + /*Wake*/ 0x1 &UIC2 0x14 0x4>; + reg = <0xef600e00 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <0>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + phy-mode = "sgmii"; + phy-map = <0xffffffff>; + gpcs-address = <0x0000000a>; + tah-device = <&TAH0>; + tah-channel = <0>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + }; + + EMAC1: ethernet@ef600f00 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC1>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 + /*Wake*/ 0x1 &UIC2 0x15 0x4>; + reg = <0xef600f00 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <1>; + mal-rx-channel = <8>; + cell-index = <1>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + phy-mode = "sgmii"; + phy-map = <0x00000000>; + gpcs-address = <0x0000000b>; + tah-device = <&TAH1>; + tah-channel = <1>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + mdio-device = <&EMAC0>; + }; + + EMAC2: ethernet@ef601100 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC2>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 + /*Wake*/ 0x1 &UIC2 0x16 0x4>; + reg = <0xef601100 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <2>; + mal-rx-channel = <16>; + cell-index = <2>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + tx-fifo-size-gige = <16384>; /* emac2&3 only */ + phy-mode = "sgmii"; + phy-map = <0x00000001>; + gpcs-address = <0x0000000C>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + mdio-device = <&EMAC0>; + }; + }; + }; +}; diff --git a/arch/powerpc/dts/canyonlands.dts b/arch/powerpc/dts/canyonlands.dts new file mode 100644 index 0000000000..0a2f5d7649 --- /dev/null +++ b/arch/powerpc/dts/canyonlands.dts @@ -0,0 +1,561 @@ +/* + * Device Tree Source for AMCC Canyonlands (460EX) + * + * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "amcc,canyonlands"; + compatible = "amcc,canyonlands"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + serial0 = &UART0; + serial1 = &UART1; + }; + + chosen { + stdout-path = &UART0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,460EX"; + reg = <0x00000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + timebase-frequency = <0>; /* Filled in by U-Boot */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + next-level-cache = <&L2C0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ + }; + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-460ex","ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0x0c0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-460ex","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0x0d0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC2: interrupt-controller2 { + compatible = "ibm,uic-460ex","ibm,uic"; + interrupt-controller; + cell-index = <2>; + dcr-reg = <0x0e0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC3: interrupt-controller3 { + compatible = "ibm,uic-460ex","ibm,uic"; + interrupt-controller; + cell-index = <3>; + dcr-reg = <0x0f0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + SDR0: sdr { + compatible = "ibm,sdr-460ex"; + dcr-reg = <0x00e 0x002>; + }; + + CPR0: cpr { + compatible = "ibm,cpr-460ex"; + dcr-reg = <0x00c 0x002>; + }; + + CPM0: cpm { + compatible = "ibm,cpm"; + dcr-access-method = "native"; + dcr-reg = <0x160 0x003>; + unused-units = <0x00000100>; + idle-doze = <0x02000000>; + standby = <0xfeff791d>; + }; + + L2C0: l2c { + compatible = "ibm,l2-cache-460ex", "ibm,l2-cache"; + dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ + 0x030 0x008>; /* L2 cache DCR's */ + cache-line-size = <32>; /* 32 bytes */ + cache-size = <262144>; /* L2, 256K */ + interrupt-parent = <&UIC1>; + interrupts = <11 1>; + }; + + plb { + compatible = "ibm,plb-460ex", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by U-Boot */ + + SDRAM0: sdram { + compatible = "ibm,sdram-460ex", "ibm,sdram-405gp"; + dcr-reg = <0x010 0x002>; + }; + + CRYPTO: crypto@180000 { + compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto"; + reg = <4 0x00180000 0x80400>; + interrupt-parent = <&UIC0>; + interrupts = <0x1d 0x4>; + }; + + HWRNG: hwrng@110000 { + compatible = "amcc,ppc460ex-rng", "ppc4xx-rng"; + reg = <4 0x00110000 0x50>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; + dcr-reg = <0x180 0x062>; + num-tx-chans = <2>; + num-rx-chans = <16>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-parent = <&UIC2>; + interrupts = < /*TXEOB*/ 0x6 0x4 + /*RXEOB*/ 0x7 0x4 + /*SERR*/ 0x3 0x4 + /*TXDE*/ 0x4 0x4 + /*RXDE*/ 0x5 0x4>; + }; + + USB0: ehci@bffd0400 { + compatible = "ibm,usb-ehci-460ex", "usb-ehci"; + interrupt-parent = <&UIC2>; + interrupts = <0x1d 4>; + reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>; + }; + + USB1: usb@bffd0000 { + compatible = "ohci-le"; + reg = <4 0xbffd0000 0x60>; + interrupt-parent = <&UIC2>; + interrupts = <0x1e 4>; + }; + + USBOTG0: usbotg@bff80000 { + compatible = "amcc,dwc-otg"; + reg = <0x4 0xbff80000 0x10000>; + interrupt-parent = <&USBOTG0>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupts = <0x0 0x1 0x2>; + interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4 + /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8 + /* DMA */ 0x2 &UIC0 0xc 0x4>; + }; + + SATA0: sata@bffd1000 { + compatible = "amcc,sata-460ex"; + reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>; + interrupt-parent = <&UIC3>; + interrupts = <0x0 0x4 /* SATA */ + 0x5 0x4>; /* AHBDMA */ + }; + + POB0: opb { + compatible = "ibm,opb-460ex", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + + EBC0: ebc { + compatible = "ibm,ebc-460ex", "ibm,ebc"; + dcr-reg = <0x012 0x002>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by U-Boot */ + /* ranges property is supplied by U-Boot */ + interrupts = <0x6 0x4>; + interrupt-parent = <&UIC1>; + + nor_flash@0,0 { + compatible = "amd,s29gl512n", "cfi-flash"; + bank-width = <2>; + reg = <0x00000000 0x00000000 0x04000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x001e0000>; + }; + partition@1e0000 { + label = "dtb"; + reg = <0x001e0000 0x00020000>; + }; + partition@200000 { + label = "ramdisk"; + reg = <0x00200000 0x01400000>; + }; + partition@1600000 { + label = "jffs2"; + reg = <0x01600000 0x00400000>; + }; + partition@1a00000 { + label = "user"; + reg = <0x01a00000 0x02560000>; + }; + partition@3f60000 { + label = "env"; + reg = <0x03f60000 0x00040000>; + }; + partition@3fa0000 { + label = "u-boot"; + reg = <0x03fa0000 0x00060000>; + }; + }; + + cpld@2,0 { + compatible = "amcc,ppc460ex-bcsr"; + reg = <2 0x0 0x9>; + }; + + ndfc@3,0 { + compatible = "ibm,ndfc"; + reg = <0x00000003 0x00000000 0x00002000>; + ccr = <0x00001000>; + bank-settings = <0x80002222>; + #address-cells = <1>; + #size-cells = <1>; + + nand { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x00100000>; + }; + partition@100000 { + label = "user"; + reg = <0x00000000 0x03f00000>; + }; + }; + }; + }; + + UART0: serial@ef600300 { + device_type = "serial"; + reg-shift = <0>; + compatible = "ns16550"; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC1>; + interrupts = <0x1 0x4>; + }; + + UART1: serial@ef600400 { + device_type = "serial"; + reg-shift = <0>; + compatible = "ns16550"; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC0>; + interrupts = <0x1 0x4>; + }; + + IIC0: i2c@ef600700 { + compatible = "ibm,iic-460ex", "ibm,iic"; + reg = <0xef600700 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x2 0x4>; + #address-cells = <1>; + #size-cells = <0>; + rtc@68 { + compatible = "stm,m41t80"; + reg = <0x68>; + interrupt-parent = <&UIC2>; + interrupts = <0x19 0x8>; + }; + sttm@48 { + compatible = "ad,ad7414"; + reg = <0x48>; + interrupt-parent = <&UIC1>; + interrupts = <0x14 0x8>; + }; + }; + + IIC1: i2c@ef600800 { + compatible = "ibm,iic-460ex", "ibm,iic"; + reg = <0xef600800 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x3 0x4>; + }; + + GPIO0: gpio@ef600b00 { + compatible = "ibm,ppc4xx-gpio"; + reg = <0xef600b00 0x00000048>; + gpio-controller; + }; + + ZMII0: emac-zmii@ef600d00 { + compatible = "ibm,zmii-460ex", "ibm,zmii"; + reg = <0xef600d00 0x0000000c>; + }; + + RGMII0: emac-rgmii@ef601500 { + compatible = "ibm,rgmii-460ex", "ibm,rgmii"; + reg = <0xef601500 0x00000008>; + has-mdio; + }; + + TAH0: emac-tah@ef601350 { + compatible = "ibm,tah-460ex", "ibm,tah"; + reg = <0xef601350 0x00000030>; + }; + + TAH1: emac-tah@ef601450 { + compatible = "ibm,tah-460ex", "ibm,tah"; + reg = <0xef601450 0x00000030>; + }; + + EMAC0: ethernet@ef600e00 { + device_type = "network"; + compatible = "ibm,emac-460ex", "ibm,emac4sync"; + interrupt-parent = <&EMAC0>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 + /*Wake*/ 0x1 &UIC2 0x14 0x4>; + reg = <0xef600e00 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <0>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + phy-mode = "rgmii"; + phy-map = <0x00000000>; + rgmii-device = <&RGMII0>; + rgmii-channel = <0>; + tah-device = <&TAH0>; + tah-channel = <0>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + }; + + EMAC1: ethernet@ef600f00 { + device_type = "network"; + compatible = "ibm,emac-460ex", "ibm,emac4sync"; + interrupt-parent = <&EMAC1>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 + /*Wake*/ 0x1 &UIC2 0x15 0x4>; + reg = <0xef600f00 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <1>; + mal-rx-channel = <8>; + cell-index = <1>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + phy-mode = "rgmii"; + phy-map = <0x00000000>; + rgmii-device = <&RGMII0>; + rgmii-channel = <1>; + tah-device = <&TAH1>; + tah-channel = <1>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + mdio-device = <&EMAC0>; + }; + }; + + PCIX0: pci@c0ec00000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix"; + primary; + large-inbound-windows; + enable-msi-hole; + reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ + 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ + 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 + 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 0 to 0x3f */ + bus-range = <0x0 0x3f>; + + /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; + }; + + PCIE0: pciex@d00000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; + primary; + port = <0x0>; /* port number */ + reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ + 0x0000000c 0x08010000 0x00001000>; /* Registers */ + dcr-reg = <0x100 0x020>; + sdr-base = <0x300>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 40 to 0x7f */ + bus-range = <0x40 0x7f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; + }; + + PCIE1: pciex@d20000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; + primary; + port = <0x1>; /* port number */ + reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ + 0x0000000c 0x08011000 0x00001000>; /* Registers */ + dcr-reg = <0x120 0x020>; + sdr-base = <0x340>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 80 to 0xbf */ + bus-range = <0x80 0xbf>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; + }; + + MSI: ppc4xx-msi@C10000000 { + compatible = "amcc,ppc4xx-msi", "ppc4xx-msi"; + reg = < 0xC 0x10000000 0x100>; + sdr-base = <0x36C>; + msi-data = <0x00000000>; + msi-mask = <0x44440000>; + interrupt-count = <3>; + interrupts = <0 1 2 3>; + interrupt-parent = <&UIC3>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &UIC3 0x18 1 + 1 &UIC3 0x19 1 + 2 &UIC3 0x1A 1 + 3 &UIC3 0x1B 1>; + }; + }; +}; diff --git a/arch/powerpc/dts/glacier.dts b/arch/powerpc/dts/glacier.dts new file mode 100644 index 0000000000..bb4e819e91 --- /dev/null +++ b/arch/powerpc/dts/glacier.dts @@ -0,0 +1,582 @@ +/* + * Device Tree Source for AMCC Glacier (460GT) + * + * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "amcc,glacier"; + compatible = "amcc,glacier"; + dcr-parent = <&{/cpus/cpu@0}>; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + ethernet2 = &EMAC2; + ethernet3 = &EMAC3; + serial0 = &UART0; + serial1 = &UART1; + }; + + chosen { + stdout-path = &UART0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,460GT"; + reg = <0x00000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + timebase-frequency = <0>; /* Filled in by U-Boot */ + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <32768>; + d-cache-size = <32768>; + dcr-controller; + dcr-access-method = "native"; + next-level-cache = <&L2C0>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ + }; + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0x0c0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0x0d0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC2: interrupt-controller2 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <2>; + dcr-reg = <0x0e0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC3: interrupt-controller3 { + compatible = "ibm,uic-460gt","ibm,uic"; + interrupt-controller; + cell-index = <3>; + dcr-reg = <0x0f0 0x009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + SDR0: sdr { + compatible = "ibm,sdr-460gt"; + dcr-reg = <0x00e 0x002>; + }; + + CPR0: cpr { + compatible = "ibm,cpr-460gt"; + dcr-reg = <0x00c 0x002>; + }; + + L2C0: l2c { + compatible = "ibm,l2-cache-460gt", "ibm,l2-cache"; + dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ + 0x030 0x008>; /* L2 cache DCR's */ + cache-line-size = <32>; /* 32 bytes */ + cache-size = <262144>; /* L2, 256K */ + interrupt-parent = <&UIC1>; + interrupts = <11 1>; + }; + + plb { + compatible = "ibm,plb-460gt", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by U-Boot */ + + SDRAM0: sdram { + compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; + dcr-reg = <0x010 0x002>; + }; + + CRYPTO: crypto@180000 { + compatible = "amcc,ppc460gt-crypto", "amcc,ppc460ex-crypto", + "amcc,ppc4xx-crypto"; + reg = <4 0x00180000 0x80400>; + interrupt-parent = <&UIC0>; + interrupts = <0x1d 0x4>; + }; + + HWRNG: hwrng@110000 { + compatible = "amcc,ppc460ex-rng", "ppc4xx-rng"; + reg = <4 0x00110000 0x50>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; + dcr-reg = <0x180 0x062>; + num-tx-chans = <4>; + num-rx-chans = <32>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-parent = <&UIC2>; + interrupts = < /*TXEOB*/ 0x6 0x4 + /*RXEOB*/ 0x7 0x4 + /*SERR*/ 0x3 0x4 + /*TXDE*/ 0x4 0x4 + /*RXDE*/ 0x5 0x4>; + desc-base-addr-high = <0x8>; + }; + + POB0: opb { + compatible = "ibm,opb-460gt", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; + clock-frequency = <0>; /* Filled in by U-Boot */ + + EBC0: ebc { + compatible = "ibm,ebc-460gt", "ibm,ebc"; + dcr-reg = <0x012 0x002>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by U-Boot */ + /* ranges property is supplied by U-Boot */ + interrupts = <0x6 0x4>; + interrupt-parent = <&UIC1>; + + nor_flash@0,0 { + compatible = "amd,s29gl512n", "cfi-flash"; + bank-width = <2>; + reg = <0x00000000 0x00000000 0x04000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0x00000000 0x001e0000>; + }; + partition@1e0000 { + label = "dtb"; + reg = <0x001e0000 0x00020000>; + }; + partition@200000 { + label = "ramdisk"; + reg = <0x00200000 0x01400000>; + }; + partition@1600000 { + label = "jffs2"; + reg = <0x01600000 0x00400000>; + }; + partition@1a00000 { + label = "user"; + reg = <0x01a00000 0x02560000>; + }; + partition@3f60000 { + label = "env"; + reg = <0x03f60000 0x00040000>; + }; + partition@3fa0000 { + label = "u-boot"; + reg = <0x03fa0000 0x00060000>; + }; + }; + + ndfc@3,0 { + compatible = "ibm,ndfc"; + reg = <0x00000003 0x00000000 0x00002000>; + ccr = <0x00001000>; + bank-settings = <0x80002222>; + #address-cells = <1>; + #size-cells = <1>; + + nand { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x00100000>; + }; + partition@100000 { + label = "user"; + reg = <0x00000000 0x03f00000>; + }; + }; + }; + }; + + UART0: serial@ef600300 { + device_type = "serial"; + reg-shift = <0>; + compatible = "ns16550"; + reg = <0xef600300 0x00000008>; + virtual-reg = <0xef600300>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC1>; + interrupts = <0x1 0x4>; + }; + + UART1: serial@ef600400 { + device_type = "serial"; + reg-shift = <0>; + compatible = "ns16550"; + reg = <0xef600400 0x00000008>; + virtual-reg = <0xef600400>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC0>; + interrupts = <0x1 0x4>; + }; + + UART2: serial@ef600500 { + device_type = "serial"; + reg-shift = <0>; + compatible = "ns16550"; + reg = <0xef600500 0x00000008>; + virtual-reg = <0xef600500>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC1>; + interrupts = <28 0x4>; + }; + + UART3: serial@ef600600 { + device_type = "serial"; + reg-shift = <0>; + compatible = "ns16550"; + reg = <0xef600600 0x00000008>; + virtual-reg = <0xef600600>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; /* Filled in by U-Boot */ + interrupt-parent = <&UIC1>; + interrupts = <29 0x4>; + }; + + IIC0: i2c@ef600700 { + compatible = "ibm,iic-460gt", "ibm,iic"; + reg = <0xef600700 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x2 0x4>; + #address-cells = <1>; + #size-cells = <0>; + rtc@68 { + compatible = "stm,m41t80"; + reg = <0x68>; + interrupt-parent = <&UIC2>; + interrupts = <0x19 0x8>; + }; + sttm@48 { + compatible = "ad,ad7414"; + reg = <0x48>; + interrupt-parent = <&UIC1>; + interrupts = <0x14 0x8>; + }; + }; + + IIC1: i2c@ef600800 { + compatible = "ibm,iic-460gt", "ibm,iic"; + reg = <0xef600800 0x00000014>; + interrupt-parent = <&UIC0>; + interrupts = <0x3 0x4>; + }; + + ZMII0: emac-zmii@ef600d00 { + compatible = "ibm,zmii-460gt", "ibm,zmii"; + reg = <0xef600d00 0x0000000c>; + }; + + RGMII0: emac-rgmii@ef601500 { + compatible = "ibm,rgmii-460gt", "ibm,rgmii"; + reg = <0xef601500 0x00000008>; + has-mdio; + }; + + RGMII1: emac-rgmii@ef601600 { + compatible = "ibm,rgmii-460gt", "ibm,rgmii"; + reg = <0xef601600 0x00000008>; + has-mdio; + }; + + TAH0: emac-tah@ef601350 { + compatible = "ibm,tah-460gt", "ibm,tah"; + reg = <0xef601350 0x00000030>; + }; + + TAH1: emac-tah@ef601450 { + compatible = "ibm,tah-460gt", "ibm,tah"; + reg = <0xef601450 0x00000030>; + }; + + EMAC0: ethernet@ef600e00 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC0>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 + /*Wake*/ 0x1 &UIC2 0x14 0x4>; + reg = <0xef600e00 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <0>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + phy-mode = "rgmii"; + phy-map = <0x00000000>; + rgmii-device = <&RGMII0>; + rgmii-channel = <0>; + tah-device = <&TAH0>; + tah-channel = <0>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + }; + + EMAC1: ethernet@ef600f00 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC1>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 + /*Wake*/ 0x1 &UIC2 0x15 0x4>; + reg = <0xef600f00 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <1>; + mal-rx-channel = <8>; + cell-index = <1>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + phy-mode = "rgmii"; + phy-map = <0x00000000>; + rgmii-device = <&RGMII0>; + rgmii-channel = <1>; + tah-device = <&TAH1>; + tah-channel = <1>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + mdio-device = <&EMAC0>; + }; + + EMAC2: ethernet@ef601100 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC2>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 + /*Wake*/ 0x1 &UIC2 0x16 0x4>; + reg = <0xef601100 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <2>; + mal-rx-channel = <16>; + cell-index = <2>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + tx-fifo-size-gige = <16384>; /* emac2&3 only */ + phy-mode = "rgmii"; + phy-map = <0x00000000>; + rgmii-device = <&RGMII1>; + rgmii-channel = <0>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + mdio-device = <&EMAC0>; + }; + + EMAC3: ethernet@ef601200 { + device_type = "network"; + compatible = "ibm,emac-460gt", "ibm,emac4sync"; + interrupt-parent = <&EMAC3>; + interrupts = <0x0 0x1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4 + /*Wake*/ 0x1 &UIC2 0x17 0x4>; + reg = <0xef601200 0x000000c4>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <3>; + mal-rx-channel = <24>; + cell-index = <3>; + max-frame-size = <9000>; + rx-fifo-size = <4096>; + tx-fifo-size = <2048>; + rx-fifo-size-gige = <16384>; + tx-fifo-size-gige = <16384>; /* emac2&3 only */ + phy-mode = "rgmii"; + phy-map = <0x00000000>; + rgmii-device = <&RGMII1>; + rgmii-channel = <1>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + mdio-device = <&EMAC0>; + }; + }; + + PCIX0: pci@c0ec00000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix"; + primary; + large-inbound-windows; + enable-msi-hole; + reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ + 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ + 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ + 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ + 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 + 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 0 to 0x3f */ + bus-range = <0x0 0x3f>; + + /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; + }; + + PCIE0: pciex@d00000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; + primary; + port = <0x0>; /* port number */ + reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ + 0x0000000c 0x08010000 0x00001000>; /* Registers */ + dcr-reg = <0x100 0x020>; + sdr-base = <0x300>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 40 to 0x7f */ + bus-range = <0x40 0x7f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; + }; + + PCIE1: pciex@d20000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; + primary; + port = <0x1>; /* port number */ + reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ + 0x0000000c 0x08011000 0x00001000>; /* Registers */ + dcr-reg = <0x120 0x020>; + sdr-base = <0x340>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 + 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; + + /* This drives busses 80 to 0xbf */ + bus-range = <0x80 0xbf>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = < + 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ + 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ + 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ + 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; + }; + }; +}; diff --git a/arch/powerpc/include/asm/arch-ppc4xx/gpio.h b/arch/powerpc/include/asm/arch-ppc4xx/gpio.h new file mode 100644 index 0000000000..3d960c3f1f --- /dev/null +++ b/arch/powerpc/include/asm/arch-ppc4xx/gpio.h @@ -0,0 +1,7 @@ +/* + * (C) Copyright 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* This is empty for now as we don't support the generic GPIO interface */ diff --git a/arch/powerpc/include/asm/linkage.h b/arch/powerpc/include/asm/linkage.h new file mode 100644 index 0000000000..559b42ed3b --- /dev/null +++ b/arch/powerpc/include/asm/linkage.h @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* We don't need anything here at present */ diff --git a/arch/powerpc/include/asm/ppc460ex_gt.h b/arch/powerpc/include/asm/ppc460ex_gt.h index f41df0da6a..ea019aafdb 100644 --- a/arch/powerpc/include/asm/ppc460ex_gt.h +++ b/arch/powerpc/include/asm/ppc460ex_gt.h @@ -19,10 +19,12 @@ /* Memory mapped registers */ #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ +#ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600) +#endif #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00) #define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00) diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 0f6298269a..05b22bb5f7 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -40,6 +40,7 @@ obj-y += extable.o obj-y += interrupts.o obj-$(CONFIG_CMD_KGDB) += kgdb.o obj-$(CONFIG_CMD_IDE) += ide.o +obj-y += stack.o obj-y += time.o # Don't include the MPC5xxx special memcpy into the diff --git a/arch/powerpc/lib/stack.c b/arch/powerpc/lib/stack.c new file mode 100644 index 0000000000..1985f0348d --- /dev/null +++ b/arch/powerpc/lib/stack.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015 Andreas Bießmann <andreas.devel@googlemail.com> + * + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2002-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int arch_reserve_stacks(void) +{ + ulong *s; + + /* setup stack pointer for exceptions */ + gd->irq_sp = gd->start_addr_sp; + + /* Clear initial stack frame */ + s = (ulong *)gd->start_addr_sp; + *s = 0; /* Terminate back chain */ + *++s = 0; /* NULL return address */ + + return 0; +} diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 3057325b47..2098b9c323 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -10,4 +10,28 @@ config SYS_BOARD config SYS_CONFIG_NAME default "sandbox" +config DM + default y + +config DM_GPIO + default y + +config DM_SERIAL + default y + +config DM_CROS_EC + default y + +config DM_SPI + default y + +config DM_SPI_FLASH + default y + +config DM_I2C + default y + +config DM_TEST + default y + endmenu diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index e38a44bd11..7b84f02a0a 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -5,10 +5,16 @@ PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM -DCONFIG_SYS_GENERIC_BOARD PLATFORM_LIBS += -lrt +# Define this to avoid linking with SDL, which requires SDL libraries +# This can solve 'sdl-config: Command not found' errors +ifneq ($(NO_SDL),) +PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL +else ifdef CONFIG_SANDBOX_SDL PLATFORM_LIBS += $(shell sdl-config --libs) PLATFORM_CPPFLAGS += $(shell sdl-config --cflags) endif +endif # Support generic board on sandbox __HAVE_ARCH_GENERIC_BOARD := y @@ -18,9 +24,3 @@ cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map CONFIG_ARCH_DEVICE_TREE := sandbox - -# Define this to avoid linking with SDL, which requires SDL libraries -# This can solve 'sdl-config: Command not found' errors -ifneq ($(NO_SDL),) -PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL -endif diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 097f29a290..ec010402d7 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -78,11 +78,13 @@ int sandbox_main_loop_init(void) /* Execute command if required */ if (state->cmd) { + int retval; + cli_init(); - run_command_list(state->cmd, -1, 0); + retval = run_command_list(state->cmd, -1, 0); if (!state->interactive) - os_exit(state->exit_type); + os_exit(retval); } return 0; diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index ba73b7e251..033958ce74 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -13,11 +13,6 @@ static struct sandbox_state main_state; static struct sandbox_state *state; /* Pointer to current state record */ -void state_record_exit(enum exit_type_id exit_type) -{ - state->exit_type = exit_type; -} - static int state_ensure_space(int extra_size) { void *blob = state->state_fdt; diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 32d55ccc4c..a0c24ba1e0 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -10,13 +10,6 @@ #include <stdbool.h> #include <linux/stringify.h> -/* How we exited U-Boot */ -enum exit_type_id { - STATE_EXIT_NORMAL, - STATE_EXIT_COLD_REBOOT, - STATE_EXIT_POWER_OFF, -}; - /** * Selects the behavior of the serial terminal. * @@ -50,7 +43,6 @@ struct sandbox_state { const char *cmd; /* Command to execute */ bool interactive; /* Enable cmdline after execute */ const char *fdt_fname; /* Filename of FDT binary */ - enum exit_type_id exit_type; /* How we exited U-Boot */ const char *parse_err; /* Error to report from parsing */ int argc; /* Program arguments */ char **argv; /* Command line arguments */ @@ -139,13 +131,6 @@ struct sandbox_state_io { } /** - * Record the exit type to be reported by the test program. - * - * @param exit_type Exit type to record - */ -void state_record_exit(enum exit_type_id exit_type); - -/** * Gets a pointer to the current state. * * @return pointer to state diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fef11f3552..35d24e4aca 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -67,6 +67,21 @@ config TARGET_GALILEO endchoice +config DM + default y + +config DM_GPIO + default y + +config DM_SERIAL + default y + +config SYS_MALLOC_F + default y + +config SYS_MALLOC_F_LEN + default 0x800 + config RAMBASE hex default 0x100000 |