diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/cpu/arm1136/start.S | 1 | ||||
-rw-r--r-- | arch/arm/cpu/arm1176/start.S | 1 | ||||
-rw-r--r-- | arch/arm/cpu/arm720t/start.S | 1 | ||||
-rw-r--r-- | arch/arm/cpu/arm920t/start.S | 1 | ||||
-rw-r--r-- | arch/arm/cpu/arm925t/start.S | 1 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/orion5x/cpu.c | 8 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S | 140 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/start.S | 2 | ||||
-rw-r--r-- | arch/arm/cpu/arm946es/start.S | 1 | ||||
-rw-r--r-- | arch/arm/cpu/arm_cortexa8/omap3/cache.S | 8 | ||||
-rw-r--r-- | arch/arm/cpu/arm_cortexa8/start.S | 2 | ||||
-rw-r--r-- | arch/arm/cpu/arm_intcm/start.S | 1 | ||||
-rw-r--r-- | arch/arm/cpu/ixp/start.S | 1 | ||||
-rw-r--r-- | arch/arm/cpu/lh7a40x/start.S | 1 | ||||
-rw-r--r-- | arch/arm/cpu/pxa/start.S | 6 | ||||
-rw-r--r-- | arch/arm/cpu/s3c44b0/start.S | 1 | ||||
-rw-r--r-- | arch/arm/cpu/sa1100/start.S | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/io.h | 14 | ||||
-rw-r--r-- | arch/arm/lib/bootm.c | 43 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc5xxx/Makefile | 5 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c | 71 | ||||
-rw-r--r-- | arch/powerpc/lib/Makefile | 5 |
22 files changed, 184 insertions, 131 deletions
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 922d01cb70..41eb82dae2 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -185,6 +185,7 @@ stack_setup: #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ #endif /* CONFIG_PRELOADER */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index a540edbfbf..f98a7aa355 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -276,6 +276,7 @@ stack_setup: sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 022b873e35..d6f2c165c7 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -172,6 +172,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 779f192e51..e532f55bfc 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -204,6 +204,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 567e80479e..346615e4b4 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -196,6 +196,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index c2f5253b05..03c6d0677c 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -260,10 +260,10 @@ int arch_misc_init(void) /* Set CPIOs and MPPs - values provided by board include file */ - writel(ORION5X_MPP_BASE+0x00, ORION5X_MPP0_7); - writel(ORION5X_MPP_BASE+0x04, ORION5X_MPP8_15); - writel(ORION5X_MPP_BASE+0x50, ORION5X_MPP16_23); - writel(ORION5X_GPIO_BASE+0x04, ORION5X_GPIO_OUT_ENABLE); + writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00); + writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04); + writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50); + writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04); return 0; } diff --git a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S index b0e15f6e23..0523bd468a 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S @@ -87,30 +87,30 @@ lowlevel_init: /* Use 'r4 as the base for internal register accesses */ - ldr r4, =ORION5X_REGS_PHY_BASE + ldr r4, =ORION5X_REGS_PHY_BASE /* move internal registers from the default 0xD0000000 * to their intended location, defined by SoC */ ldr r3, =0xD0000000 add r3, r3, #0x20000 - str r4, [r3, #0x80] + str r4, [r3, #0x80] /* Use R3 as the base for DRAM registers */ - add r3, r4, #0x01000 + add r3, r4, #0x01000 /*DDR SDRAM Initialization Control */ ldr r6, =0x00000001 str r6, [r3, #0x480] /* Use R3 as the base for PCI registers */ - add r3, r4, #0x31000 + add r3, r4, #0x31000 /* Disable arbiter */ ldr r6, =0x00000030 str r6, [r3, #0xd00] /* Use R3 as the base for DRAM registers */ - add r3, r4, #0x01000 + add r3, r4, #0x01000 /* set all dram windows to 0 */ mov r6, #0 @@ -127,63 +127,63 @@ lowlevel_init: ldr r6, =SDRAM_CONTROL str r6, [r3, #0x404] - /* 3) Write SDRAM address control register */ + /* 3) Write SDRAM address control register */ ldr r6, =SDRAM_ADDR_CTRL str r6, [r3, #0x410] - /* 4) Write SDRAM bank 0 size register */ + /* 4) Write SDRAM bank 0 size register */ ldr r6, =SDRAM_BANK0_SIZE str r6, [r3, #0x504] /* keep other banks disabled */ - /* 5) Write SDRAM open pages control register */ + /* 5) Write SDRAM open pages control register */ ldr r6, =SDRAM_OPEN_PAGE_EN str r6, [r3, #0x414] - /* 6) Write SDRAM timing Low register */ + /* 6) Write SDRAM timing Low register */ ldr r6, =SDRAM_TIME_CTRL_LOW str r6, [r3, #0x408] - /* 7) Write SDRAM timing High register */ + /* 7) Write SDRAM timing High register */ ldr r6, =SDRAM_TIME_CTRL_HI str r6, [r3, #0x40C] - /* 8) Write SDRAM mode register */ - /* The CPU must not attempt to change the SDRAM Mode register setting */ - /* prior to DRAM controller completion of the DRAM initialization */ - /* sequence. To guarantee this restriction, it is recommended that */ - /* the CPU sets the SDRAM Operation register to NOP command, performs */ - /* read polling until the register is back in Normal operation value, */ - /* and then sets SDRAM Mode register to its new value. */ + /* 8) Write SDRAM mode register */ + /* The CPU must not attempt to change the SDRAM Mode register setting */ + /* prior to DRAM controller completion of the DRAM initialization */ + /* sequence. To guarantee this restriction, it is recommended that */ + /* the CPU sets the SDRAM Operation register to NOP command, performs */ + /* read polling until the register is back in Normal operation value, */ + /* and then sets SDRAM Mode register to its new value. */ /* 8.1 write 'nop' to SDRAM operation */ - ldr r6, =SDRAM_OP_NOP + ldr r6, =SDRAM_OP_NOP str r6, [r3, #0x418] - /* 8.2 poll SDRAM operation until back in 'normal' mode. */ + /* 8.2 poll SDRAM operation until back in 'normal' mode. */ 1: ldr r6, [r3, #0x418] cmp r6, #0 bne 1b - /* 8.3 Now its safe to write new value to SDRAM Mode register */ + /* 8.3 Now its safe to write new value to SDRAM Mode register */ ldr r6, =SDRAM_MODE str r6, [r3, #0x41C] - /* 8.4 Set new mode */ - ldr r6, =SDRAM_OP_SETMODE + /* 8.4 Set new mode */ + ldr r6, =SDRAM_OP_SETMODE str r6, [r3, #0x418] - /* 8.5 poll SDRAM operation until back in 'normal' mode. */ + /* 8.5 poll SDRAM operation until back in 'normal' mode. */ 2: ldr r6, [r3, #0x418] cmp r6, #0 bne 2b - /* DDR SDRAM Address/Control Pads Calibration */ + /* DDR SDRAM Address/Control Pads Calibration */ ldr r6, [r3, #0x4C0] - /* Set Bit [31] to make the register writable */ + /* Set Bit [31] to make the register writable */ orr r6, r6, #SDRAM_PAD_CTRL_WR_EN str r6, [r3, #0x4C0] @@ -192,20 +192,20 @@ lowlevel_init: bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK - /* Get the final N locked value of driving strength [22:17] */ - mov r1, r6 - mov r1, r1, LSL #9 - mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */ - orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */ + /* Get the final N locked value of driving strength [22:17] */ + mov r1, r6 + mov r1, r1, LSL #9 + mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */ + orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */ - /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ + /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ orr r6, r6, r1 str r6, [r3, #0x4C0] - /* DDR SDRAM Data Pads Calibration */ + /* DDR SDRAM Data Pads Calibration */ ldr r6, [r3, #0x4C4] - /* Set Bit [31] to make the register writable */ + /* Set Bit [31] to make the register writable */ orr r6, r6, #SDRAM_PAD_CTRL_WR_EN str r6, [r3, #0x4C4] @@ -214,21 +214,21 @@ lowlevel_init: bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK - /* Get the final N locked value of driving strength [22:17] */ - mov r1, r6 - mov r1, r1, LSL #9 - mov r1, r1, LSR #26 - orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */ + /* Get the final N locked value of driving strength [22:17] */ + mov r1, r6 + mov r1, r1, LSL #9 + mov r1, r1, LSR #26 + orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */ - /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ + /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */ orr r6, r6, r1 str r6, [r3, #0x4C4] - /* Implement Guideline (GL# MEM-3) Drive Strength Value */ - /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + /* Implement Guideline (GL# MEM-3) Drive Strength Value */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ - ldr r1, =DDR1_PAD_STRENGTH_DEFAULT + ldr r1, =DDR1_PAD_STRENGTH_DEFAULT /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */ ldr r6, [r3, #0x4C0] @@ -252,42 +252,42 @@ lowlevel_init: orr r6, r6, r1 str r6, [r3, #0x4C4] - /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ - /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ - /* Get the "sample on reset" register for the DDR frequancy */ + /* Get the "sample on reset" register for the DDR frequancy */ ldr r3, =0x10000 - ldr r6, [r3, #0x010] - ldr r1, =MSAR_ARMDDRCLCK_MASK - and r1, r6, r1 - - ldr r6, =FTDLL_DDR1_166MHZ - cmp r1, #MSAR_ARMDDRCLCK_333_167 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_500_167 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_667_167 - beq 3f - - ldr r6, =FTDLL_DDR1_200MHZ - cmp r1, #MSAR_ARMDDRCLCK_400_200_1 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_400_200 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_600_200 - beq 3f - cmp r1, #MSAR_ARMDDRCLCK_800_200 - beq 3f - - ldr r6, =0 + ldr r6, [r3, #0x010] + ldr r1, =MSAR_ARMDDRCLCK_MASK + and r1, r6, r1 + + ldr r6, =FTDLL_DDR1_166MHZ + cmp r1, #MSAR_ARMDDRCLCK_333_167 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_500_167 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_667_167 + beq 3f + + ldr r6, =FTDLL_DDR1_200MHZ + cmp r1, #MSAR_ARMDDRCLCK_400_200_1 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_400_200 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_600_200 + beq 3f + cmp r1, #MSAR_ARMDDRCLCK_800_200 + beq 3f + + ldr r6, =0 3: /* Use R3 as the base for DRAM registers */ - add r3, r4, #0x01000 + add r3, r4, #0x01000 ldr r2, [r3, #0x484] orr r2, r2, r6 str r2, [r3, #0x484] /* Return to U-boot via saved link register */ - mov pc, lr + mov pc, lr diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 3b81151f49..cf40ce1292 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -196,7 +196,7 @@ stack_setup: #endif #endif /* CONFIG_PRELOADER */ sub sp, r0, #12 /* leave 3 words for abort-stack */ - bic sp, r0, #7 /* 8-byte align stack for ABI compliance */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 627e3cb94d..8844d4438b 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -163,6 +163,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/arm_cortexa8/omap3/cache.S b/arch/arm/cpu/arm_cortexa8/omap3/cache.S index 0f63815359..4b65ac58a5 100644 --- a/arch/arm/cpu/arm_cortexa8/omap3/cache.S +++ b/arch/arm/cpu/arm_cortexa8/omap3/cache.S @@ -130,7 +130,7 @@ finished_inval: l2_cache_enable: - push {r0, r1, r2, lr} + stmfd r13!, {r0, r1, r2, lr} @ ES2 onwards we can disable/enable L2 ourselves bl get_cpu_rev cmp r0, #CPU_3XX_ES20 @@ -157,11 +157,11 @@ l2_cache_enable_EARLIER_THAN_ES2: mov ip, r3 str r3, [sp, #4] l2_cache_enable_END: - pop {r1, r2, r3, pc} + ldmfd r13!, {r1, r2, r3, pc} l2_cache_disable: - push {r0, r1, r2, lr} + stmfd r13!, {r0, r1, r2, lr} @ ES2 onwards we can disable/enable L2 ourselves bl get_cpu_rev cmp r0, #CPU_3XX_ES20 @@ -188,4 +188,4 @@ l2_cache_disable_EARLIER_THAN_ES2: mov ip, r3 str r3, [sp, #4] l2_cache_disable_END: - pop {r1, r2, r3, pc} + ldmfd r13!, {r1, r2, r3, pc} diff --git a/arch/arm/cpu/arm_cortexa8/start.S b/arch/arm/cpu/arm_cortexa8/start.S index 29dae2f282..1e0a1504bf 100644 --- a/arch/arm/cpu/arm_cortexa8/start.S +++ b/arch/arm/cpu/arm_cortexa8/start.S @@ -164,7 +164,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 @ leave 3 words for abort-stack - and sp, sp, #~7 @ 8 byte alinged for (ldr/str)d + bic sp, sp, #7 @ 8-byte alignment for ABI compliance /* Clear BSS (if any). Is below tx (watch load addr - need space) */ clear_bss: diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index bb1f003592..328bae0274 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -161,6 +161,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index 5ebce5338c..6efe333f1a 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -289,6 +289,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S index a1321b1d74..14a1fbe121 100644 --- a/arch/arm/cpu/lh7a40x/start.S +++ b/arch/arm/cpu/lh7a40x/start.S @@ -178,6 +178,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 3989fa61bc..e07c8c2e0e 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -140,10 +140,8 @@ stack_setup: #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif /* CONFIG_USE_IRQ */ - sub r0, r0, #12 /* leave 3 words for abort-stack */ - bic sp, r0, #7 /* NOTE: stack MUST be aligned to */ - /* 8 bytes in case we want to use */ - /* 64bit datatypes (eg. VSPRINTF64) */ + sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index f5a3d3ac38..0063063f45 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -163,6 +163,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ ldr pc, _start_armboot diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 278c5008fb..deb4745e21 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -153,6 +153,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 0a4b5be715..e8f3eb13aa 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -248,13 +248,13 @@ extern void __iounmap(void *addr); * iomem_to_phys(off) */ #ifdef iomem_valid_addr -#define __arch_ioremap(off,sz,nocache) \ - ({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off),_size,0); \ - _ret; \ +#define __arch_ioremap(off,sz,nocache) \ + ({ \ + unsigned long _off = (off), _size = (sz); \ + void *_ret = (void *)0; \ + if (iomem_valid_addr(_off, _size)) \ + _ret = __ioremap(iomem_to_phys(_off),_size,nocache); \ + _ret; \ }) #define __arch_iounmap __iounmap diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 128b7e313c..5ac1302aa6 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -33,9 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; defined (CONFIG_CMDLINE_TAG) || \ defined (CONFIG_INITRD_TAG) || \ defined (CONFIG_SERIAL_TAG) || \ - defined (CONFIG_REVISION_TAG) || \ - defined (CONFIG_VFD) || \ - defined (CONFIG_LCD) + defined (CONFIG_REVISION_TAG) static void setup_start_tag (bd_t *bd); # ifdef CONFIG_SETUP_MEMORY_TAGS @@ -49,10 +47,6 @@ static void setup_initrd_tag (bd_t *bd, ulong initrd_start, # endif static void setup_end_tag (bd_t *bd); -# if defined (CONFIG_VFD) || defined (CONFIG_LCD) -static void setup_videolfb_tag (gd_t *gd); -# endif - static struct tag *params; #endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ @@ -87,9 +81,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) defined (CONFIG_CMDLINE_TAG) || \ defined (CONFIG_INITRD_TAG) || \ defined (CONFIG_SERIAL_TAG) || \ - defined (CONFIG_REVISION_TAG) || \ - defined (CONFIG_LCD) || \ - defined (CONFIG_VFD) + defined (CONFIG_REVISION_TAG) setup_start_tag (bd); #ifdef CONFIG_SERIAL_TAG setup_serial_tag (¶ms); @@ -107,9 +99,6 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) if (images->rd_start && images->rd_end) setup_initrd_tag (bd, images->rd_start, images->rd_end); #endif -#if defined (CONFIG_VFD) || defined (CONFIG_LCD) - setup_videolfb_tag ((gd_t *) gd); -#endif setup_end_tag (bd); #endif @@ -136,9 +125,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) defined (CONFIG_CMDLINE_TAG) || \ defined (CONFIG_INITRD_TAG) || \ defined (CONFIG_SERIAL_TAG) || \ - defined (CONFIG_REVISION_TAG) || \ - defined (CONFIG_LCD) || \ - defined (CONFIG_VFD) + defined (CONFIG_REVISION_TAG) static void setup_start_tag (bd_t *bd) { params = (struct tag *) bd->bi_boot_params; @@ -214,30 +201,6 @@ static void setup_initrd_tag (bd_t *bd, ulong initrd_start, ulong initrd_end) } #endif /* CONFIG_INITRD_TAG */ - -#if defined (CONFIG_VFD) || defined (CONFIG_LCD) -extern ulong calc_fbsize (void); -static void setup_videolfb_tag (gd_t *gd) -{ - /* An ATAG_VIDEOLFB node tells the kernel where and how large - * the framebuffer for video was allocated (among other things). - * Note that a _physical_ address is passed ! - * - * We only use it to pass the address and size, the other entries - * in the tag_videolfb are not of interest. - */ - params->hdr.tag = ATAG_VIDEOLFB; - params->hdr.size = tag_size (tag_videolfb); - - params->u.videolfb.lfb_base = (u32) gd->fb_base; - /* Fb size is calculated according to parameters for our panel - */ - params->u.videolfb.lfb_size = calc_fbsize(); - - params = tag_next (params); -} -#endif /* CONFIG_VFD || CONFIG_LCD */ - #ifdef CONFIG_SERIAL_TAG void setup_serial_tag (struct tag **tmp) { diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile b/arch/powerpc/cpu/mpc5xxx/Makefile index 0ee0611550..4ab2b7be76 100644 --- a/arch/powerpc/cpu/mpc5xxx/Makefile +++ b/arch/powerpc/cpu/mpc5xxx/Makefile @@ -30,6 +30,11 @@ SOBJS = io.o firmware_sc_task_bestcomm.impl.o COBJS = i2c.o traps.o cpu.o cpu_init.o ide.o interrupts.o \ loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o +# Workaround for local bus unaligned access problem on MPC5200 +#ifdef CONFIG_MPC5200 +COBJS += memcpy_mpc5200.o +#endif + SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) START := $(addprefix $(obj),$(START)) diff --git a/arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c b/arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c new file mode 100644 index 0000000000..09503548aa --- /dev/null +++ b/arch/powerpc/cpu/mpc5xxx/memcpy_mpc5200.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This is a workaround for issues on the MPC5200, where unaligned + * 32-bit-accesses to the local bus will deliver corrupted data. This + * happens for example when trying to use memcpy() from an odd NOR + * flash address; the behaviour can be also seen when using "md" on an + * odd NOR flash address (but there it is not a bug in U-Boot, which + * only shows the behaviour of this processor). + * + * For memcpy(), we test if either the source or the target address + * are not 32 bit aligned, and - if so - if the source address is in + * NOR flash: in this case we perform a byte-wise (slow) then; for + * aligned operations of non-flash areas we use the optimized (fast) + * real __memcpy(). This way we minimize the performance impact of + * this workaround. + * + */ + +#include <common.h> +#include <flash.h> +#include <linux/types.h> + +void *memcpy(void *trg, const void *src, size_t len) +{ + extern void* __memcpy(void *, const void *, size_t); + char *s = (char *)src; + char *t = (char *)trg; + void *dest = (void *)src; + + /* + * Check is source address is in flash: + * If not, we use the fast assembler code + */ + if (((((unsigned long)s & 3) == 0) /* source aligned */ + && /* AND */ + (((unsigned long)t & 3) == 0)) /* target aligned, */ + || /* or */ + (addr2info((ulong)s) == NULL)) { /* source not in flash */ + return __memcpy(trg, src, len); + } + + /* + * Copying from flash, perform byte by byte copy. + */ + while (len-- > 0) + *t++ = *s++; + + return dest; +} diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 5f85502d1c..bf23790c42 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -43,6 +43,11 @@ COBJS-y += time.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +# Workaround for local bus unaligned access problem on MPC5200 +ifdef CONFIG_MPC5200 +$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy +endif + $(LIB): $(obj).depend $(OBJS) @if ! $(CROSS_COMPILE)readelf -S $(OBJS) | grep -q '\.fixup.*PROGBITS';\ then \ |