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-rw-r--r--board/amcc/acadia/acadia.c12
-rw-r--r--board/amcc/bamboo/bamboo.c30
-rw-r--r--board/amcc/bubinga/bubinga.c12
-rw-r--r--board/amcc/canyonlands/canyonlands.c62
-rw-r--r--board/amcc/ebony/ebony.c28
-rw-r--r--board/amcc/katmai/katmai.c72
-rw-r--r--board/amcc/kilauea/kilauea.c52
-rw-r--r--board/amcc/luan/luan.c34
-rw-r--r--board/amcc/makalu/makalu.c48
-rw-r--r--board/amcc/ocotea/ocotea.c60
-rw-r--r--board/amcc/redwood/redwood.c60
-rw-r--r--board/amcc/sequoia/sequoia.c46
-rw-r--r--board/amcc/taihu/taihu.c14
-rw-r--r--board/amcc/taishan/taishan.c60
-rw-r--r--board/amcc/walnut/walnut.c14
-rw-r--r--board/amcc/yosemite/yosemite.c30
-rw-r--r--board/amcc/yucca/yucca.c64
17 files changed, 349 insertions, 349 deletions
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
index 0db619952e..482561122a 100644
--- a/board/amcc/acadia/acadia.c
+++ b/board/amcc/acadia/acadia.c
@@ -78,12 +78,12 @@ int board_early_init_f(void)
mfsdr(SDR0_ULTRA1, reg);
mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000010);
- mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */
- mtdcr(uictr, 0x00000010); /* set int trigger levels */
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000010);
+ mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */
+ mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 2ffd720d5c..38186a5d37 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -392,21 +392,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
- mtdcr(uic0sr, 0xffffffff); /* clear all */
- mtdcr(uic0er, 0x00000000); /* disable all */
- mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
- mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
- mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic0sr, 0xffffffff); /* clear all */
-
- mtdcr(uic1sr, 0xffffffff); /* clear all */
- mtdcr(uic1er, 0x00000000); /* disable all */
- mtdcr(uic1cr, 0x00000000); /* all non-critical */
- mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
- mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup the GPIO pins
diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c
index d0aebec2cd..49eadb9212 100644
--- a/board/amcc/bubinga/bubinga.c
+++ b/board/amcc/bubinga/bubinga.c
@@ -29,12 +29,12 @@ long int spd_sdram(void);
int board_early_init_f(void)
{
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000010);
- mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */
- mtdcr(uictr, 0x00000010); /* set int trigger levels */
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000010);
+ mtdcr(UIC0PR, 0xFFFF7FF0); /* set int polarities */
+ mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* Configure CPC0_PCI to enable PerWE as output
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 3a03f30731..f359d2377a 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -116,37 +116,37 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
- mtdcr(uic0sr, 0xffffffff); /* clear all */
- mtdcr(uic0er, 0x00000000); /* disable all */
- mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
- mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
- mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic0sr, 0xffffffff); /* clear all */
-
- mtdcr(uic1sr, 0xffffffff); /* clear all */
- mtdcr(uic1er, 0x00000000); /* disable all */
- mtdcr(uic1cr, 0x00000000); /* all non-critical */
- mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
- mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
- mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic1sr, 0xffffffff); /* clear all */
-
- mtdcr(uic2sr, 0xffffffff); /* clear all */
- mtdcr(uic2er, 0x00000000); /* disable all */
- mtdcr(uic2cr, 0x00000000); /* all non-critical */
- mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
- mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
- mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic2sr, 0xffffffff); /* clear all */
-
- mtdcr(uic3sr, 0xffffffff); /* clear all */
- mtdcr(uic3er, 0x00000000); /* disable all */
- mtdcr(uic3cr, 0x00000000); /* all non-critical */
- mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
- mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
- mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic3sr, 0xffffffff); /* clear all */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC3SR, 0xffffffff); /* clear all */
+ mtdcr(UIC3ER, 0x00000000); /* disable all */
+ mtdcr(UIC3CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC3SR, 0xffffffff); /* clear all */
#if !defined(CONFIG_ARCHES)
/* SDR Setting - enable NDFC */
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index 2439b03a9f..0543bad138 100644
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -71,21 +71,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
- mtdcr(uic0sr, 0xffffffff); /* clear all */
- mtdcr(uic0er, 0x00000000); /* disable all */
- mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
- mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
- mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic0sr, 0xffffffff); /* clear all */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(uic1sr, 0xffffffff); /* clear all */
- mtdcr(uic1er, 0x00000000); /* disable all */
- mtdcr(uic1cr, 0x00000000); /* all non-critical */
- mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
- mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
return 0;
}
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 1a45056daa..bcef707403 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -183,42 +183,42 @@ int board_early_init_f (void)
* Set critical interrupt values. Set interrupt polarities. Set interrupt
* trigger levels. Make bit 0 High priority. Clear all interrupts again.
*------------------------------------------------------------------------*/
- mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic3er, 0x00000000); /* disable all interrupts */
- mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */
- mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/
- mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
- mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/
- mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/
-
-
- mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic2er, 0x00000000); /* disable all interrupts*/
- mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
- mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/
- mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
- mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
-
- mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/
- mtdcr (uic1er, 0x00000000); /* disable all interrupts*/
- mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
- mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/
- mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/
- mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/
-
- mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */
- mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/
- mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/
- mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
- mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
- mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
+ mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */
+ mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/
+ mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/
+ mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/
+
+
+ mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/
+ mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
+ mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/
+ mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/
+ mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/
+ mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
+ mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/
+ mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/
+ mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/
+
+ mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */
+ mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/
+ mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/
+ mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/
+ mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index 7e84a61a96..5ebe69272c 100644
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -158,33 +158,33 @@ int board_early_init_f (void)
| interrupts again.
+-------------------------------------------------------------------*/
- mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic2er, 0x00000000); /* disable all interrupts */
- mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
- mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
- mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
-
- mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic1er, 0x00000000); /* disable all interrupts */
- mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
- mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
- mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
-
- mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
+ mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
/* Except cascade UIC0 and UIC1 */
- mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
- mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
- mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
+ mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
+ mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
/*
* Note: Some cores are still in reset when the chip starts, so
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 71ad89fa6c..5f76672fb5 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -49,23 +49,23 @@ int board_early_init_f(void)
mtebc( PB2AP, 0x03800000 );
mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
- mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
- mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
- mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */
- mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */
- mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */
- mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
- mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */
- mtdcr( uic1sr, 0xffffffff );
-
- mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */
- mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */
- mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */
- mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */
- mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */
- mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
- mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
- mtdcr( uic0sr, 0xffffffff );
+ mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */
+ mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */
+ mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */
+ mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */
+ mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */
+ mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */
+ mtdcr( UIC1SR, 0xffffffff );
+
+ mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */
+ mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */
+ mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */
+ mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */
+ mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */
+ mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */
+ mtdcr( UIC0SR, 0xffffffff );
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
index 9fc0ec6667..fb0e7b75eb 100644
--- a/board/amcc/makalu/makalu.c
+++ b/board/amcc/makalu/makalu.c
@@ -159,33 +159,33 @@ int board_early_init_f (void)
| interrupts again.
+-------------------------------------------------------------------*/
- mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic2er, 0x00000000); /* disable all interrupts */
- mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
- mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
- mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
- mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic1er, 0x00000000); /* disable all interrupts */
- mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
- mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
- mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
+ mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
+ mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
- mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
+ mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
/* Except cascade UIC0 and UIC1 */
- mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
- mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
- mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
+ mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
+ mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
/*
* Note: Some cores are still in reset when the chip starts, so
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index 5e32e8a784..8513f43a8f 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -159,36 +159,36 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
- mtdcr (uic1sr, 0xffffffff); /* clear all */
- mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
- mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
- mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
- mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic1sr, 0xffffffff); /* clear all */
-
- mtdcr (uic2sr, 0xffffffff); /* clear all */
- mtdcr (uic2er, 0x00000000); /* disable all */
- mtdcr (uic2cr, 0x00000000); /* all non-critical */
- mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
- mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic2sr, 0xffffffff); /* clear all */
-
- mtdcr (uic3sr, 0xffffffff); /* clear all */
- mtdcr (uic3er, 0x00000000); /* disable all */
- mtdcr (uic3cr, 0x00000000); /* all non-critical */
- mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
- mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
- mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic3sr, 0xffffffff); /* clear all */
-
- mtdcr (uic0sr, 0xfc000000); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000000); /* all non-critical */
- mtdcr (uic0pr, 0xfc000000); /* */
- mtdcr (uic0tr, 0x00000000); /* */
- mtdcr (uic0vr, 0x00000001); /* */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+ mtdcr (UIC1ER, 0x00000000); /* disable all */
+ mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
+ mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
+ mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+ mtdcr (UIC2ER, 0x00000000); /* disable all */
+ mtdcr (UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+ mtdcr (UIC3ER, 0x00000000); /* disable all */
+ mtdcr (UIC3CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
+ mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC0SR, 0xfc000000); /* clear all */
+ mtdcr (UIC0ER, 0x00000000); /* disable all */
+ mtdcr (UIC0CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC0PR, 0xfc000000); /* */
+ mtdcr (UIC0TR, 0x00000000); /* */
+ mtdcr (UIC0VR, 0x00000001); /* */
mfsdr (SDR0_MFR, mfr);
mfr &= ~SDR0_MFR_ECS_MASK;
/* mtsdr(SDR0_MFR, mfr); */
diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c
index 49078ebee2..bc8cb0c443 100644
--- a/board/amcc/redwood/redwood.c
+++ b/board/amcc/redwood/redwood.c
@@ -416,41 +416,41 @@ static void early_init_UIC(void)
* interrupt trigger levels. Make bit 0 High priority. Clear all
* interrupts again.
*/
- mtdcr(uic3sr, 0xffffffff); /* Clear all interrupts */
- mtdcr(uic3er, 0x00000000); /* disable all interrupts */
- mtdcr(uic3cr, 0x00000000); /* Set Critical / Non Critical
+ mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */
+ mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
- mtdcr(uic3pr, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr(uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
- mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic3sr, 0xffffffff); /* clear all interrupts */
-
- mtdcr(uic2sr, 0xffffffff); /* Clear all interrupts */
- mtdcr(uic2er, 0x00000000); /* disable all interrupts */
- mtdcr(uic2cr, 0x00000000); /* Set Critical / Non Critical
+ mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
+ mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
- mtdcr(uic2pr, 0xebebebff); /* Set Interrupt Polarities */
- mtdcr(uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
- mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic2sr, 0xffffffff); /* clear all interrupts */
-
- mtdcr(uic1sr, 0xffffffff); /* Clear all interrupts */
- mtdcr(uic1er, 0x00000000); /* disable all interrupts */
- mtdcr(uic1cr, 0x00000000); /* Set Critical / Non Critical
+ mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
+ mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
+ mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
- mtdcr(uic1pr, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr(uic1tr, 0x001fc0ff); /* Set Interrupt Trigger Levels */
- mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic1sr, 0xffffffff); /* clear all interrupts */
+ mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
- mtdcr(uic0sr, 0xffffffff); /* Clear all interrupts */
- mtdcr(uic0er, 0x00000000); /* disable all interrupts excepted
+ mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted
* cascade to be checked */
- mtdcr(uic0cr, 0x00104001); /* Set Critical / Non Critical
+ mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical
* interrupts */
- mtdcr(uic0pr, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr(uic0tr, 0x000f003c); /* Set Interrupt Trigger Levels */
- mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic0sr, 0xffffffff); /* clear all interrupts */
+ mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
}
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 5913455ba1..17f831c3f4 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -52,29 +52,29 @@ int board_early_init_f(void)
/*
* Setup the interrupt controller polarities, triggers, etc.
*/
- mtdcr(uic0sr, 0xffffffff); /* clear all */
- mtdcr(uic0er, 0x00000000); /* disable all */
- mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
- mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
- mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic0sr, 0xffffffff); /* clear all */
-
- mtdcr(uic1sr, 0xffffffff); /* clear all */
- mtdcr(uic1er, 0x00000000); /* disable all */
- mtdcr(uic1cr, 0x00000000); /* all non-critical */
- mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
- mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
- mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic1sr, 0xffffffff); /* clear all */
-
- mtdcr(uic2sr, 0xffffffff); /* clear all */
- mtdcr(uic2er, 0x00000000); /* disable all */
- mtdcr(uic2cr, 0x00000000); /* all non-critical */
- mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
- mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
- mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
/* 50MHz tmrclk */
out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c
index 4e5796ee82..be381d60ac 100644
--- a/board/amcc/taihu/taihu.c
+++ b/board/amcc/taihu/taihu.c
@@ -40,13 +40,13 @@ int board_early_init_f(void)
{
lcd_init();
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000);
- mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
- mtdcr(uictr, 0x00000000); /* set int trigger levels */
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000);
+ mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
+ mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index 086778a652..4a0573eb38 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -132,36 +132,36 @@ int board_early_init_f (void)
* UIC2 UIC1
* UIC3 UIC2
*/
- mtdcr (uic1sr, 0xffffffff); /* clear all */
- mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
- mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
- mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
- mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic1sr, 0xffffffff); /* clear all */
-
- mtdcr (uic2sr, 0xffffffff); /* clear all */
- mtdcr (uic2er, 0x00000000); /* disable all */
- mtdcr (uic2cr, 0x00000000); /* all non-critical */
- mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
- mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic2sr, 0xffffffff); /* clear all */
-
- mtdcr (uic3sr, 0xffffffff); /* clear all */
- mtdcr (uic3er, 0x00000000); /* disable all */
- mtdcr (uic3cr, 0x00000000); /* all non-critical */
- mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
- mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
- mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic3sr, 0xffffffff); /* clear all */
-
- mtdcr (uic0sr, 0xfc000000); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000000); /* all non-critical */
- mtdcr (uic0pr, 0xfc000000); /* */
- mtdcr (uic0tr, 0x00000000); /* */
- mtdcr (uic0vr, 0x00000001); /* */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+ mtdcr (UIC1ER, 0x00000000); /* disable all */
+ mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
+ mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
+ mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+ mtdcr (UIC2ER, 0x00000000); /* disable all */
+ mtdcr (UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+ mtdcr (UIC3ER, 0x00000000); /* disable all */
+ mtdcr (UIC3CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
+ mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC0SR, 0xfc000000); /* clear all */
+ mtdcr (UIC0ER, 0x00000000); /* disable all */
+ mtdcr (UIC0CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC0PR, 0xfc000000); /* */
+ mtdcr (UIC0TR, 0x00000000); /* */
+ mtdcr (UIC0VR, 0x00000001); /* */
/* Enable two GPIO 10~11 and TraceA signal */
mfsdr(SDR0_PFC0,reg);
diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c
index 28dcb66ebc..4f299324cd 100644
--- a/board/amcc/walnut/walnut.c
+++ b/board/amcc/walnut/walnut.c
@@ -47,13 +47,13 @@ int board_early_init_f(void)
|
+-------------------------------------------------------------------------*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
- mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
+ mtdcr(UIC0PR, 0xFFFFFFE0); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/* set UART1 control to select CTS/RTS */
#define FPGA_BRDC 0xF0300004
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 2a654fa895..731d441526 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -82,21 +82,21 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
- mtdcr(uic0sr, 0xffffffff); /* clear all */
- mtdcr(uic0er, 0x00000000); /* disable all */
- mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
- mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
- mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic0sr, 0xffffffff); /* clear all */
-
- mtdcr(uic1sr, 0xffffffff); /* clear all */
- mtdcr(uic1er, 0x00000000); /* disable all */
- mtdcr(uic1cr, 0x00000000); /* all non-critical */
- mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
- mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
- mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup other serial configuration
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 245004cee8..033bdd20fa 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -485,50 +485,50 @@ int board_early_init_f (void)
| interrupt trigger levels. Make bit 0 High priority. Clear all
| interrupts again.
+-------------------------------------------------------------------*/
- mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic3er, 0x00000000); /* disable all interrupts */
- mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical
+ mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
- mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
- mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest
+ mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
- mtdcr (uic3sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */
+ mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */
- mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic2er, 0x00000000); /* disable all interrupts */
- mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical
+ mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
- mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */
- mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
- mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest
+ mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
+ mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
- mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
+ mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
- mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic1er, 0x00000000); /* disable all interrupts */
- mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical
+ mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical
* interrupts */
- mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */
- mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest
+ mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
- mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
+ mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
- mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted
+ mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted
* cascade to be checked */
- mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical
+ mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical
* interrupts */
- mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */
- mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
- mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest
+ mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest
* priority */
- mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
+ mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
generated by cgit (git 2.34.1) at 2024-12-24 05:46:54 +0000