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-rw-r--r--board/armltd/integrator/arm-ebi.h62
-rw-r--r--board/armltd/integrator/config.mk5
-rw-r--r--board/armltd/integrator/integrator-sc.h91
-rw-r--r--board/armltd/integrator/integrator.c63
4 files changed, 208 insertions, 13 deletions
diff --git a/board/armltd/integrator/arm-ebi.h b/board/armltd/integrator/arm-ebi.h
new file mode 100644
index 0000000000..2d85e3fe90
--- /dev/null
+++ b/board/armltd/integrator/arm-ebi.h
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Register definitions for the External Bus Interface (EBI)
+ * found in the ARM Integrator AP and CP reference designs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARM_EBI_H
+#define __ARM_EBI_H
+
+#define EBI_BASE 0x12000000
+
+#define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */
+#define EBI_CSR1_REG 0x04 /* CS1 = Flash */
+#define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */
+#define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */
+/*
+ * The four upper bits are the waitstates for each chip select
+ * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
+ */
+#define EBI_CSR_WAIT_MASK 0xF0
+/* Whether memory is synchronous or asynchronous */
+#define EBI_CSR_SYNC_MASK 0xF7
+#define EBI_CSR_ASYNC 0x00
+#define EBI_CSR_SYNC 0x08
+/* Whether memory is write enabled or not */
+#define EBI_CSR_WREN_MASK 0xFB
+#define EBI_CSR_WREN_DISABLE 0x00
+#define EBI_CSR_WREN_ENABLE 0x04
+/* Memory bit width for each chip select */
+#define EBI_CSR_MEMSIZE_MASK 0xFC
+#define EBI_CSR_MEMSIZE_8BIT 0x00
+#define EBI_CSR_MEMSIZE_16BIT 0x01
+#define EBI_CSR_MEMSIZE_32BIT 0x02
+
+/*
+ * The lock register need to be written with 0xa05f before anything in the
+ * EBI can be changed.
+ */
+#define EBI_LOCK_REG 0x20
+#define EBI_UNLOCK_MAGIC 0xA05F
+
+#endif
diff --git a/board/armltd/integrator/config.mk b/board/armltd/integrator/config.mk
deleted file mode 100644
index 8b57af1c5e..0000000000
--- a/board/armltd/integrator/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# image should be loaded at 0x01000000
-#
-
-CONFIG_SYS_TEXT_BASE = 0x01000000
diff --git a/board/armltd/integrator/integrator-sc.h b/board/armltd/integrator/integrator-sc.h
new file mode 100644
index 0000000000..279dc55b37
--- /dev/null
+++ b/board/armltd/integrator/integrator-sc.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Register definitions for the System Controller (SC) and
+ * the similar "CP Controller" found in the ARM Integrator/AP and
+ * Integrator/CP reference designs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARM_SC_H
+#define __ARM_SC_H
+
+#define SC_BASE 0x11000000
+
+/*
+ * The system controller registers
+ */
+#define SC_ID_OFFSET 0x00
+#define SC_OSC_OFFSET 0x04
+/* Setting this bit switches to 25 MHz mode, clear means 33 MHz */
+#define SC_OSC_DIVXY (1 << 8)
+#define SC_CTRLS_OFFSET 0x08
+#define SC_CTRLC_OFFSET 0x0C
+/* Set bits by writing CTRLS, clear bits by writing CTRLC */
+#define SC_CTRL_SOFTRESET (1 << 0)
+#define SC_CTRL_FLASHVPP (1 << 1)
+#define SC_CTRL_FLASHWP (1 << 2)
+#define SC_CTRL_UART1DTR (1 << 4)
+#define SC_CTRL_UART1RTS (1 << 5)
+#define SC_CTRL_UART0DTR (1 << 6)
+#define SC_CTRL_UART0RTS (1 << 7)
+#define SC_DEC_OFFSET 0x10
+#define SC_ARB_OFFSET 0x14
+#define SC_PCI_OFFSET 0x18
+#define SC_PCI_PCIEN (1 << 0)
+#define SC_PCI_PCIBINT_CLR (1 << 1)
+#define SC_LOCK_OFFSET 0x1C
+#define SC_LBFADDR_OFFSET 0x20
+#define SC_LBFCODE_OFFSET 0x24
+
+#define SC_ID (SC_BASE + SC_ID_OFFSET)
+#define SC_OSC (SC_BASE + SC_OSC_OFFSET)
+#define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET)
+#define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET)
+#define SC_DEC (SC_BASE + SC_DEC_OFFSET)
+#define SC_ARB (SC_BASE + SC_ARB_OFFSET)
+#define SC_PCI (SC_BASE + SC_PCI_OFFSET)
+#define SC_LOCK (SC_BASE + SC_LOCK_OFFSET)
+#define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET)
+#define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET)
+
+/*
+ * The Integrator/CP as a smaller set of registers, at a different
+ * offset - probably not to disturb old software.
+ */
+
+#define CP_BASE 0xCB000000
+
+#define CP_IDFIELD_OFFSET 0x00
+#define CP_FLASHPROG_OFFSET 0x04
+#define CP_FLASHPROG_FLVPPEN (1 << 0)
+#define CP_FLASHPROG_FLWREN (1 << 1)
+#define CP_FLASHPROG_FLASHSIZE (1 << 2)
+#define CP_FLASHPROG_EXTRABANK (1 << 3)
+#define CP_INTREG_OFFSET 0x08
+#define CP_DECODE_OFFSET 0x0C
+
+#define CP_IDFIELD (CP_BASE + CP_ID_OFFSET)
+#define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET)
+#define CP_INTREG (CP_BASE + CP_INTREG_OFFSET)
+#define CP_DECODE (CP_BASE + CP_DECODE_OFFSET)
+
+#endif
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index c8d2bc7bac..a507c093aa 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c
@@ -35,6 +35,9 @@
#include <common.h>
#include <netdev.h>
+#include <asm/io.h>
+#include "arm-ebi.h"
+#include "integrator-sc.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +58,8 @@ void show_boot_progress(int progress)
int board_init (void)
{
+ u32 val;
+
/* arch number of Integrator Board */
#ifdef CONFIG_ARCH_CINTEGRATOR
gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
@@ -72,6 +77,37 @@ extern void cm_remap(void);
cm_remap(); /* remaps writeable memory to 0x00000000 */
#endif
+#ifdef CONFIG_ARCH_CINTEGRATOR
+ /*
+ * Flash protection on the Integrator/CP is in a simple register
+ */
+ val = readl(CP_FLASHPROG);
+ val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
+ writel(val, CP_FLASHPROG);
+#else
+ /*
+ * The Integrator/AP has some special protection mechanisms
+ * for the external memories, first the External Bus Interface (EBI)
+ * then the system controller (SC).
+ *
+ * The system comes up with the flash memory non-writable and
+ * configuration locked. If we want U-Boot to be used for flash
+ * access we cannot have the flash memory locked.
+ */
+ writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
+ val = readl(EBI_BASE + EBI_CSR1_REG);
+ val &= EBI_CSR_WREN_MASK;
+ val |= EBI_CSR_WREN_ENABLE;
+ writel(val, EBI_BASE + EBI_CSR1_REG);
+ writel(0, EBI_BASE + EBI_LOCK_REG);
+
+ /*
+ * Set up the system controller to remove write protection from
+ * the flash memory and enable Vpp
+ */
+ writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
+#endif
+
icache_enable ();
return 0;
@@ -86,21 +122,30 @@ int misc_init_r (void)
return (0);
}
+/*
+ * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
+ * from there, which means we cannot test the RAM underneath the ROM at this
+ * point. It will be unmapped later on, when we are executing from the
+ * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
+ * RAM on higher addresses works fine.
+ */
+#define REMAPPED_FLASH_SZ 0x40000
+
int dram_init (void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
#ifdef CONFIG_CM_SPD_DETECT
{
extern void dram_query(void);
- unsigned long cm_reg_sdram;
- unsigned long sdram_shift;
+ u32 cm_reg_sdram;
+ u32 sdram_shift;
dram_query(); /* Assembler accesses to CM registers */
/* Queries the SPD values */
/* Obtain the SDRAM size from the CM SDRAM register */
- cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
+ cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
/* Register SDRAM size
*
* 0xXXXXXXbbb000bb 16 MB
@@ -110,16 +155,18 @@ extern void dram_query(void);
* 0xXXXXXXbbb100bb 256 MB
*
*/
- sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
- gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
+ gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+ REMAPPED_FLASH_SZ,
0x01000000 << sdram_shift);
}
#else
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+ REMAPPED_FLASH_SZ,
PHYS_SDRAM_1_SIZE);
#endif /* CM_SPD_DETECT */
+ /* We only have one bank of RAM, set it to whatever was detected */
+ gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
}
generated by cgit (git 2.34.1) at 2024-12-26 02:50:51 +0000