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-rw-r--r--board/eric/eric.c2
-rw-r--r--board/eric/flash.c20
-rw-r--r--board/eric/init.S126
3 files changed, 74 insertions, 74 deletions
diff --git a/board/eric/eric.c b/board/eric/eric.c
index 600b9d7a7c..bc2a907f6b 100644
--- a/board/eric/eric.c
+++ b/board/eric/eric.c
@@ -70,7 +70,7 @@ int board_early_init_f (void)
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr (cntrl0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
+ mtdcr (CPC0_CR0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
out32 (PPC405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
out32 (PPC405GP_GPIO0_TCR, 0x7E400000);
diff --git a/board/eric/flash.c b/board/eric/flash.c
index 7e57513aeb..fded41271f 100644
--- a/board/eric/flash.c
+++ b/board/eric/flash.c
@@ -105,24 +105,24 @@ unsigned long flash_init (void)
if (size_b1)
{
- mtdcr(ebccfga, pb0cr);
- pbcr = mfdcr(ebccfgd);
- mtdcr(ebccfga, pb0cr);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
- mtdcr(ebccfgd, pbcr);
- /* printf("pb1cr = %x\n", pbcr); */
+ mtdcr(EBC0_CFGDATA, pbcr);
+ /* printf("PB1CR = %x\n", pbcr); */
}
if (size_b0)
{
- mtdcr(ebccfga, pb1cr);
- pbcr = mfdcr(ebccfgd);
- mtdcr(ebccfga, pb1cr);
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB1CR);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
- mtdcr(ebccfgd, pbcr);
- /* printf("pb0cr = %x\n", pbcr); */
+ mtdcr(EBC0_CFGDATA, pbcr);
+ /* printf("PB0CR = %x\n", pbcr); */
}
size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);
diff --git a/board/eric/init.S b/board/eric/init.S
index 4820dd08c7..16ab11eae2 100644
--- a/board/eric/init.S
+++ b/board/eric/init.S
@@ -76,129 +76,129 @@ ext_bus_cntlr_init:
/* Memory Bank 0 (Flash) initialization (from openbios) */
/*----------------------------------------------------------------------- */
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
+ addi r4,0,PB1AP
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS0_AP@h
ori r4,r4,CS0_AP@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS0_CR@h
ori r4,r4,CS0_CR@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 1 (NVRAM/RTC) initialization */
/*----------------------------------------------------------------------- */
- addi r4,0,pb1ap
- mtdcr ebccfga,r4
+ addi r4,0,PB1AP
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS1_AP@h
ori r4,r4,CS1_AP@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb1cr
- mtdcr ebccfga,r4
+ addi r4,0,PB1CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS1_CR@h
ori r4,r4,CS1_CR@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 2 (A/D converter) initialization */
/*----------------------------------------------------------------------- */
- addi r4,0,pb2ap
- mtdcr ebccfga,r4
+ addi r4,0,PB2AP
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS2_AP@h
ori r4,r4,CS2_AP@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb2cr
- mtdcr ebccfga,r4
+ addi r4,0,PB2CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS2_CR@h
ori r4,r4,CS2_CR@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 3 (Ethernet PHY Reset) initialization */
/*----------------------------------------------------------------------- */
- addi r4,0,pb3ap
- mtdcr ebccfga,r4
+ addi r4,0,PB3AP
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS3_AP@h
ori r4,r4,CS3_AP@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb3cr
- mtdcr ebccfga,r4
+ addi r4,0,PB3CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS3_CR@h
ori r4,r4,CS3_CR@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
/*----------------------------------------------------------------------- */
- addi r4,0,pb4ap
- mtdcr ebccfga,r4
+ addi r4,0,PB4AP
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS4_AP@h
ori r4,r4,CS4_AP@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb4cr
- mtdcr ebccfga,r4
+ addi r4,0,PB4CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS4_CR@h
ori r4,r4,CS4_CR@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
/*----------------------------------------------------------------------- */
- addi r4,0,pb5ap
- mtdcr ebccfga,r4
+ addi r4,0,PB5AP
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS5_AP@h
ori r4,r4,CS5_AP@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb5cr
- mtdcr ebccfga,r4
+ addi r4,0,PB5CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS5_CR@h
ori r4,r4,CS5_CR@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 6 (CPU LED0) initialization */
/*----------------------------------------------------------------------- */
- addi r4,0,pb6ap
- mtdcr ebccfga,r4
+ addi r4,0,PB6AP
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS6_AP@h
ori r4,r4,CS6_AP@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb6cr
- mtdcr ebccfga,r4
+ addi r4,0,PB6CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS6_CR@h
ori r4,r4,CS5_CR@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
/*----------------------------------------------------------------------- */
/* Memory Bank 7 (CPU LED1) initialization */
/*----------------------------------------------------------------------- */
- addi r4,0,pb7ap
- mtdcr ebccfga,r4
+ addi r4,0,PB7AP
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS7_AP@h
ori r4,r4,CS7_AP@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
- addi r4,0,pb7cr
- mtdcr ebccfga,r4
+ addi r4,0,PB7CR
+ mtdcr EBC0_CFGADDR,r4
addis r4,0,CS7_CR@h
ori r4,r4,CS7_CR@l
- mtdcr ebccfgd,r4
+ mtdcr EBC0_CFGDATA,r4
/* addis r4,r0,FPGA_BRDC@h */
/* ori r4,r4,FPGA_BRDC@l */
@@ -229,40 +229,40 @@ sdram_init:
/*------------------------------------------------------------------- */
addi r4,0,mem_mb0cf
- mtdcr memcfga,r4
+ mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB0CF@h
ori r4,r4,MB0CF@l
- mtdcr memcfgd,r4
+ mtdcr SDRAM0_CFGDATA,r4
/*------------------------------------------------------------------- */
/* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
/*------------------------------------------------------------------- */
addi r4,0,mem_mb1cf
- mtdcr memcfga,r4
+ mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB1CF@h
ori r4,r4,MB1CF@l
- mtdcr memcfgd,r4
+ mtdcr SDRAM0_CFGDATA,r4
/*------------------------------------------------------------------- */
/* Set MB2CF for bank 2. off */
/*------------------------------------------------------------------- */
addi r4,0,mem_mb2cf
- mtdcr memcfga,r4
+ mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB2CF@h
ori r4,r4,MB2CF@l
- mtdcr memcfgd,r4
+ mtdcr SDRAM0_CFGDATA,r4
/*------------------------------------------------------------------- */
/* Set MB3CF for bank 3. off */
/*------------------------------------------------------------------- */
addi r4,0,mem_mb3cf
- mtdcr memcfga,r4
+ mtdcr SDRAM0_CFGADDR,r4
addis r4,0,MB3CF@h
ori r4,r4,MB3CF@l
- mtdcr memcfgd,r4
+ mtdcr SDRAM0_CFGDATA,r4
/*------------------------------------------------------------------- */
/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
@@ -276,7 +276,7 @@ sdram_init:
/* maybe 133Mhz. */
/*------------------------------------------------------------------- */
- mfdcr r5,strap /* determine FBK divider */
+ mfdcr r5,CPC0_PSR /* determine FBK divider */
/* via STRAP reg to calc PLB speed. */
/* SDRAM speed is the same as the PLB */
/* speed. */
@@ -306,15 +306,15 @@ sdram_init:
/* Set SDTR1 */
/*------------------------------------------------------------------- */
addi r4,0,mem_sdtr1
- mtdcr memcfga,r4
- mtdcr memcfgd,r6
+ mtdcr SDRAM0_CFGADDR,r4
+ mtdcr SDRAM0_CFGDATA,r6
/*------------------------------------------------------------------- */
/* Set RTR */
/*------------------------------------------------------------------- */
addi r4,0,mem_rtr
- mtdcr memcfga,r4
- mtdcr memcfgd,r7
+ mtdcr SDRAM0_CFGADDR,r4
+ mtdcr SDRAM0_CFGDATA,r7
/*------------------------------------------------------------------- */
/* Delay to ensure 200usec have elapsed since reset. Assume worst */
@@ -333,10 +333,10 @@ sdram_init:
/* read/prefetch. */
/*------------------------------------------------------------------- */
addi r4,0,mem_mcopt1
- mtdcr memcfga,r4
+ mtdcr SDRAM0_CFGADDR,r4
addis r4,0,0x8080 /* set DC_EN=1 */
ori r4,r4,0x0000
- mtdcr memcfgd,r4
+ mtdcr SDRAM0_CFGDATA,r4
/*------------------------------------------------------------------- */
/* Delay to ensure 10msec have elapsed since reset. This is */
generated by cgit (git 2.34.1) at 2024-12-27 14:20:36 +0000