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-rw-r--r--board/freescale/mpc8349emds/Kconfig13
-rw-r--r--board/freescale/mpc8349emds/MAINTAINERS3
-rw-r--r--board/freescale/mpc8349emds/mpc8349emds.c37
-rw-r--r--board/freescale/mpc8349emds/pci.c12
4 files changed, 45 insertions, 20 deletions
diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig
index 51f0b34f39..d154118079 100644
--- a/board/freescale/mpc8349emds/Kconfig
+++ b/board/freescale/mpc8349emds/Kconfig
@@ -10,3 +10,16 @@ config SYS_CONFIG_NAME
default "MPC8349EMDS"
endif
+
+if TARGET_MPC8349EMDS_SDRAM
+
+config SYS_BOARD
+ default "mpc8349emds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8349EMDS_SDRAM"
+
+endif
diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS
index e6648d66a0..a8f26a9a31 100644
--- a/board/freescale/mpc8349emds/MAINTAINERS
+++ b/board/freescale/mpc8349emds/MAINTAINERS
@@ -4,3 +4,6 @@ S: Orphan (since 2018-05)
F: board/freescale/mpc8349emds/
F: include/configs/MPC8349EMDS.h
F: configs/MPC8349EMDS_defconfig
+F: configs/MPC8349EMDS_SDRAM_defconfig
+F: configs/MPC8349EMDS_PCI64_defconfig
+F: configs/MPC8349EMDS_SLAVE_defconfig
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index d40ed3742e..913b5843e9 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -56,7 +56,7 @@ int dram_init(void)
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
#ifndef CONFIG_SYS_FSL_DDR2
msize = spd_sdram() * 1024 * 1024;
@@ -91,7 +91,7 @@ int fixed_sdram(void)
u32 ddr_size = msize << 20; /* DDR size in bytes */
u32 ddr_size_log2 = __ilog2(ddr_size);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
@@ -112,12 +112,12 @@ int fixed_sdram(void)
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
#else
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[2].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
CSBNDS_EA_SHIFT) & CSBNDS_EA);
im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
@@ -183,28 +183,36 @@ void sdram_init(void)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
+ const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
+ LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
+ LSDMR_WRC3 | LSDMR_CL3;
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
/* setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->lbcr = 0x00000000;
+ /* LB refresh timer prescal, 266MHz/32 */
+ lbc->mrtpr = 0x20000000;
+ /* LB sdram refresh timer, about 6us */
+ lbc->lsrt = 0x32000000;
asm("sync");
/*
* Configure the SDRAM controller Machine Mode Register.
*/
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+
+ /* 0x68636733; precharge all the banks */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+ /* 0x48636733; auto refresh */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync");
/*1 times*/
*sdram_addr = 0xff;
@@ -232,12 +240,13 @@ void sdram_init(void)
udelay(100);
/* 0x58636733; mode register write operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ /* 0x40636733; normal operation */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
index a2feda855f..005190ed87 100644
--- a/board/freescale/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -77,11 +77,11 @@ void pib_init(void)
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
-#if defined(PCI_64BIT)
+#if defined(CONFIG_PCI_64BIT)
val8 = 0xf4; /* PMC2:PCI1/64-bit */
-#elif defined(PCI_ALL_PCI1)
+#elif defined(CONFIG_PCI_ALL_PCI1)
val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
-#elif defined(PCI_ONE_PCI1)
+#elif defined(CONFIG_PCI_ONE_PCI1)
val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
#else
val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
@@ -98,11 +98,11 @@ void pib_init(void)
i2c_write(0x27, 0x3, 1, &val8, 1);
asm("eieio");
-#if defined(PCI_64BIT)
+#if defined(CONFIG_PCI_64BIT)
printf("PCI1: 64-bit on PMC2\n");
-#elif defined(PCI_ALL_PCI1)
+#elif defined(CONFIG_PCI_ALL_PCI1)
printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
-#elif defined(PCI_ONE_PCI1)
+#elif defined(CONFIG_PCI_ONE_PCI1)
printf("PCI1: 32-bit on PMC1\n");
printf("PCI2: 32-bit on PMC2, PMC3\n");
#else
generated by cgit (git 2.34.1) at 2025-01-12 07:53:27 +0000