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-rw-r--r--board/freescale/mx31ads/u-boot.lds32
-rw-r--r--board/freescale/mx31pdk/Makefile3
-rw-r--r--board/freescale/mx31pdk/config.mk5
-rw-r--r--board/freescale/mx31pdk/mx31pdk.c8
-rw-r--r--board/freescale/mx53ard/mx53ard.c66
-rw-r--r--board/freescale/mx6qsabreauto/mx6qsabreauto.c18
-rw-r--r--board/freescale/mx6qsabrelite/README4
-rw-r--r--board/freescale/mx6qsabrelite/mx6qsabrelite.c8
-rw-r--r--board/freescale/mx6qsabresd/mx6qsabresd.c48
9 files changed, 158 insertions, 34 deletions
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 264c4e80ad..4969960001 100644
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -37,23 +37,23 @@ SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/arm/cpu/arm1136/start.o (.text)
- board/freescale/mx31ads/libmx31ads.o (.text)
- arch/arm/lib/libarm.o (.text)
- net/libnet.o (.text)
- drivers/mtd/libmtd.o (.text)
+ arch/arm/cpu/arm1136/start.o (.text*)
+ board/freescale/mx31ads/libmx31ads.o (.text*)
+ arch/arm/lib/libarm.o (.text*)
+ net/libnet.o (.text*)
+ drivers/mtd/libmtd.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o(.text)
+ common/env_embedded.o(.text*)
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
- .rodata : { *(.rodata) }
+ .rodata : { *(.rodata*) }
. = ALIGN(4);
.data : {
- *(.data)
+ *(.data*)
}
. = ALIGN(4);
@@ -80,17 +80,23 @@ SECTIONS
_end = .;
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
+ __bss_base = .;
}
- .bss __bss_start (OVERLAY) : {
+ .bss __bss_base (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- __bss_end = .;
+ __bss_limit = .;
}
- .bss_end __bss_end (OVERLAY) : {
- KEEP(*(__bss_end));
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.bss*) }
diff --git a/board/freescale/mx31pdk/Makefile b/board/freescale/mx31pdk/Makefile
index 5b7cafd9f6..b91072285a 100644
--- a/board/freescale/mx31pdk/Makefile
+++ b/board/freescale/mx31pdk/Makefile
@@ -27,6 +27,9 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
+ifdef CONFIG_SPL_BUILD
+SOBJS := lowlevel_init.o
+endif
COBJS := mx31pdk.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/freescale/mx31pdk/config.mk b/board/freescale/mx31pdk/config.mk
deleted file mode 100644
index de2c6429c5..0000000000
--- a/board/freescale/mx31pdk/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-ifdef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = 0x87ec0000
-else
-CONFIG_SYS_TEXT_BASE = 0x87f00000
-endif
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
index 895396cd62..49158bd90d 100644
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -36,6 +36,14 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong bootflag)
+{
+ relocate_code(CONFIG_SPL_TEXT_BASE);
+ asm volatile("ldr pc, =nand_boot");
+}
+#endif
+
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c
index 2fc8570f23..8d433a3d86 100644
--- a/board/freescale/mx53ard/mx53ard.c
+++ b/board/freescale/mx53ard/mx53ard.c
@@ -58,6 +58,71 @@ void dram_init_banksize(void)
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
+#ifdef CONFIG_NAND_MXC
+static void setup_iomux_nand(void)
+{
+ u32 i, reg;
+ #define M4IF_GENP_WEIM_MM_MASK 0x00000001
+ #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
+
+ reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
+ reg &= ~M4IF_GENP_WEIM_MM_MASK;
+ __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
+ for (i = 0x4; i < 0x94; i += 0x18) {
+ reg = __raw_readl(WEIM_BASE_ADDR + i);
+ reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
+ __raw_writel(reg, WEIM_BASE_ADDR + i);
+ }
+
+ mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
+ mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
+ mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+}
+#else
+static void setup_iomux_nand(void)
+{
+}
+#endif
+
static void setup_iomux_uart(void)
{
/* UART1 RXD */
@@ -277,6 +342,7 @@ static void weim_cs1_settings(void)
int board_early_init_f(void)
{
+ setup_iomux_nand();
setup_iomux_uart();
return 0;
}
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 91cc0073bd..aec3286e25 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -26,6 +26,7 @@
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
@@ -216,6 +217,23 @@ int board_init(void)
return 0;
}
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
+
int checkboard(void)
{
int rev = mx6sabre_rev();
diff --git a/board/freescale/mx6qsabrelite/README b/board/freescale/mx6qsabrelite/README
index 6f2f5343de..12a9c856cf 100644
--- a/board/freescale/mx6qsabrelite/README
+++ b/board/freescale/mx6qsabrelite/README
@@ -40,7 +40,7 @@ enter the following commands:
MX6Q SABRELITE U-Boot > mmc dev 0
MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200
- MX6Q SABRELITE U-Boot > sf probe 1
+ MX6Q SABRELITE U-Boot > sf probe
MX6Q SABRELITE U-Boot > sf erase 0 0x40000
MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000
@@ -63,7 +63,7 @@ https://wiki.linaro.org/Boards/MX6QSabreLite
To build U-Boot for the SabreLite board:
make mx6qsabrelite_config
- make u-boot.imx
+ make
To copy the resulting u-boot.imx to the SD card:
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 5b69a6d2de..9f9cac82c4 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -274,6 +274,9 @@ int board_mmc_init(bd_t *bis)
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ usdhc_cfg[1].max_bus_width = 4;
+
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
@@ -298,11 +301,6 @@ int board_mmc_init(bd_t *bis)
}
#endif
-u32 get_board_rev(void)
-{
- return 0x63000 ;
-}
-
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c
index 2b3926aaf3..0d7cb9efd0 100644
--- a/board/freescale/mx6qsabresd/mx6qsabresd.c
+++ b/board/freescale/mx6qsabresd/mx6qsabresd.c
@@ -26,10 +26,12 @@
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
+
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
@@ -145,21 +147,34 @@ struct fsl_esdhc_cfg usdhc_cfg[3] = {
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
- return !gpio_get_value(USDHC2_CD_GPIO);
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
case USDHC3_BASE_ADDR:
- return !gpio_get_value(USDHC3_CD_GPIO);
- default:
- return 1; /* eMMC/uSDHC4 is always present */
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = 1; /* eMMC/uSDHC4 is always present */
+ break;
}
+
+ return ret;
}
int board_mmc_init(bd_t *bis)
{
int i;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 SD2
+ * mmc1 SD3
+ * mmc2 eMMC
+ */
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
@@ -239,11 +254,6 @@ int board_eth_init(bd_t *bis)
return 0;
}
-u32 get_board_rev(void)
-{
- return 0x63000;
-}
-
int board_early_init_f(void)
{
setup_iomux_uart();
@@ -259,6 +269,26 @@ int board_init(void)
return 0;
}
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ /* 8 bit bus width */
+ {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
+
int checkboard(void)
{
puts("Board: MX6Q-SabreSD\n");
generated by cgit (git 2.34.1) at 2025-01-09 10:21:11 +0000