diff options
Diffstat (limited to 'board/freescale')
39 files changed, 1503 insertions, 77 deletions
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile index e5cc054a01..0acd2a9aa4 100644 --- a/board/freescale/b4860qds/Makefile +++ b/board/freescale/b4860qds/Makefile @@ -4,9 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-y += b4860qds.o -obj-y += ddr.o obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o -obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_PCI) += pci.o +endif + +obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg index 57b726eead..05377bac5b 100644 --- a/board/freescale/b4860qds/b4_pbi.cfg +++ b/board/freescale/b4860qds/b4_pbi.cfg @@ -22,6 +22,9 @@ 09110024 00100008 09110028 00100008 0911002c 00100008 +#slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 #Flush PBL data 09138000 00000000 091380c0 00000000 diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index 187c3b3ebc..2c17156586 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -179,6 +179,7 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); @@ -186,7 +187,9 @@ phys_size_t initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c new file mode 100644 index 0000000000..3aa5a780f4 --- /dev/null +++ b/board/freescale/b4860qds/spl.c @@ -0,0 +1,114 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/spl.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include "../common/qixis.h" +#include "b4860qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((sysclk_conf & 0x0C) >> 2) { + case QIXIS_CLK_100: + return 100000000; + case QIXIS_CLK_125: + return 125000000; + case QIXIS_CLK_133: + return 133333333; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch (ddrclk_conf & 0x03) { + case QIXIS_CLK_100: + return 100000000; + case QIXIS_CLK_125: + return 125000000; + case QIXIS_CLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); + env_relocate(); +#else + /* relocate environment function pointers etc. */ + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#endif + + i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_boot(); +#endif +} diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c index 00798a1c19..7b55b860d0 100644 --- a/board/freescale/b4860qds/tlb.c +++ b/board/freescale/b4860qds/tlb.c @@ -62,6 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -96,6 +97,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -118,6 +120,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for SRIO2. */ +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_SYS_SRIO1_MEM_PHYS /* *I*G* - SRIO1 */ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, @@ -140,6 +143,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 17, BOOKE_PAGESZ_1M, 1), #endif +#endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 17, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/qemu-ppce500/Makefile b/board/freescale/qemu-ppce500/Makefile new file mode 100644 index 0000000000..2d2749205f --- /dev/null +++ b/board/freescale/qemu-ppce500/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += qemu-ppce500.o diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c new file mode 100644 index 0000000000..3dbb0cf43b --- /dev/null +++ b/board/freescale/qemu-ppce500/qemu-ppce500.c @@ -0,0 +1,348 @@ +/* + * Copyright 2007,2009-2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/fsl_pci.h> +#include <asm/io.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <netdev.h> +#include <fdtdec.h> +#include <errno.h> +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void *get_fdt_virt(void) +{ + return (void *)CONFIG_SYS_TMPVIRT; +} + +static uint64_t get_fdt_phys(void) +{ + return (uint64_t)(uintptr_t)gd->fdt_blob; +} + +static void map_fdt_as(int esel) +{ + u32 mas0, mas1, mas2, mas3, mas7; + uint64_t fdt_phys = get_fdt_phys(); + unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful; + unsigned long fdt_virt_tlb = (ulong)get_fdt_virt() & ~0xffffful; + + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(esel); + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); + mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0); + mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb); + + write_tlb(mas0, mas1, mas2, mas3, mas7); +} + +uint64_t get_phys_ccsrbar_addr_early(void) +{ + void *fdt = get_fdt_virt(); + uint64_t r; + + /* + * To be able to read the FDT we need to create a temporary TLB + * map for it. + */ + map_fdt_as(10); + r = fdt_get_base_address(fdt, fdt_path_offset(fdt, "/soc")); + disable_tlb(10); + + return r; +} + +int board_early_init_f(void) +{ + return 0; +} + +int checkboard(void) +{ + return 0; +} + +static int pci_map_region(void *fdt, int pci_node, int range_id, + phys_size_t *ppaddr, pci_addr_t *pvaddr, + pci_size_t *psize, ulong *pmap_addr) +{ + uint64_t addr; + uint64_t size; + ulong map_addr; + int r; + + r = fdt_read_range(fdt, pci_node, 0, NULL, &addr, &size); + if (r) + return r; + + if (ppaddr) + *ppaddr = addr; + if (psize) + *psize = size; + + if (!pmap_addr) + return 0; + + map_addr = *pmap_addr; + + /* Align map_addr */ + map_addr += size - 1; + map_addr &= ~(size - 1); + + if (map_addr + size >= CONFIG_SYS_PCI_MAP_END) + return -1; + + /* Map virtual memory for range */ + assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO)); + *pmap_addr = map_addr + size; + + if (pvaddr) + *pvaddr = map_addr; + + return 0; +} + +void pci_init_board(void) +{ + struct pci_controller *pci_hoses; + void *fdt = get_fdt_virt(); + int pci_node = -1; + int pci_num = 0; + int pci_count = 0; + ulong map_addr; + + puts("\n"); + + /* Start MMIO and PIO range maps above RAM */ + map_addr = CONFIG_SYS_PCI_MAP_START; + + /* Count and allocate PCI buses */ + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + while (pci_node != -FDT_ERR_NOTFOUND) { + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + pci_count++; + } + + if (pci_count) { + pci_hoses = malloc(sizeof(struct pci_controller) * pci_count); + } else { + printf("PCI: disabled\n\n"); + return; + } + + /* Spawn PCI buses based on device tree */ + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + while (pci_node != -FDT_ERR_NOTFOUND) { + struct fsl_pci_info pci_info = { }; + const fdt32_t *reg; + int r; + + reg = fdt_getprop(fdt, pci_node, "reg", NULL); + pci_info.regs = fdt_translate_address(fdt, pci_node, reg); + + /* Map MMIO range */ + r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL, + &pci_info.mem_size, &map_addr); + if (r) + break; + + /* Map PIO range */ + r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL, + &pci_info.io_size, &map_addr); + if (r) + break; + + /* + * The PCI framework finds virtual addresses for the buses + * through our address map, so tell it the physical addresses. + */ + pci_info.mem_bus = pci_info.mem_phys; + pci_info.io_bus = pci_info.io_phys; + + /* Instantiate */ + pci_info.pci_num = pci_num + 1; + + fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs); + printf("PCI: base address %lx\n", pci_info.regs); + + fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num); + + /* Jump to next PCI node */ + pci_node = fdt_node_offset_by_prop_value(fdt, pci_node, + "device_type", "pci", 4); + pci_num++; + } + + puts("\n"); +} + +int last_stage_init(void) +{ + void *fdt = get_fdt_virt(); + int len = 0; + const uint64_t *prop; + int chosen; + + chosen = fdt_path_offset(fdt, "/chosen"); + if (chosen < 0) { + printf("Couldn't find /chosen node in fdt\n"); + return -EIO; + } + + /* -kernel boot */ + prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len); + if (prop && (len >= 8)) + setenv_hex("qemu_kernel_addr", *prop); + + /* Give the user a variable for the host fdt */ + setenv_hex("fdt_addr_r", (ulong)fdt); + + return 0; +} + +static uint64_t get_linear_ram_size(void) +{ + void *fdt = get_fdt_virt(); + const void *prop; + int memory; + int len; + + memory = fdt_path_offset(fdt, "/memory"); + prop = fdt_getprop(fdt, memory, "reg", &len); + + if (prop && len >= 16) + return *(uint64_t *)(prop+8); + + panic("Couldn't determine RAM size"); +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} +#endif + +void print_laws(void) +{ + /* We don't emulate LAWs yet */ +} + +phys_size_t fixed_sdram(void) +{ + return get_linear_ram_size(); +} + +phys_size_t fsl_ddr_sdram_size(void) +{ + return get_linear_ram_size(); +} + +void init_tlbs(void) +{ + phys_size_t ram_size; + + /* + * Create a temporary AS=1 map for the fdt + * + * We use ESEL=0 here to overwrite the previous AS=0 map for ourselves + * which was only 4k big. This way we don't have to clear any other maps. + */ + map_fdt_as(0); + + /* Fetch RAM size from the fdt */ + ram_size = get_linear_ram_size(); + + /* And remove our fdt map again */ + disable_tlb(0); + + /* Create an internal map of manually created TLB maps */ + init_used_tlb_cams(); + + /* Create a dynamic AS=0 CCSRBAR mapping */ + assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + 1024 * 1024, TLB_MAP_IO)); + + /* Create a RAM map that spans all accessible RAM */ + setup_ddr_tlbs(ram_size >> 20); + + /* Create a map for the TLB */ + assert(!tlb_map_range((ulong)get_fdt_virt(), get_fdt_phys(), + 1024 * 1024, TLB_MAP_RAM)); +} + +void init_laws(void) +{ + /* We don't emulate LAWs yet */ +} + +static uint32_t get_cpu_freq(void) +{ + void *fdt = get_fdt_virt(); + int cpus_node = fdt_path_offset(fdt, "/cpus"); + int cpu_node = fdt_first_subnode(fdt, cpus_node); + const char *prop = "clock-frequency"; + return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0); +} + +void get_sys_info(sys_info_t *sys_info) +{ + int freq = get_cpu_freq(); + + memset(sys_info, 0, sizeof(sys_info_t)); + sys_info->freq_systembus = freq; + sys_info->freq_ddrbus = freq; + sys_info->freq_processor[0] = freq; +} + +int get_clocks (void) +{ + sys_info_t sys_info; + + get_sys_info(&sys_info); + + gd->cpu_clk = sys_info.freq_processor[0]; + gd->bus_clk = sys_info.freq_systembus; + gd->mem_clk = sys_info.freq_ddrbus; + gd->arch.lbc_clk = sys_info.freq_ddrbus; + + return 0; +} + +unsigned long get_tbclk (void) +{ + void *fdt = get_fdt_virt(); + int cpus_node = fdt_path_offset(fdt, "/cpus"); + int cpu_node = fdt_first_subnode(fdt, cpus_node); + const char *prop = "timebase-frequency"; + return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0); +} + +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq (ulong dummy) +{ + sys_info_t sys_info; + get_sys_info(&sys_info); + return sys_info.freq_systembus; +} diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index da89a36b96..43f952f9c0 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -39,14 +39,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (pbsp->n_ranks == pdimm->n_ranks && (pdimm->rank_density >> 30) >= pbsp->rank_gb) { if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; popts->clk_adjust = pbsp->clk_adjust; popts->wrlvl_start = pbsp->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp->force_2t; goto found; } pbsp_highest = pbsp; @@ -59,13 +55,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, printf("for data rate %lu MT/s\n", ddr_freq); printf("Trying to use the highest speed (%u) parameters\n", pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; popts->clk_adjust = pbsp_highest->clk_adjust; popts->wrlvl_start = pbsp_highest->wrlvl_start; popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp_highest->force_2t; } else { panic("DIMM is not supported by this board"); } @@ -81,7 +74,7 @@ found: * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ - popts->half_strength_driver_enable = 0; + popts->half_strength_driver_enable = 1; /* * Write leveling override */ @@ -97,8 +90,14 @@ found: popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif } phys_size_t initdram(int board_type) diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h index afa72af26a..a6e1673525 100644 --- a/board/freescale/t1040qds/ddr.h +++ b/board/freescale/t1040qds/ddr.h @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,9 +14,6 @@ struct board_specific_parameters { u32 wrlvl_start; u32 wrlvl_ctl_2; u32 wrlvl_ctl_3; - u32 cpo; - u32 write_data_delay; - u32 force_2t; }; /* @@ -28,21 +25,25 @@ struct board_specific_parameters { static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, - {2, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, - {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, - {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, - {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, - {1, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, - {1, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, - {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, - {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, - {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, - {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, + {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,}, +#elif defined(CONFIG_SYS_FSL_DDR3) + {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, +#else +#error DDR type not defined +#endif {} }; diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 3dec4473e5..0e83d172da 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -18,6 +18,8 @@ #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> +#include <hwconfig.h> +#include <asm/mpc85xx_gpio.h> #include "../common/qixis.h" #include "t1040qds.h" @@ -89,6 +91,30 @@ int select_i2c_ch_pca9547(u8 ch) return 0; } +static void qe_board_setup(void) +{ + u8 brdcfg15, brdcfg9; + + if (hwconfig("qe") && hwconfig("tdm")) { + brdcfg15 = QIXIS_READ(brdcfg[15]); + /* + * TDMRiser uses QE-TDM + * Route QE_TDM signals to TDM Riser slot + */ + QIXIS_WRITE(brdcfg[15], brdcfg15 | 7); + } else if (hwconfig("qe") && hwconfig("uart")) { + brdcfg15 = QIXIS_READ(brdcfg[15]); + brdcfg9 = QIXIS_READ(brdcfg[9]); + /* + * Route QE_TDM signals to UCC + * ProfiBus controlled by UCC3 + */ + brdcfg15 &= 0xfc; + QIXIS_WRITE(brdcfg[15], brdcfg15 | 2); + QIXIS_WRITE(brdcfg[9], brdcfg9 | 4); + } +} + int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE @@ -196,6 +222,8 @@ int misc_init_r(void) } } + qe_board_setup(); + return 0; } @@ -245,3 +273,14 @@ int board_need_mem_reset(void) { return 1; } + +#ifdef CONFIG_DEEP_SLEEP +void board_mem_sleep_setup(void) +{ + /* does not provide HW signals for power management */ + QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index e51fb7a7f4..6cd304cce9 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -4,10 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # - +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-y += t104xrdb.o -obj-y += ddr.o +obj-y += cpld.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index 1da52bb0b0..cdbe1fafd9 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -198,3 +198,76 @@ The below commands apply to the board 2.To change from vbank4 to vbank0 => qixis reset (it will boot using vbank0) + +NAND boot with 2 Stage boot loader +---------------------------------- +PBL initialise the internal SRAM and copy SPL(160KB) in SRAM. +SPL further initialise DDR using SPD and environment variables and copy +u-boot(768 KB) from flash to DDR. +Finally SPL transer control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + + Run time view of SPL framework during boot :- + ----------------------------------------------- + Area | Address | +----------------------------------------------- + Secure boot | 0xFFFC0000 (32KB) | + headers | | + ----------------------------------------------- + GD, BD | 0xFFFC8000 (4KB) | + ----------------------------------------------- + ENV | 0xFFFC9000 (8KB) | + ----------------------------------------------- + HEAP | 0xFFFCB000 (30KB) | + ----------------------------------------------- + STACK | 0xFFFD8000 (22KB) | + ----------------------------------------------- + U-boot SPL | 0xFFFD8000 (160KB) | + ----------------------------------------------- + +NAND Flash memory Map on T104xRDB +------------------------------------------ + Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x180000 0x19FFFF u-boot env 128KB +0x280000 0x29FFFF FMAN Ucode 128KB +0x380000 0x39FFFF QE Firmware 128KB + +SD Card memory Map on T104xRDB +------------------------------------------ + Block #blocks Definition Size +0x008 2048 u-boot 1MB +0x800 0024 u-boot env 8KB +0x820 0256 FMAN Ucode 128KB +0x920 0256 QE Firmware 128KB + +SPI Flash memory Map on T104xRDB +------------------------------------------ + Start End Definition Size +0x000000 0x0FFFFF u-boot 1MB +0x100000 0x101FFF u-boot env 8KB +0x110000 0x12FFFF FMAN Ucode 128KB +0x130000 0x14FFFF QE Firmware 128KB + +Please note QE Firmware is only valid for T1040RDB + + +Switch Settings: (ON is 0, OFF is 1) +=============== +NAND boot SW setting: +SW1: 10001000 +SW2: 00111001 +SW3: 11110001 + +SPI boot SW setting: +SW1: 00100010 +SW2: 10111001 +SW3: 11100001 + +SD boot SW setting: +SW1: 00100000 +SW2: 00111001 +SW3: 11100001 diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c new file mode 100644 index 0000000000..df0e348d4a --- /dev/null +++ b/board/freescale/t104xrdb/cpld.c @@ -0,0 +1,112 @@ +/** + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include "cpld.h" + +u8 cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +void cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + u8 reg = CPLD_READ(flash_ctl_status); + + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; + + CPLD_WRITE(flash_ctl_status, reg); + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); + printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); + printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); + printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); + printf("int_status = 0x%02x\n", CPLD_READ(int_status)); + printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); + printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); + printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); + printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); + printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); + printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); + printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1)); + printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2)); + putc('\n'); +} +#endif + +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_set_defbank(); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, + "Reset the board or alternate bank", + "reset - hard reset to default bank\n" + "cpld reset altbank - reset to alternate bank\n" +#ifdef DEBUG + "cpld dump - display the CPLD registers\n" +#endif + ); diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h new file mode 100644 index 0000000000..0da9a0159b --- /dev/null +++ b/board/freescale/t104xrdb/cpld.h @@ -0,0 +1,40 @@ +/** + * Copyright 2013 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl1; /* 0x10 - Reset control Register1 */ + u8 reset_ctl2; /* 0x11 - Reset control Register2 */ + u8 int_status; /* 0x12 - Interrupt status Register */ + u8 flash_ctl_status; /* 0x13 - Flash control and status register */ + u8 fan_ctl_status; /* 0x14 - Fan control and status register */ + u8 led_ctl_status; /* 0x15 - LED control and status register */ + u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ + u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ + u8 boot_override; /* 0x18 - Boot override register */ + u8 boot_config1; /* 0x19 - Boot config override register*/ + u8 boot_config2; /* 0x1A - Boot config override register*/ +} cpld_data_t; + + +/* Pointer to the CPLD register set */ + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value)\ + cpld_write(offsetof(struct cpld_data, reg), value) diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 57d0f9cfd8..34c9224adb 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -113,6 +113,7 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); @@ -120,6 +121,8 @@ phys_size_t initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 0188fd4090..63e5f900da 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -41,6 +41,7 @@ int board_eth_init(bd_t *bis) /* T1040RDB only supports SGMII on DTSEC3 */ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_SGMII1_PHY_ADDR); + break; #endif case PHY_INTERFACE_MODE_RGMII: if (FM1_DTSEC4 == i) diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c new file mode 100644 index 0000000000..c628c95f2d --- /dev/null +++ b/board/freescale/t104xrdb/spl.c @@ -0,0 +1,122 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; +#ifdef CONFIG_SPL_NAND_BOOT + u32 porsr1, pinctl; +#endif + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#ifdef CONFIG_SPL_NAND_BOOT + /* + * There is T1040 SoC issue where NOR, FPGA are inaccessible during + * NAND boot because IFC signals > IFC_AD7 are not enabled. + * This workaround changes RCW source to make all signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#endif + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + puts("\n\n"); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t104xrdb/t1040_rcw.cfg b/board/freescale/t104xrdb/t1040_rcw.cfg new file mode 100644 index 0000000000..3300c184a1 --- /dev/null +++ b/board/freescale/t104xrdb/t1040_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 80000002 e8106000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042_rcw.cfg b/board/freescale/t104xrdb/t1042_rcw.cfg new file mode 100644 index 0000000000..a3ea8ada56 --- /dev/null +++ b/board/freescale/t104xrdb/t1042_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +06000002 00400002 e8106000 01000000 +00000000 00000000 00000000 00030810 +00000000 01fe0a06 00000000 00000000 diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg new file mode 100644 index 0000000000..7b9e9b05f7 --- /dev/null +++ b/board/freescale/t104xrdb/t104x_pbi.cfg @@ -0,0 +1,26 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 6e29d64107..fb5b84940e 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -17,16 +17,30 @@ #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> +#include <asm/mpc85xx_gpio.h> #include "t104xrdb.h" +#include "cpld.h" DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; + u8 sw; printf("Board: %sRDB\n", cpu->name); + printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", + CPLD_READ(hw_ver), CPLD_READ(sw_ver)); + + sw = CPLD_READ(flash_ctl_status); + sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + + if (sw <= 7) + printf("vBank: %d\n", sw); + else + printf("Unsupported Bank=%x\n", sw); + return 0; } @@ -91,3 +105,12 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); #endif } + +#ifdef CONFIG_DEEP_SLEEP +void board_mem_sleep_setup(void) +{ + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 84f97a41e3..95c15aa596 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -53,6 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -82,6 +83,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -102,6 +104,16 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #endif + +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 12, BOOKE_PAGESZ_1G, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile index 947b7f7324..6cb72c9fd5 100644 --- a/board/freescale/t208xqds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -4,11 +4,16 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-$(CONFIG_T2080QDS) += t208xqds.o obj-$(CONFIG_T2080QDS) += eth_t208xqds.o obj-$(CONFIG_T2081QDS) += t208xqds.o obj-$(CONFIG_T2081QDS) += eth_t208xqds.o obj-$(CONFIG_PCI) += pci.o +endif + obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c index ed1334d985..3348971b01 100644 --- a/board/freescale/t208xqds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -107,13 +107,16 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif - puts(" DDR: "); return dram_size; } diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c new file mode 100644 index 0000000000..a71c617121 --- /dev/null +++ b/board/freescale/t208xqds/spl.c @@ -0,0 +1,137 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> +#include "../common/qixis.h" +#include "t208xqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index 62cd11033a..8d602989b2 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -65,6 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -110,6 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -141,6 +143,11 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile index 092c9ff0dc..9605f8b606 100644 --- a/board/freescale/t208xrdb/Makefile +++ b/board/freescale/t208xrdb/Makefile @@ -4,10 +4,15 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-$(CONFIG_T2080RDB) += t208xrdb.o obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o obj-$(CONFIG_T2080RDB) += cpld.o obj-$(CONFIG_PCI) += pci.o +endif + obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README index 0012c6cb40..24484cd0ff 100644 --- a/board/freescale/t208xrdb/README +++ b/board/freescale/t208xrdb/README @@ -67,7 +67,7 @@ T2080PCIe-RDB board Overview - One PCIe x2 end-point device (C293 Crypto co-processor) - IFC/Local Bus - NOR: 128MB 16-bit NOR Flash - - NAND: 512MB 8-bit NAND flash + - NAND: 1GB 8-bit NAND flash - CPLD: for system controlling with programable header on-board - SATA - Two SATA 2.0 onnectors on-board @@ -120,7 +120,7 @@ Start Address End Address Definition Max size 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB -0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB 0xE8000000 0xE801FFFF RCW (current bank) 128KB @@ -146,7 +146,8 @@ Software configurations and board settings ------------------------------------------ 1. NOR boot: a. build NOR boot image - $ make T2080RDB + $ make T2080RDB_config + $ make b. program u-boot.bin image to NOR flash => tftp 1000000 u-boot.bin => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize @@ -155,18 +156,18 @@ Software configurations and board settings Switching between default bank and alternate bank on NOR flash To change boot source to vbank4: via software: run command 'cpld reset altbank' in u-boot. - via DIP-switch: set SW3[5:7] = '011' + via DIP-switch: set SW3[5:7] = '100' To change boot source to vbank0: via software: run command 'cpld reset' in u-boot. - via DIP-Switch: set SW3[5:7] = '111' + via DIP-Switch: set SW3[5:7] = '000' 2. NAND Boot: a. build PBL image for NAND boot $ make T2080RDB_NAND_config - $ make u-boot.pbl - b. program u-boot.pbl to NAND flash - => tftp 1000000 u-boot.pbl + $ make + b. program u-boot-with-spl-pbl.bin to NAND flash + => tftp 1000000 u-boot-with-spl-pbl.bin => nand erase 0 d0000 => nand write 1000000 0 $filesize set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot @@ -174,9 +175,9 @@ Software configurations and board settings 3. SPI Boot: a. build PBL image for SPI boot $ make T2080RDB_SPIFLASH_config - $ make u-boot.pbl - b. program u-boot.pbl to SPI flash - => tftp 1000000 u-boot.pbl + $ make + b. program u-boot-with-spl-pbl.bin to SPI flash + => tftp 1000000 u-boot-with-spl-pbl.bin => sf probe 0 => sf erase 0 d0000 => sf write 1000000 0 $filesize @@ -185,13 +186,68 @@ Software configurations and board settings 4. SD Boot: a. build PBL image for SD boot $ make T2080RDB_SDCARD_config - $ make u-boot.pbl - b. program u-boot.pbl to TF card - => tftp 1000000 u-boot.pbl - => mmc write 1000000 8 1650 + $ make + b. program u-boot-with-spl-pbl.bin to micro-SD/TF card + => tftp 1000000 u-boot-with-spl-pbl.bin + => mmc write 1000000 8 0x800 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot +2-stage NAND/SPI/SD boot loader +------------------------------- +PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. +SPL further initializes DDR using SPD and environment variables +and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. +Finally SPL transers control to u-boot for futher booting. + +SPL has following features: + - Executes within 256K + - No relocation required + +Run time view of SPL framework +------------------------------------------------- +|Area | Address | +------------------------------------------------- +|SecureBoot header | 0xFFFC0000 (32KB) | +------------------------------------------------- +|GD, BD | 0xFFFC8000 (4KB) | +------------------------------------------------- +|ENV | 0xFFFC9000 (8KB) | +------------------------------------------------- +|HEAP | 0xFFFCB000 (50KB) | +------------------------------------------------- +|STACK | 0xFFFD8000 (22KB) | +------------------------------------------------- +|U-boot SPL | 0xFFFD8000 (160KB) | +------------------------------------------------- + +NAND Flash memory Map on T2080RDB +-------------------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB (2 blocks) +0x100000 0x17FFFF u-boot env 512KB (1 block) +0x180000 0x1FFFFF FMAN ucode 512KB (1 block) +0x200000 0x27FFFF CS4315 ucode 512KB (1 block) + + +Micro SD Card memory Map on T2080RDB +---------------------------------------------------- +Block #blocks Definition Size +0x008 2048 u-boot img 1MB +0x800 0016 u-boot env 8KB +0x820 0128 FMAN ucode 64KB +0x8a0 0512 CS4315 ucode 256KB + + +SPI Flash memory Map on T2080RDB +---------------------------------------------------- +Start End Definition Size +0x000000 0x0FFFFF u-boot img 1MB +0x100000 0x101FFF u-boot env 8KB +0x110000 0x11FFFF FMAN ucode 64KB +0x120000 0x15FFFF CS4315 ucode 256KB + + How to update the ucode of Cortina CS4315/CS4340 10G PHY -------------------------------------------------------- => tftp 1000000 CS4315-CS4340-PHY-ucode.txt diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h index 4cee4e55cf..3f1533888d 100644 --- a/board/freescale/t208xrdb/cpld.h +++ b/board/freescale/t208xrdb/cpld.h @@ -35,8 +35,8 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_LBMAP_MASK 0x3F #define CPLD_BANK_SEL_MASK 0x07 #define CPLD_BANK_OVERRIDE 0x40 -#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */ -#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */ +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 #define CPLD_BOOT_SEL 0x80 diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c index 01e917398f..8a26276273 100644 --- a/board/freescale/t208xrdb/ddr.c +++ b/board/freescale/t208xrdb/ddr.c @@ -100,13 +100,15 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - - puts(" DDR: "); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c new file mode 100644 index 0000000000..9ae2b1e863 --- /dev/null +++ b/board/freescale/t208xrdb/spl.c @@ -0,0 +1,107 @@ +/* Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <spi_flash.h> + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#if defined(CONFIG_SPL_MMC_BOOT) + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_SPI_BOOT + spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index f3fec2aa6e..265c1f97dd 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -44,7 +44,7 @@ int checkboard(void) puts("NAND\n"); } else { reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); - printf("NOR vBank%d\n", ~reg & 0x7); + printf("NOR vBank%d\n", reg); } #endif diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index 085d9f5c6a..2ebea36a5c 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -65,6 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -110,6 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -140,7 +142,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 18, BOOKE_PAGESZ_1M, 1), #endif -#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 19, BOOKE_PAGESZ_2G, 1) diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile index 2b1f7aa301..4e8e5cb8e9 100644 --- a/board/freescale/t4qds/Makefile +++ b/board/freescale/t4qds/Makefile @@ -4,10 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-$(CONFIG_T4240QDS) += t4240qds.o obj-$(CONFIG_T4240EMU) += t4240emu.o -obj-y += ddr.o obj-$(CONFIG_T4240QDS)+= eth.o obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 7586cc3c4b..7abd38def1 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -117,11 +117,15 @@ phys_size_t initdram(int board_type) puts("Initializing....using SPD\n"); +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c new file mode 100644 index 0000000000..0c6156e7f0 --- /dev/null +++ b/board/freescale/t4qds/spl.c @@ -0,0 +1,141 @@ +/* Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/spl.h> +#include <malloc.h> +#include <ns16550.h> +#include <nand.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include "../common/qixis.h" +#include "t4240qds_qixis.h" + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, ccb_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#ifdef CONFIG_SPL_NAND_BOOT + u32 porsr1, pinctl; +#endif + +#ifdef CONFIG_SPL_NAND_BOOT + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); +#endif + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + ccb_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + ccb_clk / 16 / CONFIG_BAUDRATE); + +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_NAND_BOOT) + puts("\nNAND boot...\n"); +#endif + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); +#endif + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + i2c_init_all(); + + gd->ram_size = initdram(0); + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg index c598fb5afd..6126266a96 100644 --- a/board/freescale/t4qds/t4_pbi.cfg +++ b/board/freescale/t4qds/t4_pbi.cfg @@ -13,20 +13,6 @@ 09000d00 00000000 09000d04 fff80000 09000d08 81000012 -#workaround for IFC bus speed -091241c0 f03f3f3f -091241c4 ff003f3f -09124010 00000101 -09124130 0000000c -#workaround for SERDES A-006031 -090ea000 064740e6 -090ea020 064740e6 -090eb000 064740e6 -090eb020 064740e6 -090ec000 064740e6 -090ec020 064740e6 -090ed000 064740e6 -090ed020 064740e6 #Configure alternate space 09000010 00000000 09000014 ff000000 diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg index 74df01a70c..3e56817204 100644 --- a/board/freescale/t4qds/t4_rcw.cfg +++ b/board/freescale/t4qds/t4_rcw.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 010e0100 #serdes protocol 1_28_6_12 -120c0019 0c101915 00000000 00000000 -04383063 30548c00 6c020000 1d000000 +16070019 18101916 00000000 00000000 +04383060 30548c00 ec020000 f5000000 00000000 ee0000ee 00000000 000307fc -00000000 00000000 00000000 00000020 +00000000 00000000 00000000 00000028 diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index b701e75209..1e4d096f5f 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), - +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -105,6 +105,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -136,6 +137,11 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); |