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-rw-r--r--board/freescale/common/fman.c2
-rw-r--r--board/freescale/common/fsl_validate.c34
-rw-r--r--board/freescale/ls1021aqds/ls1021aqds.c49
-rw-r--r--board/freescale/ls1021atwr/ls1021atwr.c42
-rw-r--r--board/freescale/ls1043aqds/ddr.c9
-rw-r--r--board/freescale/ls1043ardb/MAINTAINERS5
-rw-r--r--board/freescale/ls1043ardb/ddr.c24
-rw-r--r--board/freescale/ls1043ardb/ls1043ardb.c28
-rw-r--r--board/freescale/ls2080a/ddr.c15
-rw-r--r--board/freescale/ls2080a/ls2080a.c17
-rw-r--r--board/freescale/ls2080aqds/ddr.c31
-rw-r--r--board/freescale/ls2080aqds/ls2080aqds.c17
-rw-r--r--board/freescale/ls2080ardb/ddr.c31
-rw-r--r--board/freescale/ls2080ardb/ls2080ardb.c17
14 files changed, 161 insertions, 160 deletions
diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c
index 26cf5175c7..b5025ab14e 100644
--- a/board/freescale/common/fman.c
+++ b/board/freescale/common/fman.c
@@ -52,6 +52,8 @@ int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
if (!ph)
return -FDT_ERR_BADPHANDLE;
+ ph = cpu_to_fdt32(ph);
+
offset = fdt_node_offset_by_compat_reg(fdt, compat, addr);
if (offset < 0)
return offset;
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 73b6718db9..b510c71c40 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -15,7 +15,7 @@
#include <u-boot/rsa-mod-exp.h>
#include <hash.h>
#include <fsl_secboot_err.h>
-#ifndef CONFIG_MPC85xx
+#ifdef CONFIG_LS102XA
#include <asm/arch/immap_ls102xa.h>
#endif
@@ -99,7 +99,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
- if (memcmp((u8 *)csf_hdr_addr, barker_code, ESBC_BARKER_LEN))
+ if (memcmp((u8 *)(uintptr_t)csf_hdr_addr,
+ barker_code, ESBC_BARKER_LEN))
return -1;
*csf_addr = csf_hdr_addr;
@@ -117,7 +118,7 @@ static int get_ie_info_addr(u32 *ie_addr)
if (get_csf_base_addr(&csf_addr, &flash_base_addr))
return -1;
- hdr = (struct fsl_secboot_img_hdr *)csf_addr;
+ hdr = (struct fsl_secboot_img_hdr *)(uintptr_t)csf_addr;
/* For SoC's with Trust Architecture v1 with corenet bus
* the sg table field in CSF header has absolute address
@@ -130,7 +131,7 @@ static int get_ie_info_addr(u32 *ie_addr)
(((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
flash_base_addr);
#else
- sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr +
+ sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr +
(u32)hdr->psgtable);
#endif
@@ -379,8 +380,8 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
#ifdef CONFIG_KEY_REVOCATION
if (check_srk(img)) {
ret = algo->hash_update(algo, ctx,
- (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off),
- img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
+ (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off),
+ img->hdr.len_kr.num_srk * sizeof(struct srk_table), 1);
srk = 1;
}
#endif
@@ -438,8 +439,8 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
#ifdef CONFIG_KEY_REVOCATION
if (check_srk(img)) {
ret = algo->hash_update(algo, ctx,
- (u8 *)(img->ehdrloc + img->hdr.srk_tbl_off),
- img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0);
+ (u8 *)(uintptr_t)(img->ehdrloc + img->hdr.srk_tbl_off),
+ img->hdr.len_kr.num_srk * sizeof(struct srk_table), 0);
key_hash = 1;
}
#endif
@@ -454,8 +455,13 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
return ret;
/* Update hash for actual Image */
+#ifdef CONFIG_ESBC_ADDR_64BIT
ret = algo->hash_update(algo, ctx,
- (u8 *)img->hdr.pimg, img->hdr.img_size, 1);
+ (u8 *)(uintptr_t)img->hdr.pimg64, img->hdr.img_size, 1);
+#else
+ ret = algo->hash_update(algo, ctx,
+ (u8 *)(uintptr_t)img->hdr.pimg, img->hdr.img_size, 1);
+#endif
if (ret)
return ret;
@@ -533,7 +539,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
{
char buf[20];
struct fsl_secboot_img_hdr *hdr = &img->hdr;
- void *esbc = (u8 *)img->ehdrloc;
+ void *esbc = (u8 *)(uintptr_t)img->ehdrloc;
u8 *k, *s;
#ifdef CONFIG_KEY_REVOCATION
u32 ret;
@@ -549,7 +555,11 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN))
return ERROR_ESBC_CLIENT_HEADER_BARKER;
+#ifdef CONFIG_ESBC_ADDR_64BIT
+ sprintf(buf, "%llx", hdr->pimg64);
+#else
sprintf(buf, "%x", hdr->pimg);
+#endif
setenv("img_addr", buf);
if (!hdr->img_size)
@@ -594,7 +604,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img)
if (!key_found && check_ie(img)) {
if (get_ie_info_addr(&img->ie_addr))
return ERROR_IE_TABLE_NOT_FOUND;
- ie_info = (struct ie_key_info *)img->ie_addr;
+ ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr;
if (ie_info->num_keys == 0 || ie_info->num_keys > 32)
return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY;
@@ -748,7 +758,7 @@ int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc,
hdr = &img->hdr;
img->ehdrloc = addr;
- esbc = (u8 *)img->ehdrloc;
+ esbc = (u8 *)(uintptr_t)img->ehdrloc;
memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr));
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index d889ad50fd..be3358a564 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -11,6 +11,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_sata.h>
#include <hwconfig.h>
@@ -140,17 +141,6 @@ unsigned long get_board_ddr_clk(void)
return 66666666;
}
-unsigned int get_soc_major_rev(void)
-{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- unsigned int svr, major;
-
- svr = in_be32(&gur->svr);
- major = SVR_MAJ(svr);
-
- return major;
-}
-
int select_i2c_ch_pca9547(u8 ch)
{
int ret;
@@ -193,8 +183,6 @@ int board_mmc_init(bd_t *bis)
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
- unsigned int major;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
@@ -205,40 +193,7 @@ int board_early_init_f(void)
init_early_memctl_regs();
#endif
-#ifdef CONFIG_FSL_QSPI
- out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
-#endif
-
-#ifdef CONFIG_FSL_DCU_FB
- out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
-#endif
-
- /* Configure Little endian for SAI, ASRC and SPDIF */
- out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
-
- /*
- * Enable snoop requests and DVM message requests for
- * Slave insterface S4 (A7 core cluster)
- */
- out_le32(&cci->slave[4].snoop_ctrl,
- CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
-
- major = get_soc_major_rev();
- if (major == SOC_MAJOR_VER_1_0) {
- /*
- * Set CCI-400 Slave interface S1, S2 Shareable Override
- * Register All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-
- /* Workaround for the issue that DDR could not respond to
- * barrier transaction which is generated by executing DSB/ISB
- * instruction. Set CCI-400 control override register to
- * terminate the barrier transaction. After DDR is initialized,
- * allow barrier transaction to DDR again */
- out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
- }
+ arch_soc_init();
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 4918c1192e..8eaff5f0ce 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -12,6 +12,7 @@
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/ls102xa_stream_id.h>
#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_sata.h>
#include <hwconfig.h>
#include <mmc.h>
@@ -138,17 +139,6 @@ int checkboard(void)
return 0;
}
-unsigned int get_soc_major_rev(void)
-{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- unsigned int svr, major;
-
- svr = in_be32(&gur->svr);
- major = SVR_MAJ(svr);
-
- return major;
-}
-
void ddrmc_init(void)
{
struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
@@ -394,8 +384,6 @@ conflict:
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
- unsigned int major;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
@@ -407,33 +395,7 @@ int board_early_init_f(void)
init_early_memctl_regs();
#endif
-#ifdef CONFIG_FSL_DCU_FB
- out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
-#endif
-
-#ifdef CONFIG_FSL_QSPI
- out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
-#endif
-
- /* Configure Little endian for SAI, ASRC and SPDIF */
- out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
-
- /*
- * Enable snoop requests and DVM message requests for
- * Slave insterface S4 (A7 core cluster)
- */
- out_le32(&cci->slave[4].snoop_ctrl,
- CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
-
- major = get_soc_major_rev();
- if (major == SOC_MAJOR_VER_1_0) {
- /*
- * Set CCI-400 Slave interface S1, S2 Shareable Override
- * Register All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- }
+ arch_soc_init();
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot()) {
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index 705e3843f4..42d906824a 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -126,6 +126,15 @@ phys_size_t initdram(int board_type)
void dram_init_banksize(void)
{
+ /*
+ * gd->secure_ram tracks the location of secure memory.
+ * It was set as if the memory starts from 0.
+ * The address needs to add the offset of its bank.
+ */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
}
diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS
index efca5bf245..84ffb638d8 100644
--- a/board/freescale/ls1043ardb/MAINTAINERS
+++ b/board/freescale/ls1043ardb/MAINTAINERS
@@ -7,3 +7,8 @@ F: include/configs/ls1043ardb.h
F: configs/ls1043ardb_defconfig
F: configs/ls1043ardb_nand_defconfig
F: configs/ls1043ardb_sdcard_defconfig
+
+LS1043A_SECURE_BOOT BOARD
+M: Aneesh Bansal <aneesh.bansal@freescale.com>
+S: Maintained
+F: configs/ls1043ardb_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index b181579e8e..11bc0f24d9 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -186,6 +186,28 @@ phys_size_t initdram(int board_type)
void dram_init_banksize(void)
{
+ /*
+ * gd->secure_ram tracks the location of secure memory.
+ * It was set as if the memory starts from 0.
+ * The address needs to add the offset of its bank.
+ */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+ gd->bd->bi_dram[1].size = gd->ram_size -
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->secure_ram = gd->bd->bi_dram[1].start +
+ gd->secure_ram -
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+ } else {
+ gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+ }
}
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index cdd50d6d18..c8f723a108 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -18,6 +18,8 @@
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
+#include <environment.h>
+#include <fsl_sec.h>
#include "cpld.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -123,13 +125,37 @@ int config_board_mux(void)
int misc_init_r(void)
{
config_board_mux();
-
+#ifdef CONFIG_SECURE_BOOT
+ /* In case of Secure Boot, the IBR configures the SMMU
+ * to allow only Secure transactions.
+ * SMMU must be reset in bypass mode.
+ * Set the ClientPD bit and Clear the USFCFG Bit
+ */
+ u32 val;
+ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_SCR0, val);
+ val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+ out_le32(SMMU_NSCR0, val);
+#endif
+#ifdef CONFIG_FSL_CAAM
+ return sec_init();
+#endif
return 0;
}
#endif
int ft_board_setup(void *blob, bd_t *bd)
{
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ /* fixup DT for the two DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c
index 47d73ef75a..56c5d96e99 100644
--- a/board/freescale/ls2080a/ddr.c
+++ b/board/freescale/ls2080a/ddr.c
@@ -175,14 +175,29 @@ void dram_init_banksize(void)
phys_size_t dp_ddr_size;
#endif
+ /*
+ * gd->secure_ram tracks the location of secure memory.
+ * It was set as if the memory starts from 0.
+ * The address needs to add the offset of its bank.
+ */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->secure_ram = gd->bd->bi_dram[1].start +
+ gd->secure_ram -
+ CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
}
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c
index 827fbf0835..7bce8b0772 100644
--- a/board/freescale/ls2080a/ls2080a.c
+++ b/board/freescale/ls2080a/ls2080a.c
@@ -68,23 +68,6 @@ int arch_misc_init(void)
}
#endif
-unsigned long get_dram_size_to_hide(void)
-{
- unsigned long dram_to_hide = 0;
-
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
- dram_to_hide += debug_server_get_dram_block_size();
-#endif
-
-/* Carve the MC private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_MC_ENET
- dram_to_hide += mc_get_dram_block_size();
-#endif
-
- return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
-}
-
int board_eth_init(bd_t *bis)
{
int error = 0;
diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c
index ae681de35e..9fb5e112db 100644
--- a/board/freescale/ls2080aqds/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@@ -134,10 +134,18 @@ found:
popts->zq_en = 1;
if (ddr_freq < 2350) {
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
- DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
- DDR_CDR2_VREF_RANGE_2;
+ if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
+ /* four chip-selects */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
+ popts->twot_en = 1; /* enable 2T timing */
+ } else {
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+ DDR_CDR2_VREF_RANGE_2;
+ }
} else {
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
@@ -167,14 +175,29 @@ void dram_init_banksize(void)
phys_size_t dp_ddr_size;
#endif
+ /*
+ * gd->secure_ram tracks the location of secure memory.
+ * It was set as if the memory starts from 0.
+ * The address needs to add the offset of its bank.
+ */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->secure_ram = gd->bd->bi_dram[1].start +
+ gd->secure_ram -
+ CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
}
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 1f990720a8..aa256a225b 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -253,23 +253,6 @@ int arch_misc_init(void)
}
#endif
-unsigned long get_dram_size_to_hide(void)
-{
- unsigned long dram_to_hide = 0;
-
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
- dram_to_hide += debug_server_get_dram_block_size();
-#endif
-
-/* Carve the MC private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_MC_ENET
- dram_to_hide += mc_get_dram_block_size();
-#endif
-
- return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
-}
-
#ifdef CONFIG_FSL_MC_ENET
void fdt_fixup_board_enet(void *fdt)
{
diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c
index ae681de35e..6c191738ec 100644
--- a/board/freescale/ls2080ardb/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@@ -134,10 +134,18 @@ found:
popts->zq_en = 1;
if (ddr_freq < 2350) {
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
- DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
- DDR_CDR2_VREF_RANGE_2;
+ if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
+ /* four chip-selects */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
+ popts->twot_en = 1; /* enable 2T timing */
+ } else {
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+ DDR_CDR2_VREF_RANGE_2;
+ }
} else {
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
@@ -167,14 +175,29 @@ void dram_init_banksize(void)
phys_size_t dp_ddr_size;
#endif
+ /*
+ * gd->secure_ram tracks the location of secure memory.
+ * It was set as if the memory starts from 0.
+ * The address needs to add the offset of its bank.
+ */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
gd->bd->bi_dram[1].size = gd->ram_size -
CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->secure_ram = gd->bd->bi_dram[1].start +
+ gd->secure_ram -
+ CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
} else {
gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
+ gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
}
#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 2ae9d6cf45..c63b639625 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -219,23 +219,6 @@ int arch_misc_init(void)
}
#endif
-unsigned long get_dram_size_to_hide(void)
-{
- unsigned long dram_to_hide = 0;
-
-/* Carve the Debug Server private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_DEBUG_SERVER
- dram_to_hide += debug_server_get_dram_block_size();
-#endif
-
-/* Carve the MC private DRAM block from the end of DRAM */
-#ifdef CONFIG_FSL_MC_ENET
- dram_to_hide += mc_get_dram_block_size();
-#endif
-
- return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
-}
-
#ifdef CONFIG_FSL_MC_ENET
void fdt_fixup_board_enet(void *fdt)
{
generated by cgit (git 2.34.1) at 2024-12-27 20:48:05 +0000