diff options
Diffstat (limited to 'board/logicpd/imx6')
| -rw-r--r-- | board/logicpd/imx6/MAINTAINERS | 3 | ||||
| -rw-r--r-- | board/logicpd/imx6/README | 48 | ||||
| -rw-r--r-- | board/logicpd/imx6/imx6logic.c | 72 |
3 files changed, 122 insertions, 1 deletions
diff --git a/board/logicpd/imx6/MAINTAINERS b/board/logicpd/imx6/MAINTAINERS index 5db7d2cadd..20ec5918e4 100644 --- a/board/logicpd/imx6/MAINTAINERS +++ b/board/logicpd/imx6/MAINTAINERS @@ -4,3 +4,6 @@ S: Maintained F: board/logicpd/imx6/ F: include/configs/imx6_logic.h F: configs/imx6q_logic_defconfig +F: arch/arm/dts/imx6-logicpd-baseboard.dtsi +F: arch/arm/dts/imx6-logicpd-som.dtsi +F: arch/arm/dts/imx6q-logicpd.dts diff --git a/board/logicpd/imx6/README b/board/logicpd/imx6/README index df43b55d6b..26d053a32c 100644 --- a/board/logicpd/imx6/README +++ b/board/logicpd/imx6/README @@ -22,8 +22,17 @@ To build U-Boot for the Dual and Quad variants: Flashing U-Boot into the SD card -------------------------------- +U-Boot is now building with SPL enabled which means there are two files to +load into the SD card. Make sure the card is formatted with at least two +partitions with the first partition being FAT32. First copy u-boot-dtb.img +to the first partition then burn SPL to the SD card with dd. +The SPL portion is programmed into a certain location for use by the internal +bootROM and it cannot be changed. The following instructions assume the SD +card is located as /dev/sdb. + + cp u-boot-dtb.img /dev/media/logic/boot + sudo dd if=SPL of=/dev/sdb bs=1k seek=1 oflag=sync status=none && sync -See README.imximage for details on booting from SD Flashing U-Boot into NAND ------------------------- @@ -32,6 +41,43 @@ with: kobs-ng init -v -x u-boot-dtb.imx + +Using Falcon Mode +----------------- +With Falcon Mode enabled, U-Boot can be bypassed by having SPL directly load +the kernel. The device tree, Kernel and boot args must first be configured, +and stored to a file on the micro SD card called 'args' +The kernel uImage is built with LOAD_ADDR=0x12000000 and the device tree is +assummed to be imx6q-logicpd.dtb. + +By default the mmcroot is set to the baseboard. + + # Establish bootargs + run mmcargs + + # Load Linux Kernel uImage + fatload mmc 1 $loadaddr uImage + + # Load Device Tree + run loadfdt + + # Setup the blob that will get passed to the kernel + spl export fdt ${loadaddr} - ${fdt_addr_r} + + # Note the starting and ending address of the updated device tree. + # for this example: + # Loading Device Tree to 1ffdf000, end 1fff038b ... OK + # Notice that 0x1fff038b - 1ffdf000 = 0x1138b + # now Add 1, so the length is 0x1138c. + + fatwrite mmc 1 0x1ffdf000 args 0x1138c + + # Reset the board and it will bypass U-Boot and SPL will directly boot + # the uImage + +To interrupt the boot sequence and force U-Boot to load, hold the 'c' button +while starting. + Additional Support Documentation can be found at: https://support.logicpd.com/ diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c index ce1c8a5d6b..89cf53c24d 100644 --- a/board/logicpd/imx6/imx6logic.c +++ b/board/logicpd/imx6/imx6logic.c @@ -60,6 +60,7 @@ static iomux_v3_cfg_t const uart3_pads[] = { MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#ifndef CONFIG_SPL_BUILD static void fixup_enet_clock(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -108,6 +109,7 @@ static void fixup_enet_clock(void) dm_gpio_set_value(&reset, 1); mdelay(50); } +#endif static void setup_iomux_uart(void) { @@ -158,7 +160,9 @@ int overwrite_console(void) int board_early_init_f(void) { +#ifndef CONFIG_SPL_BUILD fixup_enet_clock(); +#endif setup_iomux_uart(); setup_nand_pins(); return 0; @@ -200,6 +204,74 @@ int spl_start_uboot(void) } #endif +/* SD interface */ +#define USDHC_PAD_CTRL \ + (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC1_BASE_ADDR}, /* SOM */ + {USDHC2_BASE_ADDR} /* Baseboard */ +}; + +int board_mmc_init(bd_t *bis) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1-SOM + * 0x2 SD2-Baseboard + */ + + reg &= 0x3; /* Only care about bottom 2 bits */ + + switch (reg) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[1].sdhc_clk; + break; + } + + return fsl_esdhc_initialize(bis, &usdhc_cfg[reg]); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} +#endif + static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |