3 files changed, 134 insertions, 0 deletions
diff --git a/board/mscc/jr2/Kconfig b/board/mscc/jr2/Kconfig
new file mode 100644
index 0000000000..68a2de8ca7
--- /dev/null
+++ b/board/mscc/jr2/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+	default "mscc"
+
+if SOC_JR2
+
+config SYS_BOARD
+	default "jr2"
+
+config SYS_CONFIG_NAME
+	default "jr2"
+
+endif
+
diff --git a/board/mscc/jr2/Makefile b/board/mscc/jr2/Makefile
new file mode 100644
index 0000000000..c1db2a9045
--- /dev/null
+++ b/board/mscc/jr2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_JR2)	:= jr2.o
+
diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c
new file mode 100644
index 0000000000..eac4dcaa10
--- /dev/null
+++ b/board/mscc/jr2/jr2.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <led.h>
+
+enum {
+	BOARD_TYPE_PCB110 = 0xAABBCE00,
+	BOARD_TYPE_PCB111,
+	BOARD_TYPE_PCB112,
+};
+
+int board_early_init_r(void)
+{
+	/* Prepare SPI controller to be used in master mode */
+	writel(0, BASE_CFG + ICPU_SW_MODE);
+	clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
+			ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
+			ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
+
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+
+	/* LED setup */
+	if (IS_ENABLED(CONFIG_LED))
+		led_default_state();
+
+	return 0;
+}
+
+static void vcoreiii_gpio_set_alternate(int gpio, int mode)
+{
+	u32 mask;
+	u32 val0, val1;
+	void __iomem *reg0, *reg1;
+
+	if (gpio < 32) {
+		mask = BIT(gpio);
+		reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(0);
+		reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT(1);
+	} else {
+		gpio -= 32;
+		mask = BIT(gpio);
+		reg0 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(0);
+		reg1 = BASE_DEVCPU_GCB + GPIO_GPIO_ALT1(1);
+	}
+	val0 = readl(reg0);
+	val1 = readl(reg1);
+	if (mode == 1) {
+		writel(val0 | mask, reg0);
+		writel(val1 & ~mask, reg1);
+	} else if (mode == 2) {
+		writel(val0 & ~mask, reg0);
+		writel(val1 | mask, reg1);
+	} else if (mode == 3) {
+		writel(val0 | mask, reg0);
+		writel(val1 | mask, reg1);
+	} else {
+		writel(val0 & ~mask, reg0);
+		writel(val1 & ~mask, reg1);
+	}
+}
+
+static void do_board_detect(void)
+{
+	int i;
+	u16 pval;
+
+	/* MIIM 1 + 2  MDC/MDIO */
+	for (i = 56; i < 60; i++)
+		vcoreiii_gpio_set_alternate(i, 1);
+
+	if (mscc_phy_rd(0, 0x10, 0x3, &pval) == 0 &&
+	    ((pval >> 4) & 0x3F) == 0x3c) {
+		gd->board_type = BOARD_TYPE_PCB112; /* Serval2-NID */
+	} else if (mscc_phy_rd(1, 0x0, 0x3, &pval) == 0 &&
+		   ((pval >> 4) & 0x3F) == 0x3c) {
+		gd->board_type = BOARD_TYPE_PCB110; /* Jr2-24 */
+	} else {
+		/* Fall-back */
+		gd->board_type = BOARD_TYPE_PCB111; /* Jr2-48 */
+	}
+}
+
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	if (gd->board_type == BOARD_TYPE_PCB110 &&
+	    strcmp(name, "jr2_pcb110") == 0)
+		return 0;
+
+	if (gd->board_type == BOARD_TYPE_PCB111 &&
+	    strcmp(name, "jr2_pcb111") == 0)
+		return 0;
+
+	if (gd->board_type == BOARD_TYPE_PCB112 &&
+	    strcmp(name, "serval2_pcb112") == 0)
+		return 0;
+
+	return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void)
+{
+	do_board_detect();
+	fdtdec_setup();
+
+	return 0;
+}
+#endif